Demodulation pixel incorporating majority carrier current, buried channel and high-low junction

Abstract

A demodulation pixel improves the charge transport speed and sensitivity by exploiting two effects of charge transport in silicon in order to achieve the before-mentioned optimization. The first one is a transport method based on the CCD gate principle. However, this is not limited to CCD technology, but can be realized also in CMOS technology. The charge transport in a surface or even a buried channel close to the surface is highly efficient in terms of speed, sensitivity and low trapping noise. In addition, by activating a majority carrier current flowing through the substrate, another drift field is generated below the depleted CCD channel. This drift field is located deeply in the substrate, acting as an efficient separator for deeply photo-generated electron-hole pairs. Thus, another large amount of minority carriers is transported to the diffusion nodes at high speed and detected.

Claims

1. A demodulation pixel comprising: a semiconductor substrate; a photo sensitive section in the semiconductor substrate for converting light into charge carriers; storage nodes for receiving the charge carriers; a demodulation region for transferring the charge carriers to the different storage nodes; a high-low junction underneath the photo sensitive section for directing charge carriers generated in the photo sensitive section to a surface of the semiconductor substrate for transfer to the demodulation region; and a non-uniform doping profile in the photo sensitive section for generating a lateral drift field in the photo sensitive section to transfer the charges to the demodulation region.

2. A demodulation pixel, comprising: a semiconductor substrate; a photo sensitive section in the semiconductor substrate for converting light into charge carriers; storage nodes for receiving the charge carriers; a demodulation region for transferring the charge carriers to the different storage nodes; a majority carrier current through semiconductor substrate and under the photo sensitive section that directs the charge carriers to the demodulation region.

3. A pixel as claimed in claim 2, further comprising photo gates over the photo sensitive section for generating a lateral drift field to direct the charge carriers to the demodulation region.

4. A pixel as claimed in claim 2, further comprising an n implantation region over the photo sensitive section for generating a lateral drift field in photo sensitive section that has a changing doping concentration in a direction of the demodulation region.

5. A pixel as claimed in claim 2, further comprising capacitively-coupled gates over the photo sensitive section for generating a lateral drift field to direct the charge carriers to the demodulation region.

6. A pixel as claimed in claim 2, further comprising a non-uniform doping profile in the photo sensitive section for generating a lateral drift field in the photo sensitive section to transfer the charges to the demodulation region.

7. A pixel as claimed in claim 2, further comprising a high-low junction underneath the photo sensitive section for directing charge carriers to a surface of the semiconductor substrate.

8. A pixel as claimed in claim 2, further comprising graded or gradually doped substrate for directing charge carriers to a surface of the semiconductor substrate.

9. A pixel as claimed in claim 2, further comprising two majority carrier nodes on either end of the photo sensitive section between which the majority carrier current flows.

10. A pixel as claimed in claim 9, wherein the majority carrier nodes are p-implantations in the semiconductor substrate.

11. A pixel as claimed in claim 2, further comprising a depleted implantation region in the photo sensitive section for facilitating the transport of the charge carriers to the demodulation region.

12. A pixel as claimed in claim 11, wherein the depleted implantation region is funnel shaped in the direction of the demodulation region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the accompanying drawings, reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale; emphasis has instead been placed upon illustrating the principles of the invention. Of the drawings:

(2) FIG. 1 is a schematic diagram of a demodulation pixel to which the present invention is applied in embodiments;

(3) FIG. 2 is a schematic diagram showing photo-sensitivity enhancement and fast in-pixel charge transport mechanisms;

(4) FIG. 3 shows an example for a demodulation pixel with separated detection region and demodulation region incorporating a buried channel and the n+ diffusion area;

(5) FIG. 4 shows a cross section through the detection region in which the drift field is generated by photogates;

(6) FIG. 5 shows a cross section through the detection region in which the drift field is generated by a high resistivity layer;

(7) FIG. 6 shows a cross section through the detection region in which the drift field is generated by continuous change of the doping concentration of the n implantation; so-called built-in drift fields;

(8) FIG. 7 shows a cross section through the detection region;

(9) FIG. 8 shows a cross section through the detection region in which the drift field is generated by capacitively coupled gates; and

(10) FIG. 9 is a schematic illustration showing the operation of a TOF camera using a demodulation pixel according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(11) The following description is based on the semiconductor materials with a p-type silicon substrate such that the electrons rather than holes are collected for processing. It is also possible to use n-doped silicon so that all doping and voltage relationships are swapped accordingly. Thus, the description herein is not to be understood as a limitation for using just p-doped semiconductor substrates. The same is meant for the photo-currents, which can either be electron or hole current depending on the type of doping of the semiconductor material.

(12) FIG. 1 is a schematic diagram of a demodulation pixel 100. Photons 10 impinge onto the sensitive area 110 and create electron-hole pairs 12. In general the holes are drained by the substrate and the electrons are used as the charge carriers for the signal processing and extraction of the information. The sensitive region 110 transports the electrons as fast as possible to the demodulation region 112 in order to support high (de)modulation frequencies. The output of the demodulation region is a number of charge packets into storage nodes a, b, . . . n, which correspond to the samples of the optical signal. In general, the samples are amplified and readout in circuitry 14.

(13) According to a preferred embodiment of the present invention, the photo-sensitive region is optimized in terms of sensitivity and charge transport speed. To achieve maximum photo-sensitivity and fast in-pixel charge transport at the same time, one or more of three aforementioned pixel enhancement mechanisms are exploited, which can arbitrarily be combined together.

(14) FIG. 2 is a schematic diagram showing photo-sensitivity and fast in-pixel charge transport mechanism for the sensitive region 110 of a demodulation pixel.

(15) A first mechanism incorporates a shallow doping implantation layer 210 in the substrate 101 that creates a depleted region that separates and collects photo-generated charges. Since the layer 210 is close to the semiconductor surface, it is particularly highly sensitive to optical wavelengths in the visible part of the electromagnetic spectrum but also certain fractions of charge carriers generated by long wavelength radiation, e.g. near infrared light, are collected by this layer. The lateral charge transport through this doping layer can efficiently be realized for example by photo-transparent gates 212, 214, 216, 218 on top of a silicon oxide insulating layer 220, so that the potential distribution applied to the gates 212, 214, 216, 218 is mirrored into the doping layer 210. This technique is well-known from CCD devices. Depending on the particular gate arrangement, the speed of the lateral charge transport can be optimized. Embodiments for highest transport speeds are disclosed in patent [BUE05A]. A successive gate arrangement is shown. The idea of this embodiment is that the gate widths are small and increasing voltages are applied to the gates from left to right. Due to the small gate sizes and the buried channel implantation, the voltage distribution mirrored to the channel is smeared. Finally, an almost linearly increasing potential distribution in the channel is obtained, which is essential for a fast lateral charge transport. The implementation of the buried channels in general renders the electrical field deeper in the silicon, but for sensing and demodulating light in the near-infrared wavelength, the penetration depth of the depletion region in the substrate is still shorter than desired generally.

(16) A second mechanism relies on a current 230 of majority carriers that is generated through the semiconductor substrate 101 by applying a voltage difference between nodes or p implantations 236 and 238 and thus across the pixel sensitive area 102. The current 230 flowing from p implantation 236 to p implantation 238 generates an electric field, which forces photo-generated minority charge carriers to drift into lateral direction. Here, photo-generated charge carriers are affected that are generated deeper in the substrate than the depth of the depletion region 210 of the shallow doping layer. Thus, this additional lateral force becomes more effective for electromagnetic radiation of longer wavelengths.

(17) If the substrate 101 is p-doped as shown, the minority carriers are electrons. Since the n+ diffusion areas are set to even higher potential than the p+ regions, the electrons will be collected in the n+ diffusion nodes 232, 234. The diffusion nodes are preferably used as a sense node for accumulation of all photo-charges. Alternatively, instead of using diffusion nodes, a gate set to high potential is used in other examples as well so that the storage of the charge or even subsequent signal processing is accomplished in gate regions.

(18) A third mechanism provides even higher photo-sensitivity and vertical transfer speed in some instances by exploiting graded or gradually doped wafer types. In the easiest case of the EPI layer on top of the higher doped bulk wafer 105, a junction at the interface occurs. Such a junction is called high-low junction. The principle of high-low junctions is described by Amitabha Sinha and S.K. Chattopadhyaya in Effect of back surface field on photocurrent in a semiconductor junction, Solid-State Electronics, Vol. 21, pp. 943-951, 1977; and Effect of Heavy Doping on the Properties of High-Low Junction, IEEE Transactions on Electron Devices, Vol. Ed-25, No. 12, Dec. 1978. In this new pixel architecture, the high-low junction at the EPI-bulk interface 106 is exploited for collecting additional photo-generated charge carriers that are deeply generated in the semiconductor. Those charge carriers are directly fed toward the surface and into the region of lateral drift fields so that the photo-current signal originating from deeply inside the semiconductor contributes to the global signal detection as well.

(19) In the following the main benefits that can be obtained by embodiments of the invention are summarized:

(20) a) High sensitivity due to the collection of charge carriers deeply generated in the silicon substrate.

(21) b) High optical sensitivity due to the collection of charges generated deeply in the silicon and transported to the sense node by deep lateral drift fields.

(22) c) Fast charge transport through the whole device due to strong lateral drift fields at the SiSiO2 interface, in the highly optically sensitive buried-channel region and deep in the semiconductor.

(23) The combination of all these three items enables the realization of highly-sensitive and fast pixel devices that allow for resolving optical time signals with an accuracy by far less than a nanosecond and with an optical sensitivity at the same time, which is beyond those of prior-art demodulation pixels.

(24) A few examples of the invention are discussed below. They, however, do not restrict the invention from the generality of the pixel concept, which comprises an optimized pixel architecture in terms of photo-sensitivity and charge transport speed obtained by the combination of one or all of the mechanisms: 1) the enhanced charge transport through a buried channel, 2) the lateral enhanced transport deeply through the semiconductor, and 3) the deep photo-charge collection by vertical drift fields.

(25) FIG. 3 shows an example for a demodulation pixel with separated detection region 110 and demodulation region 112. A series of gates 110a, 110b, 110c, 110d are used to generate a static drift field in the detection region 110 to transport electrons to the demodulation region 112.

(26) The funnel-shaped area 210 shows the extent of the buried channel and the n+ diffusion area. The majority current flows from p implantation 236 to p implantation 238.

(27) FIG. 4 shows a cross section through the detection region 110 of FIG. 3.

(28) The creation of the lateral drift field 108 close to the semiconductor interface is achieved by the buried channel 210 formed by the n implantation and the arrangement of a successive gate structure 110a, 110b, 110c, 110d on top of the semiconductor and the insulator layer 220, which is typically silicon dioxide. By applying increasing voltages on the gates 110a, 110b, 110c, 110d in the direction of the demodulation region 112, a monotonously increasing potential distribution inside the buried channel region 210 is obtained as well.

(29) FIG. 5 a cross section through the detection region 110 of FIG. 3 showing another embodiment. The creation of the drift field in the n doped implantation layer of FIG. 5 is accomplished by a single high resistive gate 110r on top of the insulator layer 220. The current flowing through the gate 110r when a potential difference is applied to the two ends of it via contacts 240, 242 generates a constant drift field 108, which is seen in the buried channel 210 due to the capacitive coupling between the gate and the semiconductor substrate. This concept of drift field generation has been published in [SEI02], but here we enhance the pixel's sensitivity and speed even more by combining the prior-art drift field technique with the additional drift field concepts.

(30) FIG. 6 shows another example for the creation of the drift field in a cross section through the detection region 110 of FIG. 3. It uses a continuous change of the doping concentration of the n implantation 210 in a lateral direction and in the direction of the demodulation region. This means a change of the built-in voltage, so that the lateral electric field does not necessarily require the application of external voltages. Such a variation of the doping concentration is achieved by designing for example several layers of step-wise increasing doping concentrations. The process-inherent temperature diffusion steps are exploited for smearing the rather step-wise doping profile to a profile of more constant gradient. This technique assumes a certain flexibility of the process meaning that several doping profiles are available. Another possibility for the creation of a constant doping profile's gradient is the exploitation of gray-scale mask lithography as described by W. Henke et al. in Simulation and experimental study of gray-tone lithography for the fabrication of arbitrarily shaped surfaces, IEEE Workshop on Micro Electro Mechanical Systems, 1994, MEMS '94, pp. 205-210.

(31) FIG. 7 shows an example where just two of the charge transport mechanisms are used within the detection region 110 of FIG. 3. There is no buried layer anymore. The charge transport is only realized by the static lateral drift field generated by the majority carrier current 230 and the deeply generated electrons are collected by the vertical drift field components around interface 106.

(32) FIG. 8 generated the drift field 108 using the capacitive coupling between two gates 110a, 110b through the detection region 110 of FIG. 3. Just two gates 110a, 110b are formed on top of the insulating layer 220 and separated by an arbitrary distance, which just needs to fulfill at least the minimum design rules. Since the buried implantation 210 fully depletes, the capacitive coupling between the gates 110a, 110b is exploited for generating potential distributions that are advantageous for a fast charge transport.

(33) FIG. 9 illustrates the 3D TOF camera system using the invented pixel architecture. The light emitter 20 produces modulated light 11 illuminates the scene 30. The returning light 12 from the scene 30 is collected by the camera lens 40, which generally includes a bandpass filter so that only light at the wavelength emitted by the light emitter 20 is transmitted. An image is formed on the TOF detector chip 90 which is a two dimensional array of pixels 100. Control electronics 60, which might be integrated on the same chip as the imager 90, coordinate the modulation of the light emitter 10 with the sampling of the TOF detector chip 90. This results in synchronous demodulation. A data output interface 70 is then able to reconstruct the 3-D image representation using the samples generated by the chip 90 such that a range to the scene is produced for each of the pixels 100 of the detector chip 90.

(34) Typically the demodulation pixel is aimed for being used in 1D or 2D pixel arrays. The invention itself does not set any limitation to the total pixel count of the sensor. Standard or special dedicated read out schemes in the analogue or digital domain can be applied. The invention concentrates on the in-pixel charge transport properties according to the descriptions above, and it is independent on the dedicated sensor topology.

(35) While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.