Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Abstract

A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

Claims

1. A broadcaster that accepts a virtual scan pattern via one or more scan inputs for generating a broadcast scan pattern to test a scan-based circuit, the scan-based circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, said broadcaster comprising: a) a virtual scan controller, said virtual scan controller further including one or more shift registers for accepting said virtual scan pattern via at least one said scan input; and b) a solely combinational logic network coupled to one or more outputs of said virtual scan controller for generating said broadcast scan pattern at outputs of said combinational logic network, said combinational logic network comprising one or more multiplexers, wherein application of said virtual scan pattern to said scan-based circuit through said broadcaster decreases a test application time relative to a test application time for a test that does not utilize said broadcaster.

2. The broadcaster of claim 1, wherein the combinational logic network is further directly connected to at least one said scan input.

3. The broadcaster of claim 1, wherein each said shift register further comprises one or more memory elements, wherein each said memory element further includes a flip-flop or a latch.

4. The broadcaster of claim 1, further comprising a clock for controlling said virtual scan controller, wherein said clock runs at a frequency equal to a shift clock controlling said scan cells in a said scan chain.

5. The broadcaster of claim 1, further comprising a clock for controlling said virtual scan controller, wherein said clock runs at a frequency higher than a shift clock controlling said scan cells in a said scan chain.

6. The broadcaster of claim 1, wherein said combinational logic network further includes one or more logic gates, wherein said logic gate further includes an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate, an XNOR gate, a buffer, or an inverter.

7. The broadcaster of claim 1, wherein said virtual scan controller further controls the operation of said broadcaster during each shift cycle.

8. The broadcaster of claim 1, wherein said virtual scan controller further controls the operation of said broadcaster between test sessions.

9. The broadcaster of claim 1, further comprising a first scan connector for merging two selected scan chains into one long scan chain, wherein said first scan connector further comprises at least a buffer, an inverter, a multiplexer, or a lockup element.

10. The broadcaster of claim 1, further comprising a second scan connector inserted into the outputs of said combinational logic network and selected scan cells within said scan chains to split a selected scan chain to two or more short scan chains; wherein said second scan connector further comprises one or more multiplexers.

11. The broadcaster of claim 1, further comprising circuitry adapted to transmit said virtual scan pattern to said one or more scan inputs of said broadcaster and transmit said broadcast scan pattern generated by said broadcaster to selected scan data inputs of said scan chains in said scan-based circuit.

12. The broadcaster of claim 1, wherein said scan-based circuit is embedded in a scan-based integrated circuit.

Description

THE BRIEF DESCRIPTION OF DRAWINGS

(1) The above and other objects, advantages and features of the invention will become more apparent when considered with the following specification and accompanying drawings wherein:

(2) FIG. 1 shows a block diagram of a conventional system for testing scan-based integrated circuits using an automatic test equipment (ATE);

(3) FIG. 2 shows a block diagram of a broadcast scan test system, in accordance with the present invention, for testing scan-based integrated circuits using an ATE;

(4) FIG. 3 shows a prior art broadcaster design with only pure wires;

(5) FIG. 4 shows a block diagram of a broadcaster, in accordance with the present invention, consisting of a combinational logic network and an optional scan connector;

(6) FIG. 5A shows a first embodiment of a broadcaster shown in FIG. 4, in accordance with the present invention, consisting of a combinational logic network;

(7) FIG. 5B shows the inputs constraint imposed by the embodiment of a broadcaster shown in FIG. 5A;

(8) FIG. 5C shows a second embodiment of a broadcaster shown in FIG. 4, in accordance with the present invention, consisting of a combinational logic network and a scan connector;

(9) FIG. 5D shows the inputs constraint imposed by the embodiment of a broadcaster shown in FIG. 5C;

(10) FIG. 6 shows a block diagram of a broadcaster, in accordance with the present invention, consisting of a virtual scan controller, a combinational logic network, and an optional scan connector;

(11) FIG. 7 shows a first embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention;

(12) FIG. 8 shows a second embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention;

(13) FIG. 9 shows a third embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention;

(14) FIG. 10 shows a fourth embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention;

(15) FIG. 11 shows a fifth embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention;

(16) FIG. 12 shows a sixth embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention;

(17) FIG. 13 shows a block diagram of a compactor, in accordance with the present invention, consisting of a mask network and a XOR network or a multiple-input signature register (MISR);

(18) FIG. 14 shows a first embodiment of a compactor shown in FIG. 13, in accordance with the present invention;

(19) FIG. 15 shows a second embodiment of a compactor shown in FIG. 13, in accordance with the present invention;

(20) FIG. 16A shows an embodiment of the method before reordering scan cells or changing the scan chain length for generating broadcast scan patterns to test more faults, in accordance with the present invention;

(21) FIG. 16B shows an embodiment of the method after reordering scan cells for generating broadcast scan patterns to test more faults, in accordance with the present invention;

(22) FIG. 16C shows an embodiment of the method after changing the scan chain length for generating broadcast scan patterns to test more faults, in accordance with the present invention;

(23) FIG. 17 shows a flow chart of the method for reordering scan cells for fault coverage improvement, in accordance with the present invention;

(24) FIG. 18 shows a flow chart of the method for generating broadcast scan patterns used in testing scan-based integrated circuits, in accordance with the present invention;

(25) FIG. 19 shows a flow chart of the method for synthesizing a broadcaster and a compactor to test a scan-based integrated circuit, in accordance with the present invention; and

(26) FIG. 20 shows an example system in which the broadcast scan test method, in accordance with the present invention, may be implemented.

DETAILED DESCRIPTION OF THE INVENTION

(27) The following description is presently contemplated as the best mode of carrying out the present invention. This description is not to be taken in a limiting sense but is made merely for the purpose of describing the principles of the invention. The scope of the invention should be determined by referring to the appended claims.

(28) FIG. 1 shows a block diagram of a conventional system for testing scan-based integrated circuits using an ATE. The system 101 includes a tester or external automatic test equipment (ATE) 102 and a circuit-under-test (CUT) 107, which contains scan chains 109.

(29) The ATE 102 applies a set of fully specified test patterns 103, one by one, to the CUT 107 via scan chains 109 in scan mode from external scan input pins 111 as well as from external primary input pins 113. The CUT is then run in normal mode using the applied test pattern as input, and the response to the test pattern is captured into the scan chains. The CUT is then put back into scan mode again and the test response is shifted out to the ATE via scan chains from external scan output pins 112 as well as from external primary output pins 114. The shifted-out test response 104 is then compared by the comparator 105 with the corresponding expected test response 106 to determine if any fault exists in the CUT, and indicates the result by the pass/fail signal 115.

(30) In the conventional system 101, the number of scan chains 109 in the CUT 107 is identical to the number of the external scan input pins 111 or the number of the external scan output pins 112. Since the number of external pins is limited in an integrated circuit, the number of scan chains in the conventional system is also limited. As a result, a large integrated circuit with a large number of scan cells (SC) 108 usually contains very long scan chains for scan test. This will result in unacceptably large test data volume and costly long test application time.

(31) FIG. 2 shows a block diagram of a broadcast scan test system, in accordance with the present invention, for testing scan-based integrated circuits using an ATE. The system 201 includes an ATE 202 and a circuit 207 that includes a broadcaster 208, a CUT 209, and a compactor 213. The CUT contains scan chains 211.

(32) The broadcaster 208 may contain only a combinational logic network as shown in FIG. 4 or a virtual scan controller in addition to a combinational logic network as shown in FIG. 6. The broadcaster is used to map virtual scan patterns 203 to broadcast scan patterns, where the number of bits of a virtual scan pattern is usually smaller than that of a broadcast scan pattern. The mapping function of a broadcaster is fixed if it only contains a combinational logic network. However, the mapping function is variable if it also contains a virtual scan controller. In this case, the output values of the virtual scan controller can change the mapping function that the combinational logic network realizes, thus implementing different mapping relations from external scan input pins 215 to internal scan chain inputs 219. The compactor 213 is a combinational logic network, such as an XOR network, designed to map the internal scan chain outputs 220 to external scan output pins 216. Note that in practice, the number of external scan input or output pins is smaller than the number of internal scan chain inputs or outputs.

(33) Note that the element 213 can be replaced with an optional space compactor and a multiple-input signature registers (MISR). In this case, all test responses will be compressed into a single signature, which can be compared with a reference signature either in the circuit 207 or in the ATE 202 after all broadcast scan patterns have been applied.

(34) In addition, the compactor 213 usually contains a mask network used to block several output streams from coming into a XOR compaction network or a MISR. This is useful in fault diagnosis.

(35) FIG. 3 shows a prior art broadcaster design with only pure wires. This example broadcaster design 301 has two broadcast scan inputs 314 and 315. The broadcast scan input 314 is connected directly to scan chains 303 to 307 while the broadcast scan input 315 is connected directly to scan chains 308 to 312. Although the overhead of this pure-wire broadcast design is very low, the test pattern dependency among the scan chains fed by the same broadcast scan input is very high. From the point of view of automatic test pattern generation (ATPG), this pure-wire broadcast design puts a strong constraint on the inputs to scan chains. As a result, this scheme usually suffers from severe fault coverage loss.

(36) FIG. 4 shows a block diagram of a broadcaster, in accordance with the present invention, consisting of a combinational logic network and an optional scan connector. Virtual scan patterns are applied via broadcast scan inputs 407 of the broadcaster 401 to the combinational logic network 402. The combinational logic network implements a fixed mapping function, which converts a virtual scan pattern into a broadcast scan pattern. The broadcast scan pattern is then applied to all scan chains 409 in the CUT 404, through an optional scan connector 403.

(37) The broadcaster 401 serves the purpose of providing test patterns to a large number of internal scan chains 406 through a small number of external broadcast scan input pins 407. As a result, all scan cells SC 405 in the CUT 404 can be configured into a large number of shorter scan chains. This will help in reducing test data column and test application time. By properly designing the combinational logic network 402, one can reduce the fault coverage loss caused by additional constraints imposed on the input pins of the scan chains.

(38) FIG. 5A shows a first embodiment of a broadcaster shown in FIG. 4, in accordance with the present invention, consisting of a combinational logic network. In this example, a 3-bit virtual scan pattern is converted into an 8-bit broadcast scan pattern via the broadcaster 501.

(39) The broadcaster 501 consists of a combinational logic network 502, which contains two inverters 503 and 507, one multiplexer 508, one XOR gate 504, one OR gate 505, and one NOR gate 506. Virtual scan patterns are applied via broadcast scan inputs X2 518 to X0 520. The combinational logic network implements a fixed mapping function, which converts a virtual scan pattern into a broadcast scan pattern. The broadcast scan pattern is then applied to all scan chains 510 to 517 via Y7 521 to Y0 528 in the CUT 529.

(40) FIG. 5B shows the inputs constraint imposed by the embodiment of a broadcaster shown in FIG. 5A.

(41) The broadcaster 501 in FIG. 5A has three broadcast scan inputs X2 518 to X0 520. Thus, there are 8 input combinations for the broadcast scan inputs as listed under <X2, X1, X0> in the table 531. These are all possible input value combinations to the combinational logic network 502 in FIG. 5A. Therefore, as the outputs of the combinational logic network, there are 8 value combinations as listed under <Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0> in the table 531. These are all possible logic value combinations that may appear at the inputs of the scan chains 510 to 517 in FIG. 5A, and they are the input constraints in the process of ATPG.

(42) FIG. 5C shows a second embodiment of a broadcaster shown in FIG. 4, in accordance with the present invention, consisting of a combinational logic network and a scan connector. In this example, a 3-bit virtual scan pattern is converted into an 8-bit broadcast scan pattern via the broadcaster 561.

(43) The broadcaster 561 consists of a combinational logic network 562 and a scan connector 566. The combinational logic network contains one inverter 565, one XOR gate 563, and one OR gate 564. Virtual scan patterns are applied via broadcast scan inputs X2 581 to X0 583. The combinational logic network implements a fixed mapping function, which converts a virtual scan pattern into a broadcast scan pattern. The broadcast scan pattern is then applied to all scan chains 573 to 580 through the scan connector 566. The scan connector consists of one buffer 567, one inverter 570, one lock-up element LE 569, and one spare cell SC 568. Generally, two scan chains can be connected into one by using a buffer, an inverter, or a lock-up element in a scan connector. In addition, a spare cell can be added into an existing scan chain to change its length in order to reduce the dependency among different scan chains. This will help improve fault coverage.

(44) FIG. 5D shows the inputs constraint imposed by the embodiment of a broadcaster shown in FIG. 5C.

(45) The broadcaster 561 in FIG. 5C has three broadcast scan inputs X2 581 to X0 583. Thus, There are 8 input combinations for the broadcast scan inputs as listed under <X2, X1, X0> in the table 591. These are all possible input value combinations to the combinational logic network 562 in FIG. 5C. Therefore, as the outputs of the combinational logic network, there are 8 value combinations as listed under <Y4, Y3, Y2, Y1, Y0> in the table 591. These are the input constraints in the process of ATPG.

(46) FIG. 6 shows a block diagram of a broadcaster, in accordance with the present invention, consisting of a virtual scan controller, a combinational logic network, and an optional scan connector.

(47) The broadcaster 601 consists of a virtual scan controller 602, a combinational logic network 603, and an optional scan connector 604. Virtual scan patterns are applied via two types of input pins: broadcast scan inputs 608 and virtual scan inputs 609. The broadcast scan inputs are connected directly to the combinational logic network, while the virtual scan inputs are connected directly to the virtual scan controller. In addition, the virtual scan controller may have optional virtual scan outputs 613.

(48) Note that the virtual scan controller 602 can be either a combinational circuit such as a decoder, or a sequential circuit such as a shift register. The logic values applied through virtual scan inputs 609 may or may not change in each clock cycle although logic values applied through broadcast scan inputs 608 change in each clock cycle. The purpose of applying virtual scan input values is to change and store a proper set-up value combination in the virtual scan controller. This set-up value combination is applied to the combinational logic network 603 through 610 in order to change the mapping function that the combinational logic network implements. Since one mapping function corresponds to one set of input constraints for ATPG, providing the capability of changing mapping functions results in more flexible input constraints for ATPG. As a result, fault coverage loss due to the broadcast scheme can be substantially reduced.

(49) Generally, the broadcaster 601 serves two purposes during test. One purpose is to provide test patterns to a large number of internal scan chains 607 through a small number of external broadcast scan input pins 608 and virtual scan input pins 609. As a result, all scan cells SC 606 in a circuit can be configured into a large number of shorter scan chains. This will help in reducing test data volume and test application time. Another purpose is to increase the quality of broadcast scan patterns applied from the combinational logic network 603 to all scan chains in order to obtain higher fault coverage. This is achieved by changing the values loaded into the virtual scan controller. Because of this flexibility, the combinational logic network can realize different mapping functions rather than a fixed one.

(50) FIG. 7 shows a first embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention. The broadcaster 701 consists of a virtual scan controller 702 and a combinational logic network 705. The virtual scan controller consists of two inverters 703 and 704. The combinational logic network is composed of 8 XOR gates 706 to 713. In this example, a 4-bit virtual scan pattern is converted into an 8-bit broadcast scan pattern via the broadcaster.

(51) Obviously, the outputs 730 and 731 of the virtual scan controller 702 must have complementary values. In addition, the outputs 732 and 733 of the virtual scan controller must also have complementary values. Suppose that the values applied to the two broadcast scan inputs 728 and 729 are V1 and V2, respectively. In this case, the values appearing at scan chain inputs 734 to 743 should be 1, P1, P2, P2, V1, V2, P3, P3, P4, P4, respectively. Here P1 and P1 are complementary, P2 and P2 are complementary, P3 and P3 are complementary, P4 and P4 are complementary. In addition, P1 and P2 are either the same as V1 or are the complement of V1 while P3 and P4 are either the same as V1 or are the complement of V2. This is the input constraint for ATPG.

(52) FIG. 8 shows a second embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention. The broadcaster 801 consists of a virtual scan controller 802 and a combinational logic network 804. The virtual scan controller consists of a 2-to-4 decoder 803. The combinational logic network is composed of 8 XOR gates 805 to 812. In this example, a 4-bit virtual scan pattern is converted into an 8-bit broadcast scan pattern via the broadcaster.

(53) Obviously, there are four possible logic value combinations for the outputs 829 to 832 of the 2-to-4 decoder 803. They are 1000, 0100, 0010, and 0001 for the outputs 829 to 832, respectively. Suppose the output value combination of the 2-to-4 decoder is 1000. Also suppose that the logic values applied to the two broadcast scan inputs 827 and 828 are V1 and V2, respectively. In this case, the values appearing at scan chain inputs 833 to 842 should be V1, V1, V1, V1, V1, V2, V2, V2, V2, V2, respectively. Here V1 and V1 are complementary, while V2 and V2 are complementary. This is the input constraint for ATPG. Obviously, by changing the values of virtual scan inputs 825 and 826, one can get different set of input constraints for ATPG. This will help in improving fault coverage.

(54) FIG. 9 shows a third embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention.

(55) The broadcaster 901 consists of a virtual scan controller 902 and a combinational logic network 911. The virtual scan controller consists of an 8-stage shift register with memory elements 903 to 910. There is one virtual scan input 932, which is the input to the shift register. There is one optional virtual scan output 935, which is the output of the shift register. Optionally, the virtual scan input and the virtual scan output can be connected to TDI and TDO in the boundary scan design, respectively. The combinational logic network is composed of 8 XOR gates 912 to 919. There are two broadcast scan inputs, 933 and 934. Test patterns applied via the input 933 are broadcasted to scan chains 922 to 926; while test patterns applied via the input 934 are broadcasted to scan chains 927 to 931.

(56) The scan chains 926 and 927 are loaded directly from the broadcast scan input 933 and 934, respectively, while the scan chains 922 to 925, as well as the scan chains 928 to 931, are loaded through XOR gates 912 to 915 and 916 to 919, respectively. If the value of the memory element 903 is a logic 0, the scan chain 922 will get the identical values as those applied from the broadcast scan input 933. If the value of the memory element 903 is a logic 1, the scan chain 922 will then get the complementary values to those applied from the broadcast scan input 933. The same observation applies to the scan chains 923 to 925 as well as 928 to 931. This means that, by applying a set of properly determined values to the shift register in the virtual scan controller 902, it is possible to apply any of the 1024 combinations of logic values to the scan chains 922 to 931 in any shift cycle. As a result, any detectable fault in the CUT 920 can be detected by loading a set of properly determined logic values to the shift register and by applying a broadcast scan pattern through the inputs 933 and 934.

(57) From the point of view of ATPG, which tries to generate broadcast scan patterns to drive all scan chains in order to test the CUT 920, the broadcaster configuration determined by the values of the memory elements in the shift register of the virtual scan controller 902 represents an input constraint. Suppose that the values for the memory elements 903 to 910 are 0, 1, 0, 1, 0, 1, 0, 1, respectively. In this case, the ATPG for the CUT should satisfy such an input constraint that, in any shift cycle, the scan chains 922, 924, and 926 have the identical value V, the scan chains 923 and 925 have the identical value V that is the complement of V, the scan chains 927, 928, and 930 have the identical value P, the scan chains 929 and 931 have the identical value P that is the complement of P.

(58) FIG. 10 shows a fourth embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention.

(59) The broadcaster 1001 consists of a virtual scan controller 1002 and a combinational logic network 1006. The virtual scan controller consists of a 3-stage shift register with memory elements 1003 to 1005. There is one virtual scan input 1023, which is the input to the shift register. There is one optional virtual scan output 1026, which is the output of the shift register. Optionally, the virtual scan input and the virtual scan output can be connected to TDI and TDO in the boundary scan design, respectively. The combinational logic network is composed of 4 XOR gates 1007 to 1010. There are two broadcast scan inputs, 1024 and 1025. Test patterns applied via the input 1024 are broadcasted to scan chains 1013 to 1017; test patterns applied via the input 1025 are broadcasted to scan chains 1018 to 1022.

(60) The major difference between the broadcaster 901 in FIG. 9 and the broadcaster 1001 in FIG. 10 is that test patterns are broadcasted directly to some scan chains instead of going through XOR gates in the broadcaster 1001. The scan chains 1013, 1015, and 1017 are driven directly from the broadcast scan input 1024. This means that, in any shift cycle, scan chains 1013, 1015, and 1017 will have the identical values. In addition, the scan chains 1018, 1020, and 1022 are driven directly from the broadcast scan input 1025. This means that, in any shift cycle, scan chains 1018, 1020, and 1022 will have the identical values. As a result, by applying a set of properly determined values to the shift register in the virtual scan controller 1002, it is only possible to apply any of the 64 combinations of logic values to the scan chains 1013 to 1022 in any shift cycle. That is, the broadcaster 1001 needs less hardware overhead at the expense of stronger constraints at the inputs to the scan chains.

(61) FIG. 11 shows a fifth embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention.

(62) The broadcaster 1101 consists of a virtual scan controller 1102 and a combinational logic network 1106. The virtual scan controller consists of a 3-stage shift register with memory elements 1103 to 1105. There is one virtual scan input 1127, which is the input to the shift register. There is one optional virtual scan output 1130, which is the output of the shift register. Optionally, the virtual scan input and the virtual scan output can be connected to TDI and TDO in the boundary scan design, respectively. The combinational logic network is composed of four XOR gate (1108, 1109, 1112, 1114), two inverters (1107, 1113), one AND gate (1110), and one OR gate (1111). There are two broadcast scan inputs, 1128 and 1129. Test patterns applied via the input 1128 are broadcasted to scan chains 1117 to 1121; test patterns applied via the input 1129 are broadcasted to scan chains 1122 to 1126.

(63) The broadcaster 1101 realizes more complex broadcast mapping relations from the broadcast scan inputs 1128 and 1129 to the inputs of the scan chains 1117 to 1126. The general form of the mapping relations can be represented by <VB, VC, V, VC, V*P, V+P, PC1, PB, PC2, P> corresponding to the inputs of the scan chains 1117 to 1126, respectively. Here, V and P are two logic values applied from the broadcast scan inputs 1128 and 1129 in any shift cycle, respectively. VB and PB are the complements of V and P, respectively. VC equals V or VB if the output value of the memory element 1103 is a logic 0 or 1, respectively. PC1 equals P or PB if the output value of the memory element 1104 is a logic 0 or 1, respectively; PC2 equals P or PB if the output value of the memory element 1105 is a logic 0 or 1, respectively. Obviously, the broadcast mapping relation can be changed by changing VC, PC1, and PC2 through loading different sets of logic values into the shift register in the virtual scan controller 1102. As a result, less inter-dependent test stimuli can be applied to the CUT 1115 so that higher fault coverage can be reached.

(64) From the point of view of ATPG, which tries to generate broadcast scan patterns to drive all scan chains 1117 to 1126 in order to test the CUT 1115, the broadcaster configuration determined by the values of the memory elements in the shift register of the virtual scan controller 1102 represents an input constraint whose general form is <VB, VC, V, VC, V&P, V+P, PC1, PB, PC2, P>. This constrained ATPG can be performed if the original sequential CUT 1115 is transformed to a combinational circuit model reflecting the constraint after the values of the memory elements are determined.

(65) FIG. 12 shows a sixth embodiment of a broadcaster shown in FIG. 6, in accordance with the present invention.

(66) The broadcaster 1201 consists of a virtual scan controller 1202, a combinational logic network 1203, and a scan connector 1207. The combinational logic network contains two inverters 1204 and 1206 in addition to one OR gate 1205. Virtual scan patterns are applied via broadcast scan inputs 1226 and 1227 as well as a virtual scan input TDI 1224. One output X2 1229 from the virtual scan controller is applied to the combinational logic network, making it able to implement different mapping functions. The output values 1232 to 1236 from the combinational logic network is then applied to all scan chains 1215 to 1223 through the scan connector 1207. The scan connector consists of one buffer 1209, one inverter 1212, one lock-up element LE 1211, one spare cell SC 1210, and one multiplexer 1208. Generally, two scan chains can be connected into one by using a buffer, an inverter, or a lock-up element in a scan connector. In addition, a spare cell can be added into an existing scan chain to reduce the dependency among different scan chains. This will help improve fault coverage. Furthermore, a multiplexer can be used to split a scan chain into two parts. As shown in FIG. 12, if the selection signal 1228 of the multiplexer 1208 is a logic 1, the scan chains 1215 and 1216 will get different input value streams. However, if the selection signal 1228 of the multiplexer 1208 is a logic 0, the scan chains 1215 and 1216 can be seen as one scan chain, and only one input value stream goes though them. Obviously, a scan connector can be used to adjust the length of scan chains in the CUT in order to shorten test time or improve fault coverage.

(67) FIG. 13 shows a block diagram of a compactor, in accordance with the present invention, consisting of a mask network and a XOR network or a MISR.

(68) The test responses on the outputs 1308 of the CUT corresponding to broadcast scan patterns applied on the inputs 1307 of the CUT pass through a compactor 1304, which consists of a mask network 1305 and a XOR network or a MISR 1306. MC 1311 is the signal used to control the mask network. It can be applied from an ATE or generated by a virtual scan controller. The mask network is used to mask some inputs to a XOR network or a MISR. This is useful in fault diagnosis. A XOR network is used to conduct space compaction, i.e. reducing the number of test response lines going out of the circuit. On the other hand, a MISR can be used to compress test responses in both space and time domains. That is, there is no need to check test results cycle by cycle when a MISR is used. On the contrary, it is only necessary to compare the signature obtained at the end of the whole test session. However, it should be noted that no unknown values (X's) are allowed to come into a MISR. This means stricter design rules should be followed.

(69) FIG. 14 shows a first embodiment of a compactor shown in FIG. 13, in accordance with the present invention.

(70) The test responses on the outputs 1441 to 1448 pass through a mask network 1412 and then a XOR network 1422. The mask network consists of two groups of AND gates 1414 to 1417 and 1418 to 1421, each group being controlled by the four outputs generated by a modified 2-to-4 decoder 1413. In the diagnosis mode where the mode signal 1449 is a logic 1, this decoder maps logic values on MC1 1429 and MC2 1430 to one of the following combinations: 1000, 0100, 0010, and 0001. With any of these logic combination, it is clear that either group of AND gates will allow only one test response stream to pass to 1431 or 1432. Obviously, this will help in fault diagnosis. In the test mode where the mode signal 1449 is a logic 0, this decoder will generate an all-1 logic combination. This will allow all test response streams pass to 1431 or 1432. The XOR network 1422 consists of two groups of 4-to-1 XOR sub-networks, composed of XOR gates 1423 to 1425 and 1426 to 1428, respectively.

(71) FIG. 15 shows a second embodiment of a compactor shown in FIG. 13, in accordance with the present invention.

(72) The test responses on the outputs 1540 to 1547 pass through a mask network 1512 and then a MISR 1525. The mask network consists of two groups of AND gates 1517 to 1520 and 1521 to 1524, each group being controlled by the four outputs of a shift register composed of memory elements 1513 to 1516. In the diagnosis mode, this shift register can be loaded from TDI 1526 with one of the following combinations: 1000, 0100, 0010, and 0001. With any of these logic combination, it is clear that either group of AND gates will allow only one test response to pass stream to the MISR. Obviously, this will help in fault diagnosis. In the test mode, an all-1 logic combination will be loaded into the shift register. This will allow all test response streams pass to the MISR. The content of the MISR at the end of a test session can be shifted out from TDO 1529 for comparison with the expected signature.

(73) FIG. 16A shows an embodiment of the method before reordering scan cells or changing the scan chain length for generating broadcast scan patterns to test more faults, in accordance with the present invention. A broadcaster 1601 has one broadcast scan input 1614, which broadcasts logic values to three scan chains, 1606, 1608, and 1611.

(74) Since logic values are applied to the scan chain 1611 via an XOR gate 1604, by properly loading the shift register in the virtual scan controller 1602, it is possible, in any shift cycle, to apply any logic value which can be different from the one applied via scan chains 1606 and 1608. However, scan chains 1606 and 1608 will be loaded with the same logic values in any shift cycle. As a result, the scan cells A3 1607 and B3 1610 will have the same logic value in any broadcast test patterns. Since the outputs from the scan cells A3 1607 and B3 1610 are connected to the same combinational logic block 1612, it is possible that some faults in the combinational logic block cannot be detected due to this strong test pattern dependency. For example, in order to detect some faults in the combinational logic block, it may be necessary to have a logic 0 as the output of the scan cell A3 1607 and a logic 1 as the output of the scan cell B3 1610. Obviously, these faults will not be detected.

(75) FIG. 16B shows an embodiment of the method after reordering scan cells for generating broadcast scan patterns to test more faults, in accordance with the present invention. A broadcaster 1601 has one broadcast scan input 1614, which broadcasts logic values to three scan chains, 1606, 1608, and 1611.

(76) The only difference between FIG. 16A and FIG. 16B is that, in the scan chain 1608, the order of the scan cells B2 1609 and B3 1610 is changed. Now, although the outputs of the scan cells A3 1607 and B2 1609 have the same logic value in any shift cycle, the outputs of the scan cells A3 1607 and B3 1610 can have different logic values. As a result, this makes it possible to detect some faults that cannot be detected with the scan order shown in FIG. 16A.

(77) FIG. 16C shows an embodiment of the method after changing the scan chain length for generating broadcast scan patterns to test more faults, in accordance with the present invention. A broadcaster 1601 has one broadcast scan input 1614, which broadcasts logic values to three scan chains, 1606, 1608, and 1611.

(78) The only difference between FIG. 16A and FIG. 16C is that, one spare scan cell B0 1617 is added to the scan chain 1608 through a multiplexer 1618. It is clear that, if the selection signal 1619 is a logic 1, the spare scan cell will be added to the scan chain 1608. As a result, although the outputs of the scan cells A3 1607 and B2 1609 have the same logic value in any shift cycle, the outputs of the scan cells A3 1607 and B3 1610 can have different logic values. As a result, this makes it possible to detect some faults that cannot be detected with the scan order shown in FIG. 16A.

(79) FIG. 17 shows a flow chart of the method for reordering scan cells for fault coverage improvement, in accordance with the present invention. This method 1700 accepts the user-supplied HDL codes 1701 together with the chosen foundry library 1702. The HDL codes represent a sequential circuit comprised of a broadcaster, a full-scan CUT, and a compactor as shown in FIG. 2. The HDL codes and the library are then complied into an internal sequential circuit model 1704, which is then transformed into a combination circuit model 1706. Then, based on the original scan order information 1709 and the scan order constraints 1710, the input-cone analysis 1707 is conducted to identify scan cells whose order needs to be changed. Then, scan chain reordering 1708 is conducted. After that, the HDL test benches and tester programs 1711 are generated while all reports and errors are saved in the report files 1712.

(80) FIG. 18 shows a flow chart of the method for generating broadcast scan patterns used in testing scan-based integrated circuits, in accordance with the present invention. This method 1800 accepts the user-supplied HDL codes 1801 together with the chosen foundry library 1802. The HDL codes represent a sequential circuit comprised of a broadcaster, a full-scan CUT, and a compactor as shown in FIG. 2. The HDL codes and the library are then complied into an internal sequential circuit model 1804, which is then transformed into a combination circuit model 1806. Then, based on input constraints 1810, combinational fault simulation 1807 is performed, if so required, for a number of random patterns and all detected faults are removed from the fault list. After that, combinational ATPG 1808 is performed to generate virtual scan patterns and all detected faults are removed from the fault list. If predetermined limiting criteria, such as a pre-selected fault coverage goal, are met, the HDL test benches and ATE test programs 1811 are generated while all reports and errors are saved in the report files 1812. If the predetermined limiting criteria are not met, new input constraints 1810 will be used. For example, a new set of values can be loaded into the virtual scan controller to specify new input constraints. After that, optional random-pattern fault simulation 1807 and ATPG 1808 are performed. This iteration goes on until the predetermined limiting criteria are met.

(81) FIG. 19 shows a flow chart of the method for synthesizing a broadcaster and a compactor to test a scan-based integrated circuit, in accordance with the present invention. This method 1900 accepts the user-supplied HDL codes 1901 together with the chosen foundry library 1902. The HDL codes represent a sequential circuit comprised of a broadcaster, a full-scan CUT, and a compactor as shown in FIG. 2. The HDL codes and the library are then complied into an internal sequential circuit model 1904. Then, based on the broadcaster constraints 1908 and the compactor constraints 1909, broadcaster synthesis 1905 and compactor synthesis 1906 are conducted, respectively. After that, based on the stitching constraints 1910, stitching 1907 is conducted to integrate the broadcaster and the compactor to the original circuit. At the end, the synthesized HDL codes 1911 are generated while all reports and errors are saved in the report files 1912.

(82) FIG. 20 shows an example system in which the broadcast scan test method, in accordance with the present invention, may be implemented. The system 2000 includes a processor 2002, which operates together with a memory 2001 to run a set of the broadcast scan test design software. The processor 2002 may represent a central processing unit of a personal computer, workstation, mainframe computer or other suitable digital processing device. The memory 2001 can be an electronic memory or a magnetic or optical disk-based memory, or various combinations thereof. A designer interacts with the broadcast scan test design software run by processor 2002 to provide appropriate inputs via an input device 2003, which may be a keyboard, disk drive or other suitable source of design information. The processor 2002 provides outputs to the designer via an output device 2004, which may be a display, a printer, a disk drive or various combinations of these and other elements.

(83) Having thus described presently preferred embodiments of the present invention, it can now be appreciated that the objectives of the invention have been fully achieved. And it will be understood by those skilled in the art that many changes in construction & circuitry, and widely differing embodiments & applications of the invention will suggest themselves without departing from the spirit and scope of the present invention. The disclosures and the description herein are intended to be illustrative and are not in any sense limitation of the invention, more preferably defined in scope by the following claims.