Interfacial alloy layer for improving electromigration (EM) resistance in solder joints

Abstract

A method of forming a structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint. More specifically, in this structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 m.

Claims

1. A method of forming a joint between two structures able to control electromigration (EM), the method comprising the steps of: preparing a first copper (Cu) structure and a second copper (Cu) structure; preparing a tin (Sn) based solder structure brought into contact with the first and the second copper (Cu) structures; forming a solder joint between the first and the second copper (Cu) structures by raising the temperature to the melting-point temperature of the solder structure and forming intermetallic compounds Cu3Sn and Cu6Sn5 inside between the solder structure and the first and second copper (Cu) structures; and aging the solder joint (maintaining high-temperature conditions) for 10 to 2,000 hours in a temperature range of 150 C. to 200 C. until the thickness of the grown intermetallic compound Cu3Sn (interfacial) alloy layer exceeds 1.5 m on both an interface between the first copper (Cu) structure and a first end of the solder joint, and an interface between the second copper (Cu) structure and a second end of the solder joint opposite to the first end, wherein a thickness of the intermetallic compound Cu.sub.3Sn is less than a thickness of the intermetallic compound Cu.sub.6Sn.sub.5.

2. A method of forming a joint between two structures able to control electromigration (EM), the method comprising the steps of: forming a solder joint by bringing a tin (Sn) based solder structure into contact with a first copper (Cu) structure and a second copper (Cu) structure, raising the temperature to the melting-point temperature of the solder structure, and forming intermetallic compounds Cu3Sn and Cu6Sn5 inside between the solder structure and the first and second copper (Cu) structures; and aging the solder joint (maintaining high-temperature conditions) for 10 to 2,000 hours in a temperature range of 150 C. to 200 C. until the thickness of the grown intermetallic compound Cu3Sn (interfacial) alloy layer exceeds 1.5 m on both an interface between the first copper (Cu) structure and a first end of the solder joint, and an interface between the second copper (Cu) structure and a second end of the solder joint opposite to the first end, wherein a thickness of the intermetallic compound Cu.sub.3Sn is less than a thickness of the intermetallic compound Cu.sub.6Sn.sub.5.

3. The method of claim 2 further comprising: joining a semiconductor chip to the joint, and an integrated circuit substrate joined to the joint.

4. The method of claim 3 further comprising: sealing the semiconductor silicon chip by a lid.

5. The method of claim 2 wherein said aging comprises: aging (maintaining high-temperature conditions) for 10 to 2,000 hours in a temperature range of 150 C. to 200 C. in the copper (Cu) and the intermetallic compounds Cu3Sn, Cu6Sn5 formed in the previously formed solder joint.

6. The method of claim 2 further comprising: forming the first copper (Cu) structure, the second copper (Cu) structure, and the tin (Sn) based solder structure as pillar-like structures having a diameter of 35 m to 100 m.

7. The method of claim 2 further comprising: forming the first copper (Cu) structure, the second copper (Cu) structure, and the tin (Sn) based solder structure as pillar-like structures of 50 m5 m.

8. A semiconductor package comprising a semiconductor silicon chip and integrated circuit substrate communicating electrically via a plurality of joints formed using a method according to claim 2.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a diagram used to explain the configuration of a typical semiconductor package, and a method for manufacturing this package.

(2) FIG. 2 is a diagram used to explain the unique structure of the interfacial alloy layer of the present invention which is able to improve electromigration (EM) resistance in the solder joints of a typical semiconductor package and to explain a manufacturing method for this package.

(3) FIG. 3 is a diagram used to explain defects (voids) produced by electromigration (EM).

(4) FIG. 4 is a diagram evaluating and comparing the effects of electromigration (EM) suppression based on the thickness of the Cu3Sn (interfacial) alloy layer in the present invention.

(5) FIG. 5 is an enlarged view showing the interface between the copper (Cu) and the tin (Sn) immediately after mounting.

(6) FIG. 6 is a graph of the results of testing showing the relationship between the aging and the thickness of the grown Cu3Sn (interfacial) alloy layer.

(7) FIG. 7 is a diagram explaining the principles of void formation described in Non-patent Literature 1 which occurs when the growth of intermetallic compounds (IMC) at the interface between the solder and the under bump metallurgy (UBM) increases considerably due to electromigration (EM).

(8) FIG. 8 is a graph of the results of testing showing the relationship between time and rising resistance values.

DESCRIPTION OF EMBODIMENT

(9) FIG. 1 is a diagram used to explain the configuration of a typical semiconductor package, and a method for manufacturing this package.

(10) In the manufacture of a semiconductor package with multiple terminals, flip chips, including the C4 method, have gradually been adopted as the mounting method in place of conventional wire bonding.

(11) The C4 method is an abbreviation for the controlled collapse chip connection method. Here, the expression C4 is derived from the first letter C in each of the four words.

(12) Hump-shaped conductive protrusions called bumps are formed on the electrodes of a wafer for bonding to a substrate.

(13) The use of this method makes a reduced mounting area and a smaller product possible. Because the wiring in the semiconductor is also shorter, the electrical characteristics are improved.

(14) First, as shown in FIG. 1 (A), hump-shaped conductive protrusions called solder bumps are formed on a silicon chip (semiconductor silicon chip).

(15) A solder bump is a conductor serving as an electrical communication route between the silicon chip (semiconductor silicon chip) and the substrate (integrated circuit substrate).

(16) The bump material is usually solder, which is an alloy of tin (Sn) and lead (Pb), but so-called lead (Pb) free solder is increasingly popular.

(17) This process is called flip chip mounting.

(18) While not shown in the drawing, solder balls may be mounted on the substrate (integrated circuit substrate).

(19) In this case, flux is applied as a fixative to fix the solder balls to the metal electrodes on the substrate (integrated circuit substrate) which are known as pads.

(20) The flux also removes surface oxide film from the pad electrodes. Flux printing precision is critical to the positioning of the flux.

(21) Copper (Cu) is typically used as the pad electrodes in solder bonding.

(22) Pre-soldering can also be performed, which consists of applying solder to the pad electrodes in advance.

(23) Next, there is a heating process as shown in FIG. 1 (B).

(24) The soldering is performed by melting the solder bumps and joining components via metal bonding.

(25) This process is called reflow soldering.

(26) Next, as shown in FIG. 1 (C) there is a process called flux cleaning.

(27) In this process, the flux residue left by the reflow soldering is removed.

(28) Next, as shown in FIG. 1 (D) and FIG. 1 (E), there is a process called the underfill process.

(29) The thermal expansion coefficient of the silicon chip (semiconductor silicon chip) and the thermal expansion coefficient of the substrate (integrated circuit substrate) are different. The thermal stress owing to this difference may cause the terminals to crack and may damage the wiring in the chip.

(30) In this process, an underfill agent is applied to provide a seal.

(31) As shown in FIG. 1 (D), the underfill agent infiltrates between the chip and the substrate due to capillary action.

(32) Here, as shown in FIG. 1 (E), there is a heating process. The infiltrating underfill agent is heat-cured, where a thermosetting resin is used as the underfill agent.

(33) As shown in FIG. 1 (F), a plurality of solder balls is sometimes used as the electrodes mounted on the surface of the substrate (integrated circuit substrate) in what is called a ball grid array (BGA).

(34) Here, as in FIG. 1 (B) and FIG. 1 (E), there is a heating process.

(35) This is often sealed with a metal lid, which is a configuration expected to provide a heat sink effect.

(36) When the semiconductor package has been completed, operation in the silicon chip (semiconductor silicon chip) itself generates heat. High temperatures continue to occur during use after the packaging is complete. These also provide the effects of a heating process.

(37) During and after the manufacture of a semiconductor package, heat is applied in many (often unintended) locations.

(38) The intermetallic compounds (IMC) formed during the manufacturing process and during operation after manufacturing (when a current is applied) is primarily Cu6Sn5. Only a thin film of Cu3Sn is formed.

(39) FIG. 2 is a diagram used to explain the unique structure of the interfacial alloy layer of the present invention which is able to improve electromigration (EM) resistance in the solder joints of a typical semiconductor package and to explain a manufacturing method for this package.

(40) FIG. 2 corresponds to an enlarged view of a single solder bump in FIG. 1.

(41) A tin (Sn) based solder structure (Sn-based solder) is used in the solder bump. A well-known example is SnAg.

(42) Copper (Cu) is used as the pad metal in the solder joint.

(43) Sometimes, intermetallic compounds of copper (Cu) and tin (Sn) are already present on the pads of the substrate (integrated circuit substrate) and the pads of the silicon chip (semiconductor silicon chip).

(44) In the pre-mounting state shown here, pre-soldering has been performed by applying, heating, and melting solder on the pads of the substrate (integrated circuit substrate) in advance.

(45) Nearly all of the intermetallic compounds (IMC) of copper (Cu) and tin (Sn) have the composition of Cu3Sn or Cu6Sn5. These intermetallic compounds (IMC) have different characteristics, which are important to the object of the present invention and are effectively utilized in the present invention.

(46) Usually, the pre-mounting state becomes the after mounting state by applying heat in the reflow soldering process.

(47) In the method of the present invention, a joint is formed between two structures which is able to control electromigration (EM). Put another way, a controlled IMC joint (controlled intermetallic compound joint) is formed.

(48) In the before mounting state, a copper (Cu) structure is prepared as the pad on the silicon chip (semiconductor silicon chip) side. A tin (Sn) based solder structure is prepared and brought into contact with this copper (Cu) structure.

(49) In the before mounting state, the copper (Cu) structure on the silicon chip (semiconductor silicon chip) side is joined with the tin (Sn) based (ball-shaped) solder structure, and intermetallic compounds are formed between them.

(50) From the before mounting state, the copper (Cu) structure on the substrate (integrated circuit substrate) side and the tin (Sn) based solder structure (pre-soldered structure) are joined, and intermetallic compounds are formed between the two.

(51) A good wettability and compatibility can be obtained by using the same composition between the (ball-shaped) solder and the (pre-soldered) solder.

(52) The intermetallic compounds Cu3Sn and Cu6Sn5 are formed in the joint between the copper (Cu) and the tin (Sn). At this stage, as shown in the enlarged drawing, the Cu6Sn5 is thin and the Cu3Sn is very thin.

(53) When the temperature is raised above the melting-point temperature of the solder structure, a solder joint is formed between the solder structure and the copper (Cu) structure, and the intermetallic compounds Cu3Sn and Cu6Sn5 are formed inside. The state shown in the drawing is the after mounting state.

(54) In the method of the present invention, the solder joint is additionally aged (high-temperature conditions are maintained) for 10 to 2,000 hours in a temperature range of 150 C. to 200 C.

(55) In this unique aging process, the thickness of the intermetallic compound Cu3Sn (interfacial) alloy layer exceeds 1.5 m in the copper (Cu) and the intermetallic compounds Cu3Sn, Cu6Sn5 formed in the previously formed solder joint.

(56) The state shown in the drawing is the after aging state.

(57) FIG. 3 is a diagram used to explain defects (voids) produced by electromigration (EM).

(58) In both the upper and the lower drawings, the unique aging process of the present invention is not performed (no aging).

(59) In the test conditions for the upper drawing, SnAg is joined to a Cu post without a barrier.

(60) Here, Kirkendall voids occur near the Cu on the upper side of the chip.

(61) These voids are caused by EM. These voids caused by EM grow as current flows through.

(62) In the test conditions for the lower drawing, 100% Sn is joined to a Cu post, and nickel (Ni) is used as an anti-dispersion layer.

(63) When a Ni barrier is provided, Kirkendall voids are kept from occurring near the Cu on the upper side of the chip.

(64) However, the occurrence of voids caused by EM cannot be completely avoided.

(65) Also, the copper pads on the organic substrate side elute into the solder. The portions with hardly any Cu are visible. This may have an adverse effect on its function as a conductor, and the resistance may rise.

(66) FIG. 4 is a diagram evaluating and comparing the effects of electromigration (EM) suppression based on the thickness of the Cu3Sn (interfacial) alloy layer which is aged in the present invention.

(67) In this test, a first copper (Cu) structure, a second copper (Cu) structure, and a tin (Sn) based solder structure are prepared as pillar-shaped structures with a diameter of 35 m to 100 m. The diameter here is 50 m5 m. This corresponds closely to the miniaturization for a joining pitch used in semiconductor chips.

(68) In this test, the current density is 7 kA/cm2.

(69) The present inventor came to realize that the thickness of the Cu3Sn is important to the suppression of electromigration (EM).

(70) More specifically, it became clear that electromigration (EM) could be effectively suppressed if the (interfacial) alloy layer of intermetallic compound Cu3Sn of the solder joint is grown to a thickness exceeding 1.5 m in the copper (Cu) and the intermetallic compounds Cu3Sn, Cu6Sn5 formed in the previously formed solder joint.

(71) The near absence of EM voids was confirmed.

(72) FIG. 5 is an enlarged view showing the interface between the copper (Cu) and the tin (Sn) immediately after mounting.

(73) The Cu3Sn has not grown to a significant thickness immediately after mounting.

(74) When the diffusion coefficients of the Cu in the Cu3Sn and in the Cu6Sn5 were compared under temperature conditions of 150 C., the diffusion coefficient of the Cu3Sn was 1/18th that of the Cu6Sn5.

(75) In principle, the Cu3Sn forms a diffusion-suppressing barrier which is believed to significantly suppress the elution of Cu and the formation of voids.

(76) Because Cu3Sn has a flat organizational structure compared to the irregular organizational structure of Cu6Sn5, it is believed to be suitable for use as a barrier layer.

(77) FIG. 6 is a graph of the results of testing showing the relationship between the aging and the thickness of the grown Cu3Sn (interfacial) alloy layer. Here, it is clear that an electromigration (EM) suppressing effect is obtained when the (interfacial) alloy layer of the intermetallic compound Cu3Sn has grown to a thickness exceeding 1.5 m. At an approximate thickness of 0.5 m, the electromigration (EM) suppressing effect is insufficient (NG).

(78) FIG. 7 is a diagram explaining the principles of void formation described in Non-patent Literature 1 which occurs when the growth of intermetallic compounds (IMC) at the interface between the solder and the under bump metallurgy (UBM) increases considerably due to electromigration (EM).

(79) This provides a theoretical explanation of the compositions of Cu3Sn and Cu6Sn5, which are the intermetallic compounds of copper (Cu) and tin (Sn).

(80) FIG. 8 is a graph of the results of testing showing the relationship between time and rising resistance values in the aging of the present invention.

(81) Because the occurrence of voids appears in the form of increased resistance, this can be used indirectly (non-destructively) to determine their presence.

(82) Compared to a situation with no aging, aging results in hardly any increased resistance, and maintains a low resistance value.