Abstract
A substrate-based circuit (31) provides a carrier substrate (2), wherein a bond layer (5) is embodied on at least one part of the carrier substrate (2), and wherein a contact layer (6) which forms at least one conductor line (7) and/or at least one antenna element (8) is embodied on at least one first part (5.sub.1) of the bond layer (5). The carrier substrate (2) provides at least one fastening element (20), which is deposited at the outer region of the carrier substrate (2) and projects beyond the outer region of the carrier substrate (2).
Claims
1. A method for manufacturing a substrate-based circuit with a carrier substrate for being attached within a hollow conductor and with at least one conductor line and/or at least one antenna element arranged respectively on the carrier substrate, the method comprising: applying, by deposition, at least one fastening element to an outer region of the carrier substrate, the at least one fastening element projecting beyond the outer region of the carrier substrate; and attaching the carrier substrate to and within the hollow conductor.
2. The method according to claim 1, further including: applying the carrier substrate to at least one sacrificial carrier; applying a bond layer to the carrier substrate; applying, to the bond layer, a contact layer from which the at least one conductor line and/or the at least one antenna element is formed; and structuring the at least one conductor line and/or the at least one antenna element.
3. The method according to claim 2, wherein the applying the carrier substrate includes: applying a second sacrificial carrier to a first sacrificial carrier; and/or applying the carrier substrate to the second sacrificial carrier.
4. The method according to claim 2, wherein the structuring includes: removing the contact layer except for a part on which the at least one conductor line and/or the at least one antenna element is formed, or a part which is embodied as a support surface for at least one electrical component; removing the bond layer except for a first part which is disposed beneath the part of the contact layer on which the at least one conductor line and/or the at least one antenna element is formed; and/or removing the bond layer except for at least one second part which provides a defined distance from the support surface on the contact layer which is embodied for the support of the at least one electrical component.
5. The method according to claim 4, wherein the structuring further includes: coating the carrier substrate together with the at least one second part of the bond layer and the contact layer with a solder-stop layer; and removing the solder-stop layer except for regions which are disposed at least partially on the at least one second part of the bond layer and/or which are disposed in a region between the at least one second part of the bond layer and the support surface and/or which are disposed at least partially on the support surface.
6. The method according to claim 2, wherein the applying by deposition includes: removing an edge of the carrier substrate, thereby exposing a portion of the at least one sacrificial carrier; coating the exposed portion of the at least one sacrificial carrier and the carrier substrate having the bond layer and the contact layer thereon with a further bond layer and with a further contact layer; removing the further bond layer and the further contact layer from regions on the carrier substrate on which no fastening elements for stabilization are to be embodied; and removing the further bond layer and the further contact layer from regions on the at least one sacrificial carrier on which no fastening elements are to be embodied except for an edging which surrounds the at least one fastening element at a defined distance and connects the at least one fastenings element via at least one web.
7. The method according to claim 6, further including: removing the at least one sacrificial carrier; and removing a portion of the further bond layer that was coated on the at least one sacrificial carrier.
8. The method according to claim 7, further including: removing the edging by cutting with a laser through the at least one web of the at least one fastening element.
9. The method according to claim 5, further including: coating at least one region of the bond layer with the contact layer before the contact layer is coated with the solder-stop layer and/or a further bond layer; and coating at least parts of the solder-stop layer or of the further bond layer which are arranged above the at least one region of the bond layer with a further contact layer, thereby forming a capacitor, wherein a capacitance of the capacitor is adjusted via a variance of a thickness of the solder-stop layer and/or of the further bond layer and/or a size of the at least one region of the bond layer.
10. The method according to claim 3, wherein: the first sacrificial carrier contains Si; and/or the second sacrificial carrier contains SiO.sub.2; and/or the bond layer contains Ti, TiW, and/or Cr; and/or the carrier substrate comprises Si.sub.3N.sub.4 and/or diamond; and/or the contact layer contains Au.
11. A substrate-based circuit comprising: a hollow conductor; a carrier substrate attached within the hollow conductor; a bond layer embodied on at least one part of the carrier substrate; a contact layer embodied on at least one first part of the bond layer that forms at least one conductor line and/or at least one antenna element; and at least one fastening element deposited at an outer region of the carrier substrate, the at least one fastening element projecting beyond the outer region of the carrier substrate.
12. The substrate-based circuit according to claim 11, wherein: the at least one fastening element is formed of a same material as a material of the contact layer; and/or in the outer region in which the at least one fastening element is connected to the carrier substrate, another bond layer is arranged between the at least one fastening element and the carrier substrate.
13. The substrate-based circuit according to claim 11, wherein: the contact layer is embodied as a support surface for support of an electronic component; and/or a second part of the bond layer is embodied at a defined distance from the support surface; and/or at least part of the second part of the bond layer and/or a region between the second part of the bond layer and the support surface and/or at least a part of the support surface is provided with a solder-stop layer.
14. The substrate-based circuit according to claim 13, wherein: the contact layer is located on an area between the bond layer and the solder-stop layer; a further contact layer is located on a further area, of identical size as the contact layer, on the solder-stop layer or on the solder-stop layer and the bond layer; the further contact layer is connected in an electrically conducting manner to the at least one fastening element; and the contact layer is connected in an electrically conducting manner to the at least one conductor line and/or to the at least one antenna element, thereby forming a capacitor.
15. The substrate-based circuit according to claim 13, wherein: the bond layer contains Ti, TiW, or Cr; and/or the carrier substrate is made from Si.sub.3N.sub.4 and/or diamond; and/or the solder-stop layer is made from Si.sub.3N.sub.4; and/or the contact layer contains Au.
16. A hollow conductor comprising: two hollow-conductor segments rigidly connected to one another, each hollow-conductor segment including a groove; and a substrate-based circuit including: a carrier substrate, a bond layer embodied on at least one part of the carrier substrate, a contact layer embodied on at least one first part of the bond layer that forms at least one conductor line and/or at least one antenna element, and at least one fastening element deposited at an outer region of the carrier substrate, the at least one fastening element projecting beyond the outer region of the carrier substrate, and the at least one fastening element being clamped between the two hollow-conductor segments such that the substrate-based circuit is arranged centrally within a space in the hollow conductor formed by the respective grooves.
17. The hollow conductor according to claim 16, wherein at least one hollow-conductor segment provides at least one recess that is arranged perpendicular to the at least one antenna element such that a microwave signal can be supplied to the at least one antenna element.
Description
(1) Different exemplary embodiments of the invention are described below by way of example with reference to the drawings. Identical subject matters provide the same reference numbers. In detail, the corresponding Figs. of the drawings show:
(2) FIG. 1A an exemplary embodiment of a layer structure from which the carrier substrate according to the invention with a circuit arranged on it is created;
(3) FIG. 1B the layer structure in which a contact layer is structured;
(4) FIG. 1C the layer structure in which a bond layer exposed beneath the contact layer is structured;
(5) FIG. 1D the layer structure in which the exposed contact layer, the partially exposed bond layer and a partially exposed carrier substrate are coated with a solder-stop layer;
(6) FIG. 1E the layer structure in which the solder-stop layer is structured;
(7) FIG. 1F the layer structure in which an outer edge of the carrier substrate is removed so that a second sacrificial carrier disposed beneath it becomes evident;
(8) FIG. 1G the layer structure in which the exposed, second sacrificial carrier, the exposed carrier substrate, the exposed bond layer, the exposed contact layer and the externally disposed solder-stop layer are coated with a further bond layer;
(9) FIG. 1H the layer structure in which the further bond layer is coated with a further contact layer;
(10) FIG. 1I the layer structure in which the further bond layer and the further contact layer are structured in such a manner that the further bond layer and the further contact layer is preserved only at those positions in which the fastening elements are to be formed on the outer region of the carrier substrate and on the second sacrificial carrier, and at those positions at which the edging is to be formed on the second sacrificial carrier which combine all fastening elements with one another via webs;
(11) FIG. 1J the layer structure in which a first sacrificial carrier has been removed;
(12) FIG. 1K the layer structure in which a second sacrificial carrier has been removed;
(13) FIG. 1L the layer structure in which at least one part of the bond layer arranged on the removed second sacrificial carrier has been removed;
(14) FIG. 2A a further exemplary embodiment of the layer structure in which, between the contact layer and the further contact layer, a solder-stop layer and/or the further bond layer are enclosed, thereby embodying a capacitor;
(15) FIG. 2B an exemplary embodiment of a plan view of the carrier substrate according to the invention with a conductor line and a support surface for an electrical component;
(16) FIG. 3A a further exemplary embodiment of a plan view of the carrier substrate according to the invention with an applied circuit structure, which, alongside four fastening elements also shows an edging which connects together the four fastening elements in each case via two webs;
(17) FIG. 3B an exemplary embodiment of a plan view of the carrier substrate according to the invention with an applied circuit structure, which provides four fastening elements of which the webs have been cut by means of a laser;
(18) FIG. 4A an exemplary embodiment of a three-dimensional view of a hollow conductor according to the invention which comprises two segments into which the carrier substrate according to the invention with the applied circuit structure is inserted;
(19) FIG. 4B a further exemplary embodiment of another three-dimensional view of the hollow conductor according to the invention which comprises two segments into which the carrier substrate according to the invention with the applied circuit structure is inserted;
(20) FIG. 5A an exemplary embodiment of a flow chart for the method according to the invention for manufacturing the carrier substrate;
(21) FIG. 5B a further exemplary embodiment of a flow chart for the method according to the invention which explains the construction of the layer structure;
(22) FIG. 5C a further exemplary embodiment of a flow chart for the method according to the invention which explains the construction of the layer structure;
(23) FIG. 5D a further exemplary embodiment of a flow chart for the method according to the invention which explains the structuring of the circuit;
(24) FIG. 5E a further exemplary embodiment of a flow chart for the method according to the invention which explains the passivation of the surface in the proximity of a support surface;
(25) FIG. 5F a further exemplary embodiment of a flow chart of the method according to the invention which explains the removal of sacrificial carriers;
(26) FIG. 5G a further exemplary embodiment of a flow chart for the method according to the invention which explains the manufacture of fastening elements;
(27) FIG. 5H a further exemplary embodiment of a flow chart of the method according to the invention which explains the cutting out of the substrate-based circuit; and
(28) FIG. 5I a further exemplary embodiment of a flow chart for the method according to the invention which explains the manufacture of a capacitor on a substrate layer.
(29) FIG. 1A shows a layer structure 1 from which the carrier structure 2 according to the invention with a circuit arranged on it is built up. The layer structure 1 comprises a conventional wafer which is preferably made of silicon (Si). The Si layer is preferably a first sacrificial layer 3, as will be explained later in the description. In this context, the silicon wafer can provide a size of, for example, 2 inches or larger.
(30) A second sacrificial layer 4 is preferably applied to the first sacrificial layer 3. The second sacrificial layer 4 preferably comprises silicon oxide (SiO.sub.2). The subsequently free-standing carrier substrate 2 is applied to the second sacrificial layer 4. The carrier substrate 2 is preferably silicon nitride (Si.sub.3N.sub.4) or diamond. In this context, the selection of the respective material is defined in particular by the concrete electrical, thermal and mechanical requirements.
(31) A bond layer 5 is applied to the carrier substrate 2. This bond layer 5 preferably comprises titanium (Ti) or titanium tungsten (TiW) and/or chromium (Cr). The bond layer can be applied, for example, by a deposition process. Following this, a contact layer 6 is applied to the bond layer 5. The contact layer 6 is preferably made of gold.
(32) The thickness of the contact layer 6 is, for example, 100 nm to 500 nm. The thickness of the bond layer is preferably 10 nm to 50 nm. The thickness of the carrier substrate is preferably 1 m to 20 m, by further preference 5 m to 20 m. The carrier substrate 2 is therefore significantly thinner than the conventional ceramic circuit carriers or the individual layers of a printed-circuit board which each comprise individual foils glued to one another. The layer thickness for the first sacrificial carrier 3 and the second sacrificial carrier 4 is selected so that, as far as possible, the processing takes place in a manner not susceptible to faults.
(33) In this context, the layer structure 1 itself can adopt an arbitrary shape. Conceivable shapes are, for example, rectangles, squares or L-shaped formations, however, circular or elliptical segments can also be realised. There are also no limits to the length and the breadth of the layer structure 1 from which the carrier substrate 2 is subsequently made.
(34) FIG. 1B shows the layer structure in which the contact layer 6 is structured. It is clearly evident that the contact layer 6 has been removed with the exception of the part which forms the at least one conductor line 7 and/or the at least one antenna element 8 or the part which is formed as a support surface 9 for at least one electrical component 10. The contact layer 6 is structured in this context by means of photolithography and wet-chemical etching steps. Residues of a photo-paint 11.sub.1 on the part of the contact layer 6 which has not been removed are still clearly evident.
(35) FIG. 1C shows the layer structure 1 in which a bond layer 5 exposed beneath the contact layer 6 is structured. In this context, the bond layer 5 is removed with the exception of a first part 5.sub.1, which is disposed beneath the part of the contact layer 6 on which the at least one conductor line 7 and/or the at least one antenna element 8 is formed. Furthermore, the part of the bond layer 5 can optionally be removed with the exception of at least one second part 5.sub.2 which provides a defined distance from a support surface 9 on the contact layer 6, which is embodied for the support of at least one electrical component 10. The second part 5.sub.2 of the bond layer 5 in this context represents the adhesive connection with a solder-stop layer or the dielectric of a capacitor, as will be explained in the following.
(36) A photo-paint 11.sub.2 which is disposed on the second part 5.sub.2 of the bond layer 5 and on the other remaining contact layer 6 is also clearly evident. This photo-paint 11.sub.2 can be readily washed away in due course. The use of other photo-paints has not been further illustrated for reasons of improved visual clarity in the remaining structuring steps. The carrier substrate 2 and the first and second sacrificial carrier 3, 4 remain unchanged.
(37) FIG. 1D shows the layer structure 1 in which the exposed contact layer 6, the partially exposed bond layer 5 and a partially exposed carrier substrate 2 have been coated with a solder-stop layer 12. In this context, the carrier substrate 2 together with the second part 5.sub.2 of the bond layer 5 and the contact layer 6 is coated with the solder-stop layer 12. Such a solder-stop layer, which is also referred to as a solder-stop paint, serves, on the one hand, for protection from corrosion and mechanical damage and, on the other hand, during soldering, prevents the wetting of the surfaces on the printed-circuit board coated with it with soldering tin. The solder-stop layer therefore preferably comprises Si.sub.3N.sub.4 and provides a thickness from, for example, 500 nm to, for example, 1500 nm. As will be explained later, different materials and different thicknesses are also possible, in particular, for the adjustment of a capacitance.
(38) FIG. 1E shows the layer structure 1 in which the solder-stop layer 12 has been structured. In this context, the solder-stop layer 12 has been removed with the exception of the regions which are disposed at least partially on the second part 5.sub.2 of the bond layer 5 and/or which are disposed in a region between the second part 5.sub.2 of the bond layer 5 and the support surface 9 and/or which are disposed at least partially on the support surface 9. In the example from FIG. 1E, it is clearly evident that the solder-stop layer 12 has been partially removed in the region of the support surface 9. This allows the rigid soldering of an electrical component 10 to the support surface 9. It is also clearly evident that the regions between the second part 5.sub.2 of the bond layer 5 and the support surface 9 are lower and form a kind of indentation which subsequently serves to receive the material of the solder-stop layer 12 liquefied through the soldering process, so that the electrical component 10 can be rigidly soldered in an optimal manner.
(39) For the case that no solder barriers in the form of a second part 5.sub.2 of the bond layer 5 are required, these can also be omitted. This is possible, in particular, alongside the contact layer 6 embodied as conductor line 7 or alongside the contact layer 6 embodied as an antenna element 8. In this case, the at least one conductor line 7 and/or the at least one antenna element 8 is preferably completely covered with the solder-stop layer 12, which leads to a passivation of the surface and protects from corrosion. Even if, for reasons of compactness, FIG. 1E shows an application of the Si.sub.3N.sub.4 solder-stop layer 12 to the Si.sub.3N.sub.4 carrier substrate 2, a further separating layer, which is not illustrated and has already been removed in FIG. 1E, is disposed between the two layers.
(40) It has not been shown that the support surface 9 not covered by the solder-stop layer 12 can be filled up again through the application of an additional contact layer, which is also preferably made of gold, in such a manner that the height of the support surface 9 corresponds to the height of the solder-stop layer 12, so that the electrical component 10 can be aligned and soldered in an optimal manner. The carrier substrate 2 and the first and second sacrificial carrier 3, 4 have not been changed in FIG. 1E.
(41) FIG. 1F shows the layer structure 1, in which an external edge 15 of the carrier substrate 2 has been removed, so that a second sacrificial layer 4 disposed beneath it comes into view. The width of the edge 15 in this context can be selected arbitrarily. By preference, the edge 15 is disposed on all sides of the carrier substrate 2, independently of the shape ultimately adopted by the carrier substrate 2. The width of the edge can be, for example, less than 1 mm or less than 700 m or less than 500 m.
(42) FIG. 1G shows the layer structure 1 in which the exposed second sacrificial carrier 4, the exposed carrier substrate 2, the exposed bond layer 5, the exposed contact layer 6 and the externally disposed solder-stop layer 12 are coated with a further bond layer 16. This further bond layer 16 is preferably selected from one of the materials from which the bond layer 5 is made. Accordingly, the further bond layer 16 provides the same hatching as the bond layer 5. Materials for the further bond layer 16 can include, for example, titanium, titanium tungsten or chromium.
(43) FIG. 1H shows the layer structure 1 in which the further bond layer 16 is coated with a further contact layer 17. This further contact layer 17 preferably comprises the same material from which the contact layer 6 is already made. By preference, the further contact layer 17 is therefore made of gold. The thickness of the further bond layer 16 is disposed within a range from 10 nm to 50 nm. The thickness of the further contact layer 17 is disposed within a range from, for example, 500 nm to 3 m. This range is adjustable. In the drawings, the transitions between these further layers are illustrated abruptly. In reality, the transitions are gently rounded transitions.
(44) FIG. 1I shows the layer structure 1 in which the further bond layer 16 and the further contact layer 17 are structured in such a manner that the further bond layer 16 and the further contact layer 17 remain only at the positions at which the fastening elements 20 are to be formed on the outer region of the carrier substrate 2 and on the second sacrificial carrier 4 and at the positions at which the edging 21, which connects all of the fastening element 20 via webs 22, is to be formed. Accordingly, the further bond layer 16 and the further contact layer 17 also remain at those positions which subsequently form the webs 22. A corresponding construction is shown in FIG. 3A and will be explained later. It is also possible that, in a first step, only the further contact layer 17 is removed, whereas the further bond layer 16 is removed in a subsequent step. The removal of the further contact layer 17 and of the further bond layer 16 is achieved by means of photolithography and wet chemical etching steps.
(45) FIG. 1J shows the layer structure 1 in which a first sacrificial carrier 3 has been removed. The first sacrificial carrier 3 which preferably comprises silicon, can be removed by undercutting, for example, by means of potassium hydroxide at a temperature of, for example, 80 C.
(46) FIG. 1K shows the layer structure 1 in which a second sacrificial carrier 4 has been removed. Accordingly, all sacrificial carriers 3 and 4 have been removed.
(47) FIG. 1L shows the layer structure 1 in which at least a part of the bond layer 16 arranged on the removed second sacrificial carrier 4 has been removed. A plan view of the layer structure 1 as illustrated in FIG. 1, which will be explained in greater detail below, is shown in FIG. 3A.
(48) FIG. 2A shows the layer structure 1 in which a capacitor or respectively a condenser is embodied through the contact layer 6 and the further contact layer 17, between which the solder-stop layer 12 and/or the further bond layer 16 are enclosed. For this purpose, in FIG. 1C, the contact layer 6 is preferably left on the second part 5.sub.2 of the bond layer 5, and it is ensured that the contact layer 6 is also connected in an electrically conducting manner via the second part 5.sub.2 of the bond layer 5 to the part of the contact layer 6 which forms the conductor line 7. In the exemplary embodiment from FIG. 2A, there is therefore no interruption between the first part 5.sub.1 of the bond layer 5 and the second part 5.sub.2 of the bond layer 5. Following this, the solder-stop layer 12 is applied correspondingly, as shown in FIG. 1D and in FIG. 1E. In the further course, the further bond layer 16 can then be applied over the solder-stop layer 12, wherein the further contact layer 17 is applied to the further bond layer 16, thereby forming a capacitor. The capacitor is formed between the mutually overlapping area of the contact layer 6 and the further contact layer 17. The level of the capacitance can be adjusted through the size of the mutually overlapping area and/or through the thickness of the dielectric which is formed by the solder-stop layer 12 and/or the further bond layer 16 between the contact layer 6 and the further contact layer 17.
(49) In this case, the further contact layer 17 is connected in an electrically conducting manner to the fastening element 20. As will be explained in greater detail later, the contact layer 6 forms the at least one conductor line 7 and/or the at least one antenna element 8.
(50) FIG. 2B shows a plan view of the carrier substrate 2 with a conductor line 7 and a support surface 9 for an electrical component 10. It is clearly evident that the support surface 9 is surrounded by a solder-stop layer 12, which ensures that the soldering means (for example, soldering tin) does not flow away in uncontrolled tracks, so that reproducible solder pads can be obtained. The conductor line 7 can provide a structural width of, for example, less than 50 m, by preference, less than 20 m. The support surface is therefore not true to scale.
(51) The effect of the bond layer as a solder-stop does not occur as a mechanical barrier but by preventing a wetting/alloying with the gold of the contact layer. The second part 5.sub.2 of the bond layer 5 therefore functions as a solder barrier. The conductor line 7, which is formed by the contact layer 6 is electrically isolated from a further ground surface 25. The further ground surface 25 can also already be part of the fastening element 20.
(52) FIG. 3A shows a plan view of an exemplary embodiment of the carrier substrate 2 according to the invention with an applied circuit structure, which, alongside four fastening elements 20, also shows an edging 21, which connects each of the four fastening elements to one another, for example, via two (or more or fewer) webs 22 in each case. It is clearly evident that the carrier substrate 2 provides a rectangular shape. Two fastening elements 20 are disposed respectively at two sides of the carrier substrate 2 in each case. These are preferably embodied parallel to the conductor line. FIGS. 1A to 1L show a section through the axis A. Each fastening element 20 is connected to an outer edging 21, in each case via two webs 22. The distance between the outer edging 21 and the carrier substrate 20 can be selected arbitrarily.
(53) Two antenna elements 8 and the associated line structures are also clearly evident. Two filters 30 which filter the high-frequency microwave signal are thus also illustrated. The carrier substrate 2 can have any arbitrary shape. This shape is surrounded by an edging 21, as shown in FIG. 3A, wherein the edging 21 is connected to the carrier substrate 2 only via the fastening elements 20. The number of fastening elements 20 is not restricted to four, but can provide an arbitrary number. Dependent upon the thickness of the carrier substrate 2, more or fewer fastening elements are required. The shape and the width of the carrier substrate 2 also mean that a different number of fastening element 20 is required. The fastening elements 20 provide an excellent mechanical stability to the carrier substrate 2 which is preferably less than 20 m thin. At the same time, the fastening elements 20 allow the removal of surplus thermal energy via the former to a corresponding heat sink, for example, in the form of a housing. This factual situation will be described in greater detail with reference to FIGS. 4A and 4B. The substrate-based circuit 31 which is illustrated in FIG. 3A is the end product of the steps described in FIGS. 1A to 1L.
(54) FIG. 3B shows a plan view of an exemplary embodiment according to the invention of the carrier substrate 2 according to the invention with an applied circuit structure which provides four fastening elements 20, of which the webs 22 have been separated preferably by means of a laser. The substrate-based circuit 31, which has been formed through separation of the frame 21, that is, of the edging 21, by means of cutting through the webs 22 from FIG. 3A, is clearly evident. The support surface 9 in this context can already be fitted with the electronic component 10 before the cutting through of the webs 22 by means of the laser. However, it is also possible for the electronic component 10 to be fitted only when the webs 22 and the edging 21 have already been removed.
(55) The region of the conductor line 7 which is disposed at the edge of the substrate-based circuit 31 can be used for the purpose of supplying a bias (English: BIAS) to the substrate-based circuit 31.
(56) The carrier substrate 2 in the substrate-based circuit 31 in FIG. 3B is clearly evident, wherein the carrier substrate 2 is coated with a solder-stop layer 12. However, before this, a bond layer 5 is embodied on the carrier substrate 2, wherein a contact layer 6 which forms at least one conductor line 7 and/or at least one antenna element 8 is embodied on at least one first part 5.sub.1 of the bond layer 5. In this context, the carrier substrate 2 provides at least one fastening element 20, which is deposited on the outer region of the carrier substrate 2 and projects beyond the outer region of the carrier substrate 2. In this context, deposited is understood to refer to a mechanically stable, non-detachable connection, as has been described in FIGS. 1A to 1L. The deposition can be implemented, for example, through a physical PVD or chemical CVD process. The fastening elements 20 can be further reinforced through a galvanic process. In this context, the outer region of the carrier substrate 2 is freely selectable. By preference, the outer region is smaller than 300 m, by particular preference smaller than 200 m or even smaller than 100 m.
(57) The frequencies of the microwave signal which is coupled via at least one antenna element 1 to the substrate-based circuit 31 is, for example, at least 100 GHz and extends, for example, up to 2 THz.
(58) The at least one fastening element 20 is preferably formed, in this context, from the same material from which the contact layer 6 is made. This material is preferably gold. The region in which the at least one fastening element 20 is connected to the carrier substrate 2 further comprises a further bond layer 16 which is arranged between the carrier substrate 2 and the fastening element 20.
(59) Furthermore, it is clearly evident that at least one part of the contact layer 6 is embodied as a support surface 9 for the support of an electronic component 10. As already explained, a second part 5.sub.2 of the bond layer 5 is disposed at a defined distance, which is adjustable, from the support surface 9, wherein at least a part of the second part 5.sub.2 of the bond layer 5 is provided with a solder-stop layer 12. The region between the second part 5.sub.2 of the bond layer 5 and the support surface 9 is also provided with a solder-stop layer 12. Furthermore, the same applies for at least a part of the support surface 9. It is also possible for a contact layer 6, 17 to be embodied on an area between the bond layer 5 and the solder-stop layer 12, wherein the second part 5.sub.2 or a further part of the bond layer 5 is preferably used, and for a contact layer 6, 17 also to be embodied on a further area of equal size on the solder-stop layer 12, wherein the two contact layers 6, 17 are not connected to one another in an electrically conducting manner and are connected to the at least one fastening element 20 or to the at least one conductor line 7, thereby forming a capacitor. The level of the capacitance can be adjusted through the thickness of the solder-stop layer 12 and the area of the structured contact layers 6, 17.
(60) FIG. 4A shows a three-dimensional view of an exemplary embodiment of a hollow conductor 40 according to the invention, which is made from two segments 41.sub.1, 41.sub.2, into which the carrier substrate 2 according to the invention, that is, the substrate-based circuit 31 with the applied circuit structure, is inserted. It is clearly evident that the hollow conductor 40 is formed from two hollow-conductor segments 41.sub.1, 41.sub.2 capable of being connected rigidly to one another. In this context, a first hollow-conductor segment 41.sub.1 can be connected rigidly to a second hollow-conductor segment 41.sub.2 via a screw connection and/or welded connection, which is not illustrated. By preference, each hollow-conductor segment 41.sub.1, 41.sub.2 provides a groove 42.sub.1, 42.sub.2, wherein the at least one fastening element 20 is pressed between the two segments 41.sub.1, 41.sub.2, so that the substrate-based circuit 31 is arranged centrally within the hollow conductor 40 formed from the two grooves 41.sub.1, 41.sub.2. In this context, the depth of each groove 42.sub.1, 42.sub.2 can depend upon the respective operating frequency. The higher the operating frequencies are, the less deeply the grooves need to be embodied.
(61) An electrical component 10 which is mounted on the support surface 9 and connected in an electrically conducting manner to the at least one electrical conductor line 7 is also clearly evident. The at least one electrical component 10 can be, for example, a mixer.
(62) Furthermore, it is clearly evident that the substrate-based circuit 31 provides four fastening elements 20, wherein, by means of fastening element 20, a part projects beyond the edge of the carrier substrate 2. This part of each fastening element 20 which projects beyond the edge of the carrier substrate 2 is clamped between the two segments 41.sub.1, 41.sub.2 after these have been rigidly connected to one another. In this context, each groove 42.sub.1, 42.sub.2 is at least precisely as wide as the carrier substrate 2.
(63) It is also clearly evident that at least one hollow-conductor segment 41.sub.1, 41.sub.2 provides at least one recess 43.sub.1, 43.sub.2, wherein the at least one recess 43.sub.1, 43.sub.2 is arranged perpendicular (or horizontally, not shown) relative to the at least one antenna element 8, wherein a microwave signal can accordingly be supplied to the at least one antenna element 8 via the at least one recess 43.sub.1, 43.sub.2. The at least one recess 43.sub.1, 43.sub.2 itself therefore forms a hollow conductor. The perpendicular alignment is illustrated, for example, by the dashed line. In this context, a microwave signal can be supplied to an antenna element 8, for example, via the first recess 43.sub.1. Via the antenna element 8, the microwave signal is coupled to the at least one conductor line 7 and is further processed by the electronic component 10 and, for example, stepped up in its frequency. Via the further antenna element 8, which is also connected in an electrically conducting manner to the electronic component 10, the microwave signal stepped up in its frequency can be guided out of the hollow conductor 40 via the second recess 43.sub.2.
(64) Such a hollow conductor 40 can be used, for example, in order to generate radar signals which provide a very high-frequency for weather satellites.
(65) FIG. 4B shows a further three-dimensional view of an exemplary embodiment according to the invention of the hollow conductor 40 according to the invention which is made from two segments 41.sub.1, 41.sub.2 into which the carrier substrate 3 according to the invention with the applied circuit structure is inserted. It is clearly evident how at least a part of the fastening elements 20 is supported on a surface of the second segment 41.sub.2 of the hollow conductor 40. Via this part of the fastening element 20, the substrate-based circuit is rigidly and, above all, stably held in a central position within the hollow conductor 40 formed after the connection of the two hollow-conductor segments 41.sub.1, 41.sub.2. As a result of the fact that both segments 41.sub.1, 41.sub.2 are rigidly connected to one another, an electrical contact with the housing ground of the hollow conductor 40 can also be provided via the connecting element 20. The hollow conductor 40 can thus serve as a heat sink in order to absorb surplus thermal energy.
(66) It is also possible for the surface of the first hollow-conductor segment 41.sub.1 and the surface of the second hollow-conductor segment 41.sub.2, which are partially in contact and between which some of the fastening elements 20 are inserted, to provide a contour or respectively profile, wherein the contour or respectively the profile of the corresponding surface of the first hollow-conductor segment 41.sub.1 is inverse to the contour or respectively the profile of the corresponding surface of the second hollow-conductor segment 41.sub.2, so that the surface of the first hollow-conductor segment 41.sub.1 engages in the surface of the second hollow-conductor segment 41.sub.2 and vice versa. Accordingly, the fastening elements 20 are pressed together with the hollow conductor even more effectively.
(67) FIG. 5A shows an exemplary embodiment of a flow chart for the method according to the invention. In a first method step S.sub.1, at least one fastening element 20 is applied through a deposition process to an outer region of the carrier substrate 2, wherein the at least one fastening element projects beyond the outer region of the carrier substrate 2. For the deposition of the fastening element 20, all known deposition processes, such as PVD (English: physical vapour deposition; German: physikalische Vakuum-Abscheidung) and galvanisation are suitable. In this context, the fastening elements 20 are also referred to as beam leads.
(68) FIG. 5B shows a further exemplary embodiment of a flow chart for the method according to the invention which explains in greater detail the construction of the layer structure 1. In a second method step S.sub.2, the carrier substrate 2 is applied to at least one sacrificial carrier 3, 4. Following this, in method step S.sub.3, a bond layer 5 is applied to the carrier substrate 2. Following this, in method step S.sub.4, a contact layer 6 is formed on the bond layer 7 and/or the at least one antenna element 8. In a further method step S.sub.5, the at least one conductor line 7 and/or the at least one antenna element 8 is structured. In this context, the carrier substrate 2 preferably comprises Si.sub.3N.sub.4 or diamond in the required thickness. The bond layer 5 preferably comprises titanium, titanium tungsten or chromium. The contact layer 6 is preferably made of gold. The conductor lines 7 preferably have a width of, for example, less than 50 m, by further preference less than 20 m. Method step S.sub.5 is illustrated in FIGS. 1B and 1C.
(69) FIG. 5C shows a further exemplary embodiment of a flow chart for the method according to the invention which explains the construction of the layer structure 1. By preference, the method step of applying the carrier substrate S.sub.2 comprises the following sub-method steps. These include method step S.sub.2.sub._.sub.1, which comprises the application of a second sacrificial carrier 4 to the first sacrificial carrier 3. Instead of method step S.sub.2.sub._.sub.1 or in addition to method step S.sub.2.sub._.sub.1, method step S.sub.2.sub._.sub.2 can be implemented. In method step S.sub.2.sub._.sub.2, the carrier substrate 2 is applied to the second sacrificial carrier 4. The first sacrificial carrier 3 is preferably silicon. The second sacrificial carrier 4 is preferably SiO.sub.2.
(70) FIG. 5D shows a further exemplary embodiment of a flow chart for the method according to the invention which explains the structuring of the circuit. Accordingly, the method step of structuring S.sub.5 preferably comprises the method steps S.sub.5.sub._.sub.1 and S.sub.5.sub._.sub.1. In method step S.sub.5.sub._.sub.1, the contact layer 6 is removed with the exception of the part which forms the at least one conductor line 7 and/or the at least one antenna element 8, or respectively the part which is embodied as a support surface 9 for at least one electrical component 10. This step is illustrated in FIG. 1D.
(71) In method step S.sub.5.sub._.sub.2, the bond layer 5 is removed with the exception of a first part 5.sub.1 which is disposed beneath the part of the contact layer 6 on which the at least one conductor line 7 and/or the at least one antenna element 8 is embodied. Alternatively or in addition to this, the bond layer 5 is removed with the exception of at least one second part 5.sub.2 which provides a defined distance from the support surface 9 on the contact layer 6 which is embodied to receive at least one electrical component 10. These steps are shown in FIG. 1C.
(72) FIG. 5E shows a further exemplary embodiment of a flow chart for the method according to the invention which explains the passivation of the surface in the proximity of a support surface 9. For this purpose, method steps S.sub.5.sub._.sub.3 and S.sub.5.sub._.sub.4 are implemented within the method step of structuring S.sub.5, preferably after the method step S.sub.5.sub._.sub.2. In method step S.sub.5.sub._.sub.3, the carrier substrate 2, together with the second part 5.sub.2 of the bond layer 5 and the contact layer 6, is coated with a solder-stop layer 12. This factual situation is illustrated in FIG. 1D.
(73) In method step S.sub.5.sub._.sub.4, the solder-stop layer 12 is removed with the exception of the regions which are disposed at least partially on the second part 5.sub.2 of the bond layer 5 and/or the regions which are disposed in a region between the second part 5.sub.2 of the bond layer 5 and the support surface 9 and/or the regions which are disposed at least partially on the support surface 9. This factual situation is illustrated in FIG. 1E.
(74) FIG. 5F shows a further exemplary embodiment of a flow chart for the method according to the invention which explains the removal of the sacrificial carrier 3, 4. For this purpose, method steps S.sub.6 and S.sub.7 are implemented after the completion of method step S.sub.5. In method step S.sub.6, all sacrificial carriers 3, 4 are removed. The removal of the sacrificial carriers 3, 4 can be implemented by undercutting.
(75) In method step S.sub.7, the further bond layer 16 arranged on the at least one removed sacrificial carrier 3, 4 is removed. These factual situations are shown in FIGS. 1J, 1K and 1L.
(76) FIG. 5G shows a further exemplary embodiment of a flow chart for the method according to the invention which explains the manufacture of the fastening elements 20. For this purpose, method steps S.sub.1.sub._.sub.1, S.sub.1.sub._.sub.2, S.sub.1.sub._.sub.3 and S.sub.1.sub._.sub.4 are implemented, preferably within method step S.sub.1. In method step S.sub.1.sub._.sub.1, an edge 15 of the carrier substrate 2 is removed. This method step is shown in FIG. 1F.
(77) Following this, method step S.sub.1.sub._.sub.2 is implemented. In method step S.sub.1.sub._.sub.2, the at least one sacrificial carrier 3, 4 exposed in method step S.sub.1.sub._.sub.1, together with the carrier substrate 2 which contains the bond layer 5 and the contact layer 6, is coated with a further bond layer 16 and with a further contact layer 17. The coating with the further bond layer 16 and with the further contact layer 17 is also a deposition process. These factual situations are explained in greater detail in FIG. 1G and FIG. 1H.
(78) Following this, method step S.sub.1.sub._.sub.3 is implemented. In method step S.sub.1.sub._.sub.3, the further bond layer 16 and the further contact layer 17 is removed with the exception of the region on the carrier substrate 2 on which no fastening elements 20 for stabilisation are to be embodied. Furthermore, this factual situation is explained in greater detail in FIG. 1I.
(79) Finally, following this, method step S.sub.1.sub._.sub.4 is implemented. In method step S.sub.1.sub._.sub.4, the further bond layer 16 and the further contact layer 17 is removed from the regions on the at least one sacrificial carrier 3, 4 on which no fastening elements 20 are to be embodied, with the exception of an edging 21 and at least one web 22 which surrounds all fastening elements 20 at a defined distance and connects them via at least one web 22. This factual situation also takes place in FIG. 1J but is not illustrated there, because FIG. 1J illustrates a simplified cross-section through the substrate-based circuit 1 along the axis A, as shown in FIG. 3A. The fastening elements 20 and also the edging 21 and the at least one web 22 are formed from the same material, namely on one side, from the further bond layer 16 and on the other side from the further contact layer 17 disposed above this.
(80) FIG. 5H shows a further exemplary embodiment of a flow chart for the method according to the invention which explains the cutting out of the substrate-based circuit 31. For this purpose, method step S.sub.8 is implemented, preferably after method step S.sub.7. In method step S.sub.8, the edging 21 is removed by means of a laser by cutting through the at least one web 22 at the transition to the corresponding fastening element 20. The substrate-based circuit 31 is accordingly detached from the edging 21 and from the webs 22. This factual situation is clearly evident in the transition from FIG. 3A to FIG. 3B.
(81) FIG. 5I shows a further exemplary embodiment of a flow chart for the method according to the invention which explains the manufacture of a capacitor on a substrate layer 1. For this purpose, method steps S.sub.9 and S.sub.10, which can be implemented, for example, following method step S.sub.5.sub._.sub.2 and S.sub.5.sub._.sub.4, are implemented. Within method step S.sub.9, at least one region of the bond layer 5 is coated with a contact layer 6 before the contact layer 6 is coated with the solder-stop layer 12 and/or the further bond layer 16 itself.
(82) After the solder-stop layer 12 and/or the further bond layer 16 has been applied, method step S.sub.10 is carried out. Within method step S.sub.10, at least the parts of the solder-stop layer 12 and/or the further bond layer 16 which are arranged above the region of the bond layer 5 are coated with the further contact layer 17, thereby forming a capacitor the level of which is adjusted via a thickness of the solder-stop layer 12 and/or of the further bond layer 16 and/or the size of the area of the region. The area of the region is defined by the overlapping parts of the first contact layer 6 and the further contact layer 17. In this context, the further contact layer 17 can be connected, for example, to the at least one fastening element 20, as illustrated in FIG. 2A. Accordingly, the contact layer 6 is preferably connected in an electrically conducting manner to the conductor line 7 or the at least one antenna element 8.
(83) Within the scope of the invention, all of the features described and/or illustrated can be combined arbitrarily with one another.
