Light-receiving device and method for producing the same

Abstract

A method produces a light-receiving device by growing a light-receiving layer having an undoped multi-quantum well structure; growing a cap layer on the light-receiving layer while the cap layer is doped with a p-type impurity during its growth; growing a mesa structure; growing a protective film on surfaces of the mesa structure; and annealing to form a p-n junction. The mesa structure is defined by a surrounding trench. Alternatively, a selective growth mask can be formed on the light-receiving layer whereafter the cap layer is grown on the light-receiving layer by use of the mask. In the alternative, the p-n junction is formed by diffusing p-type impurity from a p-type contact layer of the cap layer through a concentration adjusting layer thereof to the light-receiving layer.

Claims

1. A method for producing a light-receiving device, the method comprising the steps of: growing a light-receiving layer on a substrate, the light-receiving layer having an undoped multi-quantum well structure; growing on the light-receiving layer, a cap layer including a concentration adjusting layer formed on the light-receiving layer and a p-type contact layer formed on the concentration adjusting layer as a p-type semiconductor layer doped with a p-type impurity as the p-type semiconductor layer is grown, the concentration adjusting layer being undoped or being doped with a p-type or an n-type impurity at a lower concentration than that of the p-type contact layer; forming a mesa structure including the cap layer by etching the cap layer, the mesa structure being defined by a trench surrounding the mesa structure; after the step of forming the mesa structure, forming a protective film on an upper surface and a side surface of the mesa structure; and after the step of forming the protective film, annealing the substrate with the protective film covering the upper surface and the side surface of the mesa structure at a predetermined temperature to form a p-n junction in the light-receiving layer or at the boundary between the light-receiving layer and the cap layer, wherein, in the step of forming the mesa structure, the trench reaches the vicinity of an upper surface of the light-receiving layer, and in the step of annealing the substrate, the p-type impurity in the p-type semiconductor layer is diffused from the cap layer in the mesa structure to the light-receiving layer through the concentration adjusting layer.

2. The method according to claim 1, wherein, in the step of growing the cap layer, the p-type semiconductor layer is grown while gradually or stepwise increasing doping with the p-type impurity with the lapse of growth time from the beginning of growth.

3. The method according to claim 1, wherein the light-receiving layer and the cap layer are grown at a growth temperature of 425 C. to 575 C. by a metal-organic vapor phase epitaxy method using metal-organic compounds for a III group source material and a V group source material.

4. The method according to claim 1, wherein the light-receiving layer includes an undoped type-II multi-quantum well structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of a light-receiving device and a sensing apparatus according to a first embodiment.

(2) FIG. 2A is a partially enlarged view of a pixel of the light-receiving device illustrated in FIG. 1. FIG. 2B illustrates the in-depth distribution of impurity concentration in the light-receiving device illustrated in FIG. 1.

(3) FIG. 3A is an enlarged view of a pixel in a modified embodiment of the light-receiving device illustrated in FIG. 1. FIG. 3B illustrates the in-depth distribution of impurity concentration in the light-receiving device illustrated in FIG. 3A.

(4) FIGS. 4A to 4D illustrate a process for producing the light-receiving device illustrated in FIG. 1. FIG. 4A illustrates a state in which after an insulating film is formed on a stacked semiconductor layer, a resist mask is formed on the insulating film and subjected to dry etching.

(5) FIG. 4B illustrates a state during the dry etching. FIG. 4C illustrates a state in which after an insulating film is formed on the entire surface of a wafer including a mesa trench, a resist mask having an opening at an end portion of a chip is formed and subjected to dry etching. FIG. 4D illustrates a state in which the resist mask and the insulating film located at the end portion of the chip are removed.

(6) FIG. 5 illustrates the in-depth distribution of Zn obtained by a selective diffusion method in the related art, and, in particular, illustrates the pile-up of Zn at a hetero-interface.

(7) FIG. 6 illustrates a light-receiving device and a sensing apparatus according to a second embodiment.

(8) FIG. 7A is a partially enlarged view of a pixel of the light-receiving device illustrated in FIG. 6. FIG. 7B illustrates the in-depth distribution of impurity concentration in the light-receiving device illustrated in FIG. 6.

(9) FIG. 8A is a cross-sectional view of a light-receiving device and a sensing apparatus according to a third embodiment. FIG. 8B is a partially enlarged view of a pixel.

(10) FIGS. 9A and 9B are a cross-sectional view and a plan view, respectively, of a light-receiving device according to a fourth embodiment.

(11) FIGS. 10A to 10D illustrate a process for producing the light-receiving device illustrated in FIG. 9. FIG. 10A illustrates a stage at which a light-receiving layer is formed on a buffer layer. FIG. 10B illustrates a stage at which a selective growth mask is formed on the light-receiving layer. FIG. 10C illustrates a stage at which selective growth layers are grown while an impurity is selectively diffused. FIG. 10D illustrates a stage at which pixel electrodes are formed on the selective growth layers.

(12) FIG. 11 is a plan view of the opening pattern of the selective growth mask illustrated in FIG. 10B.

(13) FIG. 12A is a schematic diagram of p-type regions and p-n junctions, the p-type regions extending from selectively grown contact layers serving as diffusion sources. FIG. 12B is a partial enlarged view of edges of the p-n junctions illustrated in FIG. 12A.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(14) Findings of the present invention can be readily understood by considering the following detailed description with reference to the attached drawings illustrated. A light-receiving device, a method for producing the same, and a sensing apparatus according to embodiments of the present invention will be described with reference to the attached drawings. The same components are designated using the same reference numerals, when possible.

First Embodiment

(15) FIG. 1 illustrates a sensing apparatus 50 including a light-receiving device 10 and a read-out integrated circuit (ROIC) 70 connected to the light-receiving device 10. The light-receiving device 10 has a stacked semiconductor layer described below, (InP substrate 1/n-type InP buffer layer 2/light-receiving layer 3/cap layer 5). The light-receiving layer 3 includes an undoped multi-quantum well (MQW) structure in which well layers and barrier layers are alternately stacked. Especially, the light-receiving layer 3 includes an undoped type-II multi-quantum well (MQW) structure. The light-receiving layer 3 including the type-II multi-quantum well (MQW) structure is explained hereinafter.

(16) The cap layer 5 includes a p-type InGaAs contact layer 5a and an InGaAs concentration adjusting layer 5b adjacent to the p-type InGaAs contact layer 5a. A pixel electrode 11 is formed on the p-type InGaAs contact layer 5a and is in ohmic contact with the p-type InGaAs contact layer 5a. Zinc (Zn) doped in the p-type InGaAs contact layer 5a as a p-type impurity diffuses into the InGaAs concentration adjusting layer 5b. In the InGaAs concentration adjusting layer 5b, zinc (Zn) impurity is distributed so as to have a concentration gradient decreasing toward the light-receiving layer. The concentration adjusting layer 5b may be formed of the foregoing InGaAs layer, an InP layer, or a composite layer formed of (InGaAs layer/InP layer). The p-type contact layer Sa may be formed of the foregoing InGaAs layer, an InP layer, or a composite layer formed of (InGaAs layer/InP layer). The p-type contact layer 5a has a concentration of a p-type impurity, such as zinc (Zn), of 110.sup.18 cm.sup.3 or more so as to form an ohmic contact with the pixel electrode 11. Impurity concentrations in the p-type contact layer 5a and the concentration adjusting layer 5b will be described in detail below in connection with a p-n junction 15.

(17) The light-receiving layer 3 has a multi-quantum well (MQW) structure. Specifically, the light-receiving layer 3 has a type-II multi-quantum well (MQW) structure in which InGaAs and GaAsSb layers are alternately stacked. Each of the InGaAs layers has a thickness of 2 nm to 6 nm. Each of the GaAsSb layers has a thickness of 2 nm to 6 nm. The multi-quantum well structure has about 250 pairs to about 500 pairs. The light-receiving layer 3 has a thickness of 2 m to 5 m. The p-type contact layer Sa of the cap layers 5 has a thickness of 0.3 m to 3 m. The concentration adjusting layer 5b has a thickness of 0.05 m to 2 m. As illustrated in a second embodiment, the concentration adjusting layer 5b may be absent.

(18) Pixels P are mechanically and structurally separated by a trench K of a mesa structure. To protect an edge portion of the mesa structure, a protective film 25 is formed on a top surface and a side surface of the mesa structure. The protective film 25 is also formed in the trench K of the mesa structure. The trench K of the mesa structure, the p-type contact layer Sa, and a ground electrode 12 are located at the edge portion. The trench K of the mesa structure, the p-type contact layer 5a, and the ground electrode 12 are covered with the protective film 25. Each of the pixel electrodes 11 of the light-receiving device 10 is electrically connected to a corresponding read-out electrode 71 provided in the ROIC 70 with a bump (not illustrated). A ground electrode 12 is formed on the n-type buffer layer 2 and is in ohmic contact with the n-type buffer layer 2. Furthermore, the ground electrode 12 is electrically connected to a ground electrode 72 with a bump (not illustrated) via a wiring electrode 13 which is arranged on a side surface of the edge portion and which extends to the top surface of the p-type contact layer 5a. The bump is arranged so as to face the ground electrode 72 of the ROIC 70. The pixel electrode 11 is composed of AuZn. The ground electrode 12 is composed of AuGeNi. The pixel electrode 11 and the ground electrode 12 may be composed of PtTiAu. As described above, the p-type contact layer 5a has an impurity concentration of 110.sup.18 cm.sup.3 or more. The n-type buffer layer 2 may be doped with Si serving as an n-type impurity in an amount of 110.sup.18 cm.sup.3 or more. When the pixels are two-dimensionally arranged, the backside of the InP substrate 1 may be defined as an incident surface. To increase responsivity, an antireflection coating 27 composed of, for example, SiON, may be arranged on the backside of the InP substrate 1. A complimentary metal-oxide semiconductor (CMOS)-containing multiplexer is used as the ROIC 70.

(19) In the light-receiving device 10 according to this embodiment, a combination of the mesa structure and the impurity diffusion achieves the pixel separation and the pixel arrangement having a high fill factor. When the p-n junction is formed, the edge of the p-n junction is arranged in the light-receiving layer or at the upper boundary of the light-receiving layer (the upper surface of the light-receiving layer) without exposure to an atmosphere for a moment from the beginning of the production to the completion of a product. The edge of the p-n junction 15 is not exposed to the atmosphere from the beginning of the production to the completion of a product; hence, an impurity, such as oxygen, does not adhere to the edge of the p-n junction 15. No adhesion of oxygen or the like to the edge of the p-n junction 15 effectively serves to suppress dark current. Due to the position of the p-n junction, a depletion layer extends to the light-receiving layer 3 at a low operating voltage. The low operating voltage also contributes assuredly to suppress the dark current.

(20) The mesa structure of the light-receiving device 10 according to this embodiment will be described below. As illustrated in FIG. 1, the trench K reaches the vicinity of the upper surface of the light-receiving layer 3. Regarding the trench of the mesa structure described above, the expression the trench K reaches the vicinity of the upper surface of the light-receiving layer indicates that when the depth position of the boundary between the light-receiving layer 3 and an upper layer (the concentration adjusting layer 5b in each of the cap layers 5 in FIG. 1) on the light-receiving layer 3 is defined as a reference depth position, the bottom of the trench is located at a position in a depth range of (a position in the upper layer away from the reference depth position by 1/10 of the thickness of the light-receiving layer 3) to (a position in the light-receiving layer 3 away from the reference depth position by 2/10 of the thickness of the light-receiving layer 3). Thus, the bottom of the trench K is located at a position in the concentration adjusting layer 5b of a corresponding one of the cap layers 5 away from the reference depth position by 10% or less of the thickness of the light-receiving layer 3. Alternatively, when the bottom of the trench K is located in the light-receiving layer 3, the depth position of the bottom of the trench K is limited to the inside of an upper portion of the light-receiving layer 3, the upper portion having a thickness of 20% or less of the thickness of the light-receiving layer 3. Accordingly, a near-infrared light-receiving device which includes the pixels P separated mechanically and structurally is obtained. In addition, in the near-infrared light-receiving device, excellent performances such as low dark current and high signal-to-noise ratio can be realized. With respect to pixel separation in the related art, the trench is arranged so as to extend substantially completely through the light-receiving layer. As a result, a side wall of the light-receiving layer is exposed to an atmosphere at the trench. Therefore, in the light-receiving device with the trench extending completely through the light-receiving layer, dark current is increased. In the embodiment, the trench K is formed so as to have the bottom which is located at a position in the upper layer away from the reference depth position by 10% or less of the thickness of the light-receiving layer or which are each located at a position in the upper portion of the light-receiving layer 3 away from the reference depth position by 20% or less of the thickness of the light-receiving layer 3. Therefore, the pixels P are separated without exposure of the p-n junction 15 to the outside air. The mesa structure is formed by forming the trench K surrounding the mesa structure, and then the mesa structure is covered with the protective film 25. An impurity (Zn) is diffused to form the final p-n junction 15. Specifically, the trench K is formed within the depth range described above. In the embodiment, a p-type impurity (Zn) doped in the p-type contact layers 5a is diffused toward the light-receiving layer 3. The p-type contact layers 5a is used as a diffusion source.

(21) A method for forming the p-n junction 15 by impurity diffusion from the p-type contact layer 5a will be described below. In a planar-type light-receiving device using the selective diffusion of an impurity in the related art, pixels are separated by regions in which the impurity does not diffuse. In the selective diffusion, however, the impurity is diffused from opening portions not only in the depth direction but also in the lateral direction. This is a major obstacle to reducing the pixel pitch to increase the fill factor. In contrast, according to this embodiment, pixels are mechanically and structurally separated by the mesa structure, thereby resulting in a narrow pitch. According to the first embodiment, after forming the protective film 25 on the side surface and top surface of the mesa structure, the p-type impurity, such as Zn, in the p-type contact layers 5a is diffused by annealing to the upper surface of the light-receiving layer 3 or inside the light-receiving layer 3. Thus, the p-n junction 15 is accurately located at predetermined positions on the upper surface of the light-receiving layer 3 or in the upper portion of the light-receiving layer 3.

(22) FIG. 2A is a partially enlarged cross-sectional view of the pixel P illustrated in FIG. 1 and illustrates the distribution of Zn serving as a p-type impurity in a pixel P mechanically and structurally separated by the trench K of the mesa structure. FIG. 2B illustrates the in-depth distribution of the concentration of the impurity. Zinc (Zn) serving as a p-type impurity is diffused from the p-type contact layer 5a toward the light-receiving layer 3 by a driving force resulting from a concentration gradient, thereby forming a p-type region 6. An end of the p-type region 6 is located at a position which is inside the light-receiving layer 3 and in the vicinity of the upper surface of the light-receiving layer 3, thereby resulting in the formation of the p-n junction 15.

(23) Referring to FIG. 2B, immediately after the epitaxial growth of the p-type contact layer 5a, the impurity is uniformly distributed (indicated by a dotted line) with high concentration in the p-type contact layer 5a. In the annealing process, the impurity is diffused toward the light-receiving layer 3. As a result, the impurity concentration at a corner portion of a high-concentration region in the p-type contact layer 5a is gradually reduced toward the light-receiving layer 3. In the concentration adjusting layer 5b disposed between the p-type contact layer 5a and the light-receiving layer 3, a distribution in Zn concentration has a large slope of (concentration/in-depth distance) in the depth direction. As described above, the concentration of the p-type impurity, such as Zn, may be set at a low concentration of 510.sup.16 cm.sup.3 or less at the boundary between the light-receiving layer 3 and the concentration adjusting layer 5b because the concentration adjusting layer 5b is disposed between the p-type contact layer 5a and the light-receiving layer 3. This inhibits the degradation of the crystallinity of the type-II multi-quantum well structure constituting the light-receiving layer 3.

(24) The p-n junction 15 is formed at a position (crossing position) at which the concentration of the p-type impurity at the end of the p-type region 6 is equal to the background concentration of an n-type impurity in the light-receiving layer 3. When the position of the p-n junction 15 is defined as a reference position, the p-type region 6 extending from the reference position to the p-type contact layer 5a has a high p-type impurity concentration. The light-receiving layer 3 is composed of an undoped semiconductor that has an n-type conductivity and a background concentration of the n-type impurity. Therefore, the concentration of the n-type impurity in a portion of the light-receiving layer 3 extending from the reference position toward the substrate 1 is equal to the background concentration. The background concentration of the n-type impurity in the portion of the light-receiving layer 3 extending from the reference position toward the substrate 1 is, for example, about 510.sup.15 cm.sup.3 and is substantially constant. The p-type impurity in the p-type contact layer 5a, which serves as a diffusion source, is doped during growing the contact layer 5a. The p-type contact layer 5a serves as a diffusion source and the p-type impurity in the p-type contact layer 5a is diffused toward the light-receiving layer 3. In the method, steps of vacuum-sealing an epitaxial wafer in a silica tube or the like and selectively diffusing an impurity from the outside through a gas phase are not required. It is thus possible to improve the productivity by increasing the diameter of the semiconductor substrate.

(25) When the light-receiving device 10 receives light, it is necessary to apply a predetermined operating voltage (the absolute value of a reverse-bias voltage) to the p-n junction 15 to extend a depletion layer into the light-receiving layer 3. As illustrated in FIG. 2, the p-n junction 15 is formed in the light-receiving layer 3 or at the boundary between the light-receiving layer 3 and the concentration adjusting layer 5b in the cap layer 5. In this case, even if a low reverse-bias voltage is applied to the light-receiving device 10, the depletion layer extends into the light-receiving layer 3.

(26) As described above, in general, dark current is proportional to an operating voltage (the absolute value of a reverse-bias voltage). Thus, a lower operating voltage results in further suppression of the dark current. As illustrated in FIG. 2B, the portion of the light-receiving layer 3 extending from the reference position of the p-n junction 15 toward the substrate 1 has a low impurity concentration that corresponds to the n-type background concentration. On the other hand, a portion of the light-receiving layer 3 extending from the reference position toward the concentration adjusting layer 5b contains a p-type impurity with a high concentration. Thus, by applying a low operating voltage, the depletion layer is extended largely into the light-receiving layer 3. The operating voltage is applied between the pixel electrode 11 and the ground electrode 12. In this embodiment, the depletion layer is sufficiently extended in the light-receiving layer even at a low operating voltage, so that sufficient responsivity is provided. As described above, the reduction in operating voltage results in the suppression of the dark current.

Modified Embodiment

(27) FIGS. 3A and 3B illustrate a modified embodiment of the light-receiving device 10 illustrated in FIG. 1. FIG. 3A is a partially enlarged cross-sectional view of the pixel P. FIG. 3B illustrates the in-depth distribution of the concentration of Zn serving as a p-type impurity. The difference between the modified embodiment and the light-receiving device 10 illustrated in FIGS. 1 and 2 is that a trench K is deepened in such a manner that the bottom of the trench K is located at a position 3b in the light-receiving layer 3. When the trench K is deepened to the light-receiving layer 3, the position of the bottom is located at a position in the light-receiving layer 3 away from the boundary between the concentration adjusting layer 5b and the light-receiving layer 3 by 2/10 or less of the thickness of the light-receiving layer. As illustrated in FIG. 3A, the deep mesa trench K increases a region where the depth position of the p-n junction 15 lies at a shallower depth than the depth position of the bottom of the mesa trench. In this case, the pixels P can be more surely separated from adjacent pixels.

(28) A method for producing the light-receiving device 10 will be described below. As illustrated in FIG. 4A, the n-type InP buffer layer 2, the light-receiving layer 3 having a type-II multi-quantum well structure, the concentration adjusting layer 5b including an InP layer and/or an InGaAs layer, and the p-type InGaAs contact layers 5a are grown, in that order, on the InP substrate 1 by an epitaxial growth method to form a stacked semiconductor layer. The light-receiving layer 3 includes a type-II multi-quantum well structure. The concentration adjusting layer 5b includes an InP layer and/or an InGaAs layer. As the epitaxial growth method, for example, a metal-organic vapor phase epitaxy (MOVPE) method using metal-organic compounds for a III group source material and a V group source material may be employed. For example, as a V group source material, tertiarybutylarsine (TBAs) and tertiarybutylphosphine (TBP) are used. TBAs and TBP are source materials of As and P, respectively. In the MOVPE method, low-temperature growth may be performed because the metal-organic sources are decomposed at relatively low temperatures. It is thus possible to inhibit the decomposition and so forth of the type-II multi-quantum well structure during growing the stacked semiconductor layer. Hence, the foregoing semiconductor layers are grown by the MOVPE method to form a light-receiving layer having satisfactory crystallinity. In the MOVPE method, as a p-type-impurity source or the like, a metal-organic source may also be used. For example, diethylzinc (DEZn), which is a metal-organic material, may be used as a Zn source. The growth temperature may be set at a temperature between 425 C. and 575 C. At the growth temperature, the crystallinity of the type-II MQW structure composed of, for example, InGaAs and GaAsSb is not degraded. As the InP substrate 1, an Fe-doped semi-insulating InP substrate is used because of a low optical absorption of the Fe-doped semi-insulating InP in the near-infrared region. Alternatively, a conductive InP substrate may be used, depending on a production process. The impurity concentration in the p-type contact layer 5a is 110.sup.18 cm.sup.3 or more. The n-type buffer layer 2 is doped with Si at a concentration of 110.sup.18 cm.sup.3 or more. The concentration adjusting layer 5b may be lightly doped with an n-type impurity or a p-type impurity in a concentration of 110.sup.16 cm.sup.3 or less. Alternatively, the concentration adjusting layer 5b may not be doped.

(29) A trench of a mesa structure is formed to separate the pixels P in a pixel region. To form the trench of the mesa structure, an insulating film 21 is formed on the stacked semiconductor layer. The insulating film 21 is formed of, for example, SiO.sub.2 or SiN. A mask R1 composed of a resist is formed on the insulating film 21. Arrows in FIGS. 4A and 4B indicate etching positions. The insulating film 21 is etched with buffered hydrofluoric acid using the mask R1 to form an etching mask. As illustrated in FIG. 4B, the stacked semiconductor layer is etched by dry etching using the patterned insulating film 21 as the etching mask. As a result of etching the stacked semiconductor layer, the trench K of the mesa structure is formed in the pixel region. In this dry etching, it is possible to determine the time at which the dry etching is stopped when the bottom of the trench K reaches the upper surface of the light-receiving layer by monitoring antimony in the GaAsSb layer included in the type-II MQW structure. Then the insulating film 21 is removed. As described above, when the depth position of the boundary between the light-receiving layer and the upper layer (the concentration adjusting layer 5b in this embodiment) on the light-receiving layer is defined as the reference depth position, the depth of the trench K of the mesa structure is in the range of (a position in the upper layer away from the reference depth position by 1/10 of the thickness of the light-receiving layer) to (a position in the light-receiving layer away from the reference depth position by 2/10 of the thickness of the light-receiving layer). Then a damaged layer is removed by wet etching.

(30) Next, a groove G for the formation of the ground electrode 12 is formed at the edge portion. In this embodiment, the depth of the ground electrode groove G is significantly different from the depth of the trench K for pixel separation. To form the groove G and the trench K, the stacked semiconductor layer is thus etched in two steps. As illustrated in FIG. 4C, an insulating film 22 is formed on the entire surface. The insulating film 22 is formed of, for example, SiO.sub.2 or SiN. In the trench K for the pixel separation, side surfaces of the mesa structures are also surely covered and protected. This protection prevents damage to the side surfaces of the mesa structures due to the dry etching, thereby achieving low dark current. A resist mask R2 is formed so as to have an opening at an edge of the light-receiving device 10. As illustrated in FIG. 4D, the ground electrode groove G for the formation of the ground electrode 12 is formed by dry etching. Thereby, the ground electrode groove G is formed at the edge of the light-receiving device 10. In FIG. 4D, the resist mask R2 is omitted.

(31) In FIG. 1 and so forth, the bottom and the inner walls of the trench K and top surfaces of the stacked semiconductor layer are protected by the protective film 25. That is, the side surfaces and upper surfaces of the mesa structures are protected by the protective film 25. Regarding the protective film 25, the insulating film 22 illustrated in FIG. 4D is used, as-is, as the protective film 25.

(32) Next, an annealing process is performed by heating to 400 C. to 550 C. with the bottom and the inner walls of the trench K and top surfaces of the stacked semiconductor layer covered with the protective film 25. Accordingly, the annealing process is performed with the side surfaces and the upper surfaces of the mesa structures covered with the protective film 25. In the annealing process, the p-type impurity (Zn) doped in the p-type contact layer 5a is diffused toward the light-receiving layer 3. In the embodiment, after the mesa structure is covered with the protective film, the p-type impurity is diffused to form the p-n junction 15 at the upper surface of the light-receiving layer 3 or in the light-receiving layer 3. The p-n junction 15 is not exposed to an atmosphere in a growth chamber during the annealing process (in which p-type impurity is diffused). Hence, an impurity, such as oxygen, is not attached to the edge of the p-n junction 15, leading to a reduction in leakage current. Therefore, an increase in the dark current of the light-receiving device 10 can be suppressed.

(33) Next, a mask composed of a resist is formed in order to form the pixel electrode 11. The protective film 25 is etched with the resist mask to form an opening for forming the electrode on the mesa structure. A p-side electrode composed of, for example, AuZn is formed as the pixel electrode 11 by, for example, a lift-off process on the upper surface of the mesa structure. An n-side electrode to be formed into the ground electrode 12 common to the pixels is formed. The n-type electrode may be composed of, for example, AuGeNi. The wiring electrode 13 extending from the ground electrode 12 to the protective film 25 on the mesa structure through a surface of the n-type InP buffer layer 2 and a wall of the stacked semiconductor layer is formed. The backside of the InP substrate 1 is polished to a thickness of about 100 m. The antireflection (AR) coating 27 as illustrated in FIG. 1 is formed on the backside of the InP substrate 1.

(34) In the embodiment, as a method for forming an impurity region, such as the p-type region 6, the impurity doped in the impurity layer, such as the p-type contact layer 5a is diffused. In addition, the p-n junction 15 is formed by the diffusion of the impurity (Zn) from the impurity layer, such as the p-type contact layer 5a. Here, the impurity (Zn) is doped in the impurity layer during growing the impurity layer. It is thus possible to obtain an impurity concentration distribution different from the case where an impurity is introduced from the outside gas phase. FIG. 5 illustrates the in-depth distribution of Zn obtained by a selective diffusion method in the related art. The in-depth distribution of Zn shown in FIG. 5 is obtained by the selective diffusion method described below. At first, a stacked semiconductor layer including an InP buffer layer, a light-receiving layer, an InGaAs layer, and an InP window layer is formed on an InP substrate. The InP buffer layer, the light-receiving layer, the InGaAs layer, and the InP window layer are grown in this order on the InP substrate by, for example, MOVPE. The InP window layer is a top layer of the stacked semiconductor layer. The light-receiving layer includes a type-II multi-quantum well structure. A selective diffusion mask having openings above the InP window layer is formed to provide an intermediate product (epitaxial wafer). The intermediate product (epitaxial wafer) is vacuum-sealed in a silica tube together with a solid zinc source. The zinc source sublimes by heat treatment. The gas-phase Zn that has sublimed diffuses in desired regions (pixel regions) in the epitaxial wafer from the gas phase through the openings of the selective diffusion mask to form Zn regions. As a result, the in-depth concentration distribution as illustrated in FIG. 5 is obtained when zinc (Zn) is selectively diffused from the outside gas phase through the openings of the selective diffusion mask on the epitaxial wafer.

(35) When a large amount of the diffusion source is present in the gas phase, compared with that in the epitaxial wafer or the light-receiving layer, a small spike-like Zn peak is observed at the heterointerface between InGaAs and the (InGaAs/GaAsSb) type-II multi-quantum well structure, as described as Pile-up of Zn in FIG. 5. This is referred to as the pile-up of Zn.

(36) In contrast, in the embodiment, the method is employed in which the impurity region, such as p-type region 6, is formed using the diffusion from the p-type contact layer 5a containing the p-type impurity (Zn) serving as a diffusion source. In the method according to the embodiment, the pile-up of Zn as illustrated in FIG. 5 does not occur at the heterointerfaces between the concentration adjusting layers 5b and the light-receiving layer 3. Thus, the absence of the pile-up of an impurity (Zn) indicates that the diffusion source of the impurity is the p-type contact layers 5a.

Second Embodiment

(37) FIG. 6 illustrates the sensing apparatus 50 in which the light-receiving device 10 according to a second embodiment is connected to the read-out integrated circuit (ROIC) 70. The difference from the light-receiving device 10 according to the first embodiment is that the cap layer 5 is formed of the p-type contact layer 5a alone without the concentration adjusting layer in this embodiment. The bottom of the trench K of the mesa structure is located at a position away from the upper surface of the light-receiving layer 3 by 20% or less of the thickness of the light-receiving layer 3.

(38) FIG. 7A is a partially enlarged view of a pixel P illustrated in FIG. 6. FIG. 7A also illustrates a cross-sectional view of the distribution of Zn serving as a p-type impurity in the pixel P. In the embodiment, the pixels P are mechanically and structurally separated from each other by the trench K of the mesa structure. FIG. 7B illustrates the in-depth distribution of Zn concentration. In the pixel P, zinc (Zn) is directly diffused from the p-type contact layer 5a into the light-receiving layer 3 without a concentration adjusting layer by a driving force resulting from a concentration gradient. The p-type region 6 extends to the light-receiving layer 3. The p-n junction 15 is formed at the end of the p-type region 6. The concentration of the p-type impurity is 510.sup.16 cm.sup.3 or less at the boundary between the light-receiving layer 3 and the p-type contact layer 5a serving as an upper layer on the light-receiving layer 3, thereby maintaining satisfactory crystallinity of the type-II InGaAs/GaAsSb multi-quantum well structure. However, the p-type contact layer 5a is a region with which the pixel electrode 11 forms an ohmic contact. Thus, at least a surface of the p-type contact layer 5a needs to have a p-type impurity concentration of 110.sup.18 cm.sup.3 or more. To achieve both the two points concerning the impurity concentration, when the p-type contact layer 5a is epitaxially grown, the doping amount of the p-type impurity may be gradually or stepwise increased from an undoped state or a lightly doped state with the lapse of growth time from the beginning of the growth. For example, as illustrated in FIG. 7B, a step-like concentration distribution indicated by a dotted line may be obtained immediately after the growth of the p-type contact layer Sa by the doping method. In the concentration distribution immediately after the growth, the impurity concentration is 510.sup.16 cm.sup.3 or less at the boundary between the light-receiving layer 3 and the p-type contact layer 5a.

(39) Hereafter, the p-type impurity exhibiting the step-like concentration distribution is diffused toward the light-receiving layer 3 by annealing. The shape of the step-like concentration distribution immediately after the growth is changed from a rectangular shape to a rounded shape by the diffusion. However, the impurity concentration is not more than 510.sup.16 cm.sup.3 at the boundary between the light-receiving layer 3 and the p-type contact layer 5a. Thus, there is no degradation in the crystallinity of the type-II multi-quantum well structure due to a high impurity concentration.

Third Embodiment

(40) FIGS. 8A and 8B illustrate the light-receiving device 10 according to a third embodiment and the sensing apparatus 50 including the light-receiving device 10. FIG. 8A is a cross-sectional view of the sensing apparatus. FIG. 8B is a partially enlarged view of a pixel P. Structures of the light-receiving device 10 according to this embodiment and the sensing apparatus 50 are different from the light-receiving device 10 according to the first embodiment and the sensing apparatus 50 as illustrated in FIG. 1 and so forth in the following points:

(41) (1) walls of the trench K of the mesa structure are inclined. This mesa shape may be obtained by forming the mesa structure by wet etching;

(42) (2) the bottom of the trench K of the mesa structure is located in the concentration adjusting layer 5b of the cap layer 5. The bottom of the trench K is located at a position in the concentration adjusting layer 5b away from the upper surface of the light-receiving layer 3 by 10% or less of the thickness of the light-receiving layer 3; and
(3) the p-n junction 15 is formed at the boundary between the light-receiving layer 3 and the concentration adjusting layer 5b.

(43) The light-receiving device 10 in this embodiment also provides the same advantageous effects as the foregoing first embodiment. The same production method may also be employed, except that the mesa structure is etched by wet etching.

(44) The formation of the trench K and the groove G by wet etching does not substantially cause damage to the crystal. Thus, the removal of a damaged layer by wet etching may not be performed or may be performed.

Fourth Embodiment

(45) FIGS. 9A and 9B are a cross-sectional view and a plan view, respectively, of a light-receiving device according to a fourth embodiment. A plurality of pixels P are provided on the InP substrate 1. To detect optical signals independently one another, the plural pixels P are separately arranged. Referring to FIGS. 9A and 9B, the light-receiving device 10 has a stacked semiconductor layer described below, (InP substrate 1/buffer layer 2/type-II MQW light-receiving layer 3/cap layer 5).

(46) The n-type buffer layer 2 may be composed of InP, InAlAs, or InGaAs. Light is incident on the backside of the InP substrate 1. To increase the amount of light received, the antireflection coating 27 composed of SiON or a multilayer film is disposed on the backside of the InP substrate 1.

(47) The InP substrate 1 is composed of an Fe-doped semi-insulating InP. The ground electrode 12 is arranged on the n.sup.+-type buffer layer 2. The undoped type-II MQW light-receiving layer 3 is grown without intentionally doping any impurities. The type-II MQW light-receiving layer 3 contains an n-type impurity, such as Si, in a concentration of background of 110.sup.16 cm.sup.3 or less. The cap layer 5 may be composed of InGaAs or InP. The cap layers 5 are selectively grown within openings 25h of the selective growth mask 25. Each of the cap layers 5 includes the p-type contact layer 5a and the concentration adjusting layer 5b. The p-type contact layer 5a in the cap layer 5 is doped with a p-type impurity (for example, Zn). The p-side electrode 11 serving as the pixel electrode is arranged on the p-type contact layer 5a. The p-side electrode 11 is composed of, for example, AuZn. The n-side electrode 12 which is composed of AuGeNi and which serves as the ground electrode is arranged on the n.sup.+-type buffer layer 2.

(48) According to the plan view of FIG. 9B, the pixels P are arranged in the respective openings 25h of the selective growth mask 25 in plan. Regarding the arrangement of the pixels P, for example, the pixel pitch is 30 m. The length of a side of each square opening 25h is 20 m to 25 m. The pixel P is a unit of the light-receiving element. As illustrated in FIG. 9B, the pixels P are two-dimensionally arrayed. Thus, for example, imaging may be performed. While the openings 25h have a rectangular or square shape in plan view in the foregoing embodiment, they may have a circular shape or the like.

(49) In this embodiment, the cap layers 5 are selectively grown within the openings 25h of the selective growth mask 25. The mechanical skeleton of the pixels P is formed with the cap layers 5. The selective growth mask 25 is formed so as to be in contact with the light-receiving layer 3. Then the cap layers 5 (5b and 5a) are selectively grown on the light-receiving layer 3 through the openings 25h of the selective growth mask 25 to have a substantially square shape in plan view and thus a post-shape in side view. A semiconductor layer is not grown on the selective growth mask 25. The selective growth mask 25 is composed of, for example, SiN or SiO.sub.2. Thus, the cap layers 5 (5b and 5a) are selectively grown in the respective openings 25h. A production method according to this embodiment does not include a step of forming a mesa structure or a step of performing etching a mesa. In the light-receiving device according to this embodiment, gaps between the cap layers 5 correspond to a mesa trench. The skeleton of the pixels P is defined by the cap layers 5 (5b and 5a) confined to the openings 25h.

(50) The formation of a p-n junction according to this embodiment will be described below. The pixel P includes the p-n junction or pi junction to extend a depletion layer to the light-receiving layer 3. Furthermore, the p-n junction is used for separating the pixels P from each other. In this embodiment, when the cap layer 5 (5b and 5a) is epitaxially grown, zinc (Zn) is added as a p-type dopant. The growth temperature is 450 C. or higher. Zn is thermally diffused toward the light-receiving layer 3 during the growth of the cap layer 5. The light-receiving layer 3 contains a low concentration of the n-type impurity as described above. Thus, Zn is diffused from the bottom of the cap layer 5 toward the light-receiving layer 3 while the p-type region 6 is being formed. In this way, the p-n junction 15 may be formed at a position near the upper surface of the light-receiving layer 3 or the boundary between the light-receiving layer 3 and the cap layer 5 (the concentration adjusting layer 5b).

(51) When the light-receiving device is operated, a reverse-bias voltage is applied between the n-side electrode 12 and the p-side electrode 11 to generate an electric field at the p-n junction 15. At this time, in the light-receiving device according to this embodiment, a depletion layer is formed so as to extend from the p-n junction 15 toward a low-impurity-concentration region, i.e., a region containing a low concentration of the n-type impurity. In other words, the depletion layer extends toward the lower surface of the light-receiving layer 3. When light is incident on the backside of the InP substrate 1, light is absorbed in the depletion layer. At this time, electron-hole pairs are efficiently formed in the depletion layer. Among the resulting electron-hole pairs, electrons move to the n-side electrode 12, and the holes move to the p-side electrode 11, thereby accumulating charges in proportion to the amount of light received. Thus, the optical signal is efficiently converted into an electrical signal. The light-receiving device supplies the electrical signal. Providing the electrical signal in response to the intensity of light received for each pixel P results in the intensity distribution of light received, thereby enabling imaging or the like. The separation of the p-n junctions 15 from adjacent pixels P will be described in detail in the section of a production method. In the description, the suppression of dark current will also be described.

(52) FIGS. 10A to 10D schematically illustrate a method for producing the light-receiving device 10 illustrated in FIGS. 9A and 9B. As illustrated in FIG. 10A, the n.sup.+-type buffer layer 2 and the undoped light-receiving layer 3 having a type-II MQW structure are grown by an epitaxial growth method on the Fe-doped semi-insulating InP substrate 1. The n.sup.+-type buffer layer 2 is composed of, for example, InP, InAlAs, or InGaAs. For the epitaxial growth, for example, a metal-organic vapor phase epitaxy method using only metal-organic sources may be employed with metal-organic compounds for a group III source and a group V source. As Ga (gallium), In (indium), As (arsenic), P (phosphorus), and Sb (antimony) sources, triethylgallium (TEGa), trimethylindium (TMIn), tertiarybutylarsine (TBAs), tertiarybutylphosphine (TBP), and trimethylantimony (TMSb) are used, respectively. As the Ga source, trimethylgallium (TMGa) may also be used. As the In source, triethylindium (TEIn) may be used. As the As source, trimethylarsine (TMAs) may also be used. As the Sb source, triethylantimony (TESb) may also be used. As an n-type dopant, tetraethylsilane (TeESi) may be used. As a p-type dopant, diethylzinc (DEZn) may be used. In the metal-organic vapor phase epitaxy method using only metal-organic sources, a size of a metal-organic vapor molecule in the source is large, and the metal-organic vapor molecule is decomposed at a low temperature to grow a semiconductor layer. Thus, in the metal-organic vapor phase epitaxy method using only metal-organic sources, a semiconductor layer may be grown even at a relatively low temperature. The number of InGaAsGaAsSb pairs in the MQW structure is in the range of about 50 to 500.

(53) Next, the selective growth mask 25 is formed on the light-receiving layer 3. The selective growth mask 25 is formed of a dielectric film composed of, for example, SiN, SiON, or SiO.sub.2. FIG. 11 illustrates the pattern of the selective growth mask 25. As described above, the length of a side of each square opening 25h is 20 m to 25 m. Each of the longitudinal and transverse pitches of the openings 25h is about 30 m. The light-receiving layer 3 is exposed through the openings 25h of the selective growth mask 25. Comparing FIG. 11 and FIG. 9B reveals that the openings 25h correspond to central regions of the pixels P in plan. FIG. 10B illustrates a state in which the selective growth mask 25 is formed. Then the cap layers 5 each including the p-type contact layer 5a and the concentration adjusting layer 5b are selectively grown on the light-receiving layer 3 through the openings 25h using the selective growth mask 25. No growth occurs on a region covered with the selective growth mask 25. When the p-type contact layer 5a in the cap layer 5 is formed, for example, diethylzinc (DEZn), which is an organometallic compound, may be used as a dopant source of a p-type impurity. The cap layer 5 including the p-type contact layer 5a and the concentration adjusting layer 5b may be composed of, for example, InGaAs, InP, or a composite layer of InGaAs and InP. The p-type contact layers 5a and the concentration adjusting layers 5b may be composed of the same material or different materials. However, the p-type contact layer Sa is doped with the p-type impurity in a high concentration. On the other hand, the concentration adjusting layer 5b is doped with the n-type impurity or the p-type impurity in a low concentration. Alternatively, the concentration adjusting layer 5b may be not doped (undoped). The presence of the concentration adjusting layers 5b enables the adjustment of the concentration of the p-type impurity that is diffused from the p-type contact layer 5a toward the light-receiving layer 3.

(54) The concentration adjusting layers 5b are selectively grown thorough the selective growth mask 25 on the light-receiving layer 3 exposed at the openings 25h. At this time, nothing is grown on a region of the selective mask other than the openings. The growth temperature of the concentration adjusting layers Sb and the contact layers 5a is 450 C. or higher and 550 C. or lower. At the growth temperature, the crystallinity of the type-II MQW structure is not degraded. Furthermore, the satisfactory crystallinity of the selective growth layers, such as the concentration adjusting layers 5b, is maintained. Moreover, at the growth temperature, DEZn is decomposed into Zn serving as a p-type impurity. It is thus possible to dope the contact layers 5a with the impurity, Zn, in a high concentration during the growth of the contact layers Sa. In addition, the growth temperature is sufficient to allow the impurity, Zn, with which the contact layers 5a are doped to diffuse from the bottoms of the contact layers 5a into the light-receiving layer 3 while the concentration adjusting layers 5b are changed to a p-type region.

(55) At the foregoing growth temperature, the Zn concentration at a position near the upper surface of the light-receiving layer 3 can be adjusted to about 510.sup.15 cm.sup.3, which is the background concentration of the n-type impurity in the light-receiving layer 3, by adjusting the thickness of the concentration adjusting layers 5b. Thereby, the p-n junction 15 is arranged at a desired position in the light-receiving layer 3. FIG. 10C illustrates a state in which the p-n junction 15 is formed in the light-receiving layer 3. Note that an edge M of the p-n junction is located on the surface of the light-receiving layer 3. The p-type impurity is diffused from the contact layer 5a through the concentration adjusting layer 5b in the thickness direction (depth direction or vertical direction). The p-type impurity is also diffused in the transverse direction (direction along a layer surface). As a result, each of the p-type regions 6 is slightly larger than a corresponding one of the openings 25h in plan.

(56) The edge M of the p-n junction 15 is located on the surface of the light-receiving layer 3. Here, the edge M of the p-n junction 15 is covered with the region of the selective growth mask 25 other than the opening, i.e., the dielectric film. Thus, an impurity, such as oxygen, in the atmosphere is not attached to the edge M of the p-n junction. In FIG. 10C, the range of a pixel P is demarcated by a thick broken line. The range of each p-type region 6 in plan corresponds to a corresponding one of the pixels P. Then the p-side electrode 11 is formed on the p.sup.+-type contact layer Sa. The ground electrode (not illustrated) is formed on the n.sup.+-type buffer layer 2. This leads to the completion of the light-receiving device 10 illustrated in FIG. 9A. The selective growth mask 25 is left as is in the product because it functions as a passivation film.

(57) Next, dark current of the light-receiving device produced in the production method according to this embodiment will be described. When the edge M of the p-n junction 15 is exposed to the atmosphere, oxygen and so forth in the atmosphere are attached to cause an increase in dark current. It is thus necessary to prevent the edge M of the p-n junction 15 from being exposed to the atmosphere or an atmosphere in a growth chamber even during the production. In this embodiment, as illustrated in FIG. 10C, Zn is diffused from the p.sup.+-type contact layer 5a to the light-receiving layer 3 through the concentration adjusting layer 5b. As illustrated in FIG. 12B, the edge M appears on the surface of the light-receiving layer 3 at the stage in which the p-n junction 15 is formed in the light-receiving layer 3. At this time, the edge M of the p-n junction 15 has already been covered with the dielectric film or the region of the selective growth mask 25 other than the opening. The selective growth mask 25 is left as a passivation film in the light-receiving device, so that the edge M of the p-n junction 15 is not exposed to the atmosphere or the like hereafter. As a result, the edge M of the p-n junction 15 is not exposed to the atmosphere or the atmosphere in the growth chamber, thereby providing the light-receiving device having low-dark-current characteristics.

(58) Regarding the independence of the pixels P, the skeleton of the pixels P is formed with the discrete cap layers 5 as described above. Furthermore, the p-n junctions 15 are separated from the p-n junctions 15 of adjacent pixels P, so that adjacent pixels P are surely and electrically separated from each other. As illustrated in FIG. 12B, the diffusion of the p-type impurity to the transverse direction may be substantially negligible, compared with diffusion in the vertical direction (thickness direction or depth direction). Thus, when a predetermined level of the pitch of the cap layers 5 or the pitch of the openings 25h is ensured, adjacent pixels P are surely and electrically separated from each other.

(59) The crystallinity of the light-receiving layer of the light-receiving device produced by the production method according to this embodiment will be described below. When the light-receiving layer has a type-II MQW structure, the MQW structure is not so stable, compared with a bulk crystal. For example, when the type-II MQW structure is processed at a temperature equal to or higher than a predetermined temperature or the type-II MQW structure is heavily doped at a high impurity concentration, the MQW structure may be changed. Alternatively, the layer structure of the MQW structure may be decomposed. With respect to the temperature, the temperature at which the cap layers 5a and 5b are grown may be set to a relatively low temperature of, for example, 600 C. or lower and even 550 C. or lower. For example, by using the metal-organic vapor phase epitaxy method using only metal-organic sources, a semiconductor layer may be grown even at a relatively low temperature. With respect to the impurity concentration, the thickness of the undoped or lightly-doped concentration adjusting layer 5b is adjusted in such a manner that an excess of the p-type impurity is not diffused to the light-receiving layer 3 during the growth of the cap layer 5, in particular, the p-type contact layers 5a. In other words, the undoped or lightly-doped concentration adjusting layer 5b is used as a layer configured to adjust the diffusion concentration distribution of the p-type impurity. In this case, the concentration of Zn in each concentration adjusting layer 5b decreases monotonically from the side of a corresponding one of the contact layers 5a (diffusion source) toward the light-receiving layer 3. Note that the pile-up of Zn at the heterointerface does not occur.

(60) With respect to the type-II MQW structure, (InGaAs/GaAsSb), (GaSb/InAs), and so forth may be used. A (InGaAs/GaAsSb) type-II MQW structure is formed on an InP substrate. A (GaSb/InAs) type-II MQW structure is formed on a substrate selected from GaAsSb substrates, GaAs substrates, and InP substrates.

(61) When the concentration adjusting layer 5b is provided, the foregoing structure results in a reduction in the concentration of the p-type impurity in the light-receiving layer 3. Unlike the structure according to this embodiment, even when the concentration adjusting layer 5b is not provided, a doping method may be employed in which, for example, in the step of forming the p-type contact layer 5a, the doping amount of the p-type impurity is gradually or stepwise increased from an undoped state or a lightly doped state with the lapse of growth time. The amount of the p-type impurity diffused toward the light-receiving layer 3 can be adjusted and reduced by the doping method of the impurity in the case of the absence of the concentration adjusting layer. Thus, even in the case of the absence of the concentration adjusting layer, it is possible to form the light-receiving layer 3 having a satisfactory type-II MQW structure with a high crystal quality. Naturally, in the case of the presence of the concentration adjusting layer 5b, the foregoing doping method may also be employed. Furthermore, when the selective growth layer is composed of a semiconductor material, such as InGaAs, having a relatively high electrical conductivity even at a low impurity concentration, it is possible to suppress the disadvantage of increasing the electrical resistance or the like even if a layer with a low concentration of the p-type impurity is included in the cap layer 5.

(62) While the embodiments and the examples of the present invention have been described, the disclosed embodiments and examples of the present invention are intended to illustrate and not limit the scope of the invention. The scope of the present invention is defined by the Claims. All changes which fall within meanings and scopes equivalent to the Claims are included.