Semiconductor device and method for manufacturing the same

Abstract

It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.

Claims

1. A semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on the substrate; and a gate electrode formed on the gate insulating film; wherein the gate insulating film includes silicon, oxygen and nitrogen, a nitrogen distribution is continuously formed across a part of the gate insulating film and a part of the gate electrode and the nitrogen distribution has a first peak and a second peak lower than the first peak, the first peak is located closer to the substrate than the second peak, the first peak has a substrate-side tail included in the gate insulating film.

2. The device according to claim 1, wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than nitrogen concentration at the first peak.

3. The device according to claim 1, wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than nitrogen concentration at the second peak.

4. The device according to claim 1, wherein nitrogen concentration of the first peak is in range of 20 atomic % to 47 atomic %.

5. The device according to claim 3, wherein nitrogen concentration of the first peak is in range of 20 atomic % to 47 atomic %.

6. The device according to claim 1, wherein the nitrogen distribution has a continuous region where nitrogen concentration is 20 atomic % or higher.

7. The device according to claim 6, wherein the continuous region has a physical film thickness of 1 nm or more.

8. The device according to claim 6, wherein the continuous region is in a region 5 nm or less from an interface between the gate insulating film and the gate electrode.

9. The device according to claim 6, wherein the first peak is located in the continuous region, and the second peak is located out of the continuous region.

10. The device according to claim 1, wherein a first distance of the first peak from an interface between the substrate and the gate insulating film is longer than a second distance of the second peak from an interface between the gate insulating film and the gate electrode.

11. The device according to claim 1, wherein the second peak has a gate electrode-sided tail, and the substrate-side tail is steeper than the gate electrode-sided tail of the second peak.

12. The device according to claim 1, wherein the substrate, the gate insulating film, and the gate electrode constitute a MOS transistor.

13. The device according to claim 1, wherein the gate electrode includes polysilicon.

14. A semiconductor device comprising: a semiconductor substrate; a gate insulating film formed on the substrate; and a gate electrode formed on the gate insulating film; wherein the gate insulating film has a multi layered structure and includes silicon, oxygen and nitrogen, a nitrogen distribution is continuously formed across a part of the gate insulating film and a part of the gate electrode, the nitrogen distribution has a first peak and a second peak lower than the first peak, the first peak is located closer to the substrate than the second peak, and the first peak has a substrate-side tail included in the gate insulating film.

15. The device according to claim 14, wherein the multi layered structure includes three stacked layers with a silicon oxide layer, a silicon oxynitride layer, and a silicon oxide layer.

16. The device according to claim 15, wherein nitrogen concentration in the silicon oxide layer adjacent to the substrate is 10 atomic % or less.

17. The device according to claim 14, wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than nitrogen concentration at the first peak.

18. The device according to claim 14, wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than nitrogen concentration at the second peak.

19. The device according to claim 14, wherein nitrogen concentration of the first peak is in range of 20 atomic % to 47 atomic %.

20. The device according to claim 18, wherein nitrogen concentration of the first peak is in range of 20 atomic % to 47 atomic %.

21. The device according to claim 14, wherein the nitrogen distribution has a continuous region where nitrogen concentration is 20 atomic % or higher.

22. The device according to claim 21, wherein the continuous region has a physical film thickness of 1 nm or more.

23. The device according to claim 21, wherein the continuous region is in a region 5 nm or less from an interface between the gate insulating film and the gate electrode.

24. The device according to claim 21, wherein the first peak is located in the continuous region, and the second peak is located out of the continuous region.

25. The device according to claim 14, wherein a first distance of the first peak from an interface between the substrate and the gate insulating film is longer than a second distance of the second peak from an interface between the gate insulating film and the gate electrode.

26. The device according to claim 14, wherein the second peak has a gate electrode-sided tail, and the substrate-side tail is steeper than the gate electrode-sided tail of the second peak.

27. The device according to claim 14, wherein the substrate, the gate insulating film, and the gate electrode constitute a MOS transistor.

28. The device according to claim 14, wherein the gate electrode includes polysilicon.

29. A semiconductor device comprising: a semiconductor substrate; a gate insulating film including silicon, oxygen, and nitrogen, formed on the substrate; and a gate electrode formed on the gate insulating film; wherein a nitrogen distribution is continuously formed across a part of the gate insulating film and a part of the gate electrode, a region in the gate insulating film where the nitrogen distribution is continuously formed has a first region having a first nitrogen concentration, a second region having a second nitrogen concentration lower than the first nitrogen concentration, and a third region having a third nitrogen concentration lower than the second nitrogen concentration, the first region is located closer to the substrate than the second and the third region and the third region is located closer to the substrate than the second region, and a peak of the nitrogen distribution in the first region has a substrate-side tail included in the gate insulating film.

30. The device according to claim 29, wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than the first nitrogen concentration.

31. The device according to claim 29, wherein nitrogen concentration at an interface between the gate insulating film and the gate electrode is lower than the second nitrogen concentration.

32. The device according to claim 29, wherein the first nitrogen concentration is in range of 20 atomic % to 47 atomic %.

33. The device according to claim 31, wherein nitrogen concentration of the first peak is in range of 20 atomic % to 47 atomic %.

34. The device according to claim 29, wherein the nitrogen distribution has a continuous region where nitrogen concentration is 20 atomic % or higher.

35. The device according to claim 34, wherein the continuous region has a physical film thickness of 1 nm or more.

36. The device according to claim 34, wherein the continuous region is in a region 5 nm or less from an interface between the gate insulating film and the gate electrode.

37. The device according to claim 34, wherein the first region is located in the continuous region, and the second region is located out of the continuous region.

38. The device according to claim 29, wherein a peak of the nitrogen distribution in the second region has a gate electrode-side tail, and the substrate-side tail is steeper than the gate electrode-side tail.

39. The device according to claim 29, wherein the substrate, the gate insulating film, and the gate electrode constitute a MOS transistor.

40. The device according to claim 29, wherein the gate electrode includes polysilicon.

41. The device according to claim 1, wherein the gate insulating film includes Hf.

42. The device according to claim 2, wherein the gate insulating film includes Hf.

43. The device according to claim 29, wherein the gate insulating film includes Hf.

44. The device according to claim 30, wherein the gate insulating film includes Hf.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A to 4B are cross-sectional views illustrating the procedures for manufacturing a semiconductor device according to a first embodiment;

(2) FIG. 5 shows the variations in the surface roughness after the amorphous silicon layer is nitrided in the first embodiment with respect to a case where oxygen is added and a case where oxygen is not added;

(3) FIG. 6 shows the results of a comparison made on the SILC properties of the stacked structure insulating film formed with a SiO.sub.2 layer, a SiON layer, and a SiO.sub.2 layer in a case where oxygen is added and a case where oxygen is not added;

(4) FIG. 7 shows the relationship between the conditions for adding oxygen to the amorphous silicon layer and the C-V characteristics;

(5) FIG. 8 shows the relationship between the conditions for adding oxygen to the amorphous silicon layer and the leakage current;

(6) FIG. 9 shows the relationship between the conditions for adding oxygen to the amorphous silicon layer and the C-V characteristics;

(7) FIG. 10 shows the relationship between the conditions for adding oxygen to the amorphous silicon layer and the leakage current;

(8) FIG. 11 shows the variation in leakage current observed where the applied voltage was 4 MV/cm;

(9) FIGS. 12A to 15B are cross-sectional views illustrating the procedures for manufacturing a semiconductor device according to a second embodiment;

(10) FIGS. 16A and 16B show the differences in erase characteristics between a case where surface nitridation is performed and a case where surface nitridation is not performed;

(11) FIG. 17 shows the differences in charge retention properties between a case where surface nitridation is performed and a case where surface nitridation is not performed;

(12) FIGS. 18A to 21B are cross-sectional views illustrating the procedures for manufacturing a semiconductor device according to a third embodiment;

(13) FIG. 22 shows the differences in reliability between a case where a heat treatment is carried out in an oxidizing atmosphere after nitridation and a case where the heat treatment is not carried out;

(14) FIGS. 23A to 26B are cross-sectional views illustrating the procedures for manufacturing a semiconductor device according to a fourth embodiment;

(15) FIGS. 27A and 27B show the relationship between the heat treatment conditions in an oxidizing atmosphere and the reliability;

(16) FIG. 28 shows the relationship between the oxidation time and the electric field required to inject 0.01 A/cm.sup.2 of electrons;

(17) FIGS. 29A to 32B are cross-sectional views illustrating the procedures for manufacturing a semiconductor device according to a fifth embodiment;

(18) FIG. 33 illustrates the effects of adding Ge to the silicon oxide layer;

(19) FIG. 34 is an energy band diagram of a case where Ge is added to the silicon oxide layer;

(20) FIG. 35 illustrates the reason to define the layer thickness of the amorphous silicon layer;

(21) FIG. 36 illustrates the defined distribution of the nitrogen concentration in the tunnel insulating film having a three-layer stacked structure; and

(22) FIG. 37 also illustrates the defined distribution of the nitrogen concentration in the tunnel insulating film having a three-layer stacked structure.

DETAILED DESCRIPTION OF THE INVENTION

(23) The following is a description of embodiments of the present invention, with reference to the accompanying drawings.

First Embodiment

(24) Referring to FIGS. 1A to 4B, a method for manufacturing a semiconductor device in accordance with a first embodiment of the present invention is described. FIGS. 1A, 1C, 1E, 2A, 2C, 3A, 3C, and 4A are cross-sectional views that are taken perpendicularly to the cross-sectional views of FIGS. 1B, 1D, 1F, 2B, 2D, 3B, 3D, and 4B.

(25) A semiconductor device manufactured by the manufacturing method in accordance with this embodiment is a FG (floating gate) nonvolatile semiconductor memory that includes memory cells arranged in a matrix fashion. As shown in FIGS. 4A and 4B, each of the memory cells includes: source and drain regions 17a and 17b that are formed at a distance from each other in a silicon substrate 1; a tunnel insulating film 5 that is formed on a region 18 of the silicon substrate 1 located between the source region 17a and the drain region 17b to be channel; a floating gate electrode 6 that is formed on the tunnel insulating film 5 and serves as a charge storage film having charges stored therein; an interelectrode insulating film 10 that is formed on the floating gate electrode 6; and a control gate electrode 11 that is formed on the interelectrode insulating film 10.

(26) Next, the method for manufacturing the semiconductor device in accordance with this embodiment is described.

(27) First, as shown in FIGS. 1A and 1B, the silicon substrate 1 doped with desired impurities is subjected to diluted hydrofluoric acid treatment, so as to terminate the surface of the silicon substrate 1 with hydrogen. After that, the silicon substrate 1 is left in the chamber of a film forming device (not shown). The chamber is filled only with a gas (such as a nitrogen gas) that does not react with or etch silicon during the manufacturing process. The temperature of the silicon substrate 1 is then heated to 700 C., so as to completely detach the hydrogen from the silicon substrate 1. The chamber is then filled with a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 3 Torr, for example. The surface of the silicon substrate 1 is heated to 1050 C., and is maintained at that temperature for ten seconds. In this manner, a silicon oxide layer 2 is formed on the silicon substrate 1, as shown in FIGS. 1C and 1D.

(28) An amorphous silicon layer of 2 nm in thickness is then deposited on the silicon oxide layer 2 with the use of a disilane gas. It is preferable that the temperature of the silicon substrate 1 at this point is 550 C. or lower. The atmosphere at the time of deposition of the amorphous silicon layer 3 may contain oxygen, NO, or N.sub.2O. If the atmosphere contains NO or N.sub.2O in this case, the resultant amorphous silicon layer contains a small amount of nitrogen. The temperature of the silicon substrate 1 is set at 750 C. and the atmosphere in the chamber is changed to a N.sub.z gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 3 Torr, for example. These conditions are maintained for ten seconds. In this manner, a small amount of oxygen is added to the amorphous silicon layer, and an oxygen-added amorphous silicon layer is formed. After that, the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and a NH.sub.3 gas having a partial pressure of 0.03 Torr, for example. The surface of the silicon substrate 1 is then set at 750 C., and is maintained at that temperature for 400 seconds. In this manner, the amorphous silicon layer is nitrided to form a silicon oxynitride layer 3 (see FIGS. 1E and 1F). By the manufacturing method in accordance with this embodiment, a nitrogen gas NH.sub.3 diluted with a N.sub.2 gas is used to form the silicon oxynitride layer 3. By diluting the nitrogen gas NH.sub.3 with a dilution gas N.sub.2, a high-quality silicon oxynitride layer having few defects can be formed. This nitriding technique using NH.sub.3 was invented by the inventor of the present invention, and a patent application covering this technique was filed (see JP-A 2007-123825(KOKAI)).

(29) The temperature of the silicon substrate 1 is then set at 750 C. or higher, and a 5-nm thick silicon oxide layer 4 is deposited on the silicon oxynitride layer 3 by the HTO (High Temperature Oxidation) technique. By doing so, the tunnel insulating film 5 including the silicon oxide layer 2, the silicon oxynitride layer 3, and the silicon oxide layer 4 is formed as shown in FIGS. 1E and 1F. It should be noted here that, in the drawings illustrating the manufacturing procedures carried out after this procedure, the tunnel insulating film 5 including the silicon oxide layer 2, the silicon oxynitride layer 3, and the silicon oxide layer 4 is shown as a single-layer tunnel insulating film 5.

(30) A 60-nm thick, phosphorus-doped polycrystalline silicon film 6 to be the floating gate electrode, and a mask material 7 for device isolation are then deposited in this order by the CVD (Chemical Vapor Deposition) technique. After that, etching is performed on the mask material 7, the polycrystalline silicon film 6, and the tunnel insulating film 5 in this order by the RIE (Reactive Ion Etching) technique with the use of a resist mask (not shown). Etching is further performed on the exposed regions of the silicon substrate 1, so as to form device isolation grooves 8 of 100 nm in depth (see FIGS. 2A and 2B).

(31) A silicon oxide film 9 for device isolation is then deposited on the entire surface, so as to completely fill the device isolation grooves 8. After that, the portion of the silicon oxide film 9 on the surface is removed by the CMP (Chemical Mechanical Polishing) technique, so that the surface is flattened. At this point, the mask material 7 is exposed (see FIGS. 2C and 2D).

(32) The exposed mask material 7 is selectively removed by etching, and the exposed surface portions of the silicon oxide film 9 are removed by etching with the use of a diluted hydrofluoric acid solution. In this manner, side faces 6a of the polycrystalline silicon film 6 are partially exposed. After that, a 15-nm thick alumina layer 10a is formed on the entire surface by the ALD (Atomic Layer Deposition) technique. Due to the oxidizing agent used in the film formation by ALD, a very thin silicon oxide layer 10b is formed at the interface between the alumina layer 10a and the polycrystalline silicon film 6. As a result, a 16-nm thick interelectrode insulating film 10 having a two-layer structure consisting of the alumina layer 10a and the silicon oxide layer 10b is formed (see FIGS. 3A and 3B), In FIGS. 3A and 3B, the interelectrode insulating film 10 having the two-layer structure of the silicon oxide layer 10b and the alumina layer 10a is shown as a single-layer interelectrode insulating film 10, instead of a two-layer stacked structure.

(33) A polycrystalline silicon layer is then formed on the interelectrode insulating film 10 by CVD. After that, a tungsten layer is formed on this polycrystalline silicon layer, and a heat treatment is carried out to turn the tungsten layer into a tungsten silicide layer. In this manner, a 100-nm thick conductive film 11 having a two-layer structure consisting of the polycrystalline silicon layer and the tungsten silicide layer is formed (see FIGS. 3C and 3D). This conductive film 11 serves as the control gate electrode 11. A mask material 12 for RIE is then deposited on the entire surface by CVD. Etching is performed by RIE on the mask material 12, the conductive film 11, the interelectrode insulating film 10, the polycrystalline silicon film 6, and the tunnel insulating film 5 in this order, so as to form the gate having a stacked structure. In this manner, the shape of the gate having the stacked structure is defined, and grooves 14 extending in the word-line direction (the direction in which the control gate electrode 11 extends) are formed on the side of this gate having the stacked structure (see FIGS. 3C and 3D).

(34) As shown in FIGS. 4A and 4B, a silicon oxide film 16 is then formed on the side faces and the upper face of the gate having the stacked structure by a thermal oxidation technique. After that, the source and drain regions 17a and 17b are formed by an ion injection technique. The region of the silicon substrate 1 located between the source region 17a and the drain region 17b is the channel region 18. Further, an interlayer insulating film 19 is formed to cover the entire surface by CVD. After that, a wiring layer and the likes are formed by known techniques, so as to complete the nonvolatile semiconductor memory (see FIGS. 4A and 4B).

(35) The silicon oxynitride layer in the tunnel insulating film 5 formed by performing nitridation after oxygen is added to the amorphous silicon layer has higher flatness and fewer hydrogen radicals. Thus, improvement of not only the charge retention properties but also the reliability can be expected. For example, FIG. 5 shows the variation in the surface roughness under different conditions for forming the silicon oxynitride layer. FIG. 6 shows the variation in the SILC (Stress Induced Leakage Current) properties. More specifically, FIG. 5 shows the surface roughness observed where a silicon nitride layer is formed by performing nitridation directly on an amorphous silicon layer, and the surface roughness observed where a silicon oxynitride layer is formed by performing nitridation after oxygen is added to an amorphous silicon layer. As can be seen from FIG. 5, the surface roughness is reduced by performing the nitridation after oxygen is added to the amorphous silicon. This indicates that agglomeration of the amorphous silicon layer at the time of nitridation is prevented by adding oxygen to the amorphous silicon layer, and the flatness of the silicon oxynitride layer is increased accordingly.

(36) FIG. 6 shows the results of comparisons of SILC properties between a MOS transistor having a gate insulating film of a stacked structure formed with SiO.sub.2, SiON, and SiO.sub.2, and a MOS transistor having a gate insulating film of a stacked structure formed with SiO.sub.2, SiN, and SiO.sub.2. As can be seen from FIG. 6, the SILC is reduced by performing the nitridation after oxygen is added to the amorphous silicon layer. This indicates that, as the flatness and the insulation quality are improved, the hydrogen radicals in the amorphous silicon layer are substituted with the oxygen, and the amount of hydrogen radial becomes smaller. In other words, the reliability is improved by performing the nitridation after oxygen is added to the amorphous silicon layer. In FIG. 6, the ordinate axis indicates the leakage current J.sub.g, and the abscissa axis indicates the value obtained by dividing the difference between the gate voltage V.sub.g and the flat-band voltage V.sub.fb by the electrically effective film thickness T.sub.eff of the transistor. This value indicated by the abscissa axis represents the electric field induced in the insulating film. This arrangement is made to eliminate the influence of the fixed charges in the insulating film, and compare the insulating properties at the intensity of the electric field induced in the insulating film. This is because, since the flat-band voltage V.sub.fb shifts in accordance with the amount of fixed charges in the film, the electric field induced in the insulating film is wrongly estimated when a comparison is made only in terms of the gate voltage V.sub.g. The electrically effective film thickness T.sub.eff of the transistor includes not only the electrically effective film thickness of the gate insulating film but also the thickness of the depletion layer in the polysilicon electrode and the thickness of the inversion layer on the side of the semiconductor substrate. When a voltage is applied to a MOS structure, the voltage is applied not only to the gate insulating film but also to the gate electrode and the semiconductor substrate. With the voltage, an inversion layer is formed on the semiconductor substrate side, and a depletion layer is formed on the gate electrode side. These layers are connected as capacitances in series to the capacitance of the gate insulating film. Those series-connected capacitances function as the electrically effective film thickness when the transistor is on.

(37) When oxygen is added to the amorphous silicon layer, it is necessary to pay attention to the temperature, the oxygen partial pressure, the time, the heating-up time, and the timing for introducing oxygen. It is preferable that the temperature is 700 C. or higher, at which hydrogen is detached from the amorphous silicon layer. However, the temperature cannot be too high, and should preferably be 800 C. or lower. Furthermore, it is preferable to supply oxygen while the temperature is rising. This is because movement of the silicon is limited by the oxygen entering the amorphous silicon layer and being coupled with the silicon. This is also because, when the amorphous silicon layer is heated in a vacuum containing no oxygen at a high temperature, agglomeration is formed as the weak bonds in the amorphous silicon layer turn into stable bonds and crystals that lead to an increase in the roughness.

(38) The oxygen partial pressure should preferably be low so as to reduce the oxidation speed and increase the controllability. More preferably, the oxygen partial pressure should be 50 Torr or lower. However, the oxygen partial pressure cannot be too low. If it is too low, an active oxidation region is formed where silicon etching is caused by the oxygen with the low partial pressure. The oxygen partial pressure should preferably be 10.sup.4 Torr or higher, which is a passive oxidation region where oxidation is caused at 700 C. to 800 C. The time required for the temperature rise to a point between 700 C. and 800 C. should preferably be 10 seconds or less. If the temperature rise takes long while oxygen is being supplied, the 2-nm thick amorphous silicon layer is completely oxidized before the temperature reaches the target temperature, and a SiO.sub.2 layer in which nitrogen is easily diffused is readily formed. Because of this, a large amount of nitrogen penetrates through the amorphous silicon oxide layer and the SiO.sub.2 layer below the amorphous silicon oxide layer due to the nitridation caused after that. The Si substrate is then nitrided, and many interface states are formed. Ideally, while oxygen is being supplied, it is preferable that the time required for the temperature to reach a point between 700 C. and 800 C. is ten seconds or less, and the oxidation time at a temperature between 700 C. and 800 C. is ten seconds or less. Within this time limit, the 2-nm thick amorphous silicon layer is not completely oxidized, and nitridation can be performed on the amorphous silicon layer while nitrogen is restrained from penetrating through the amorphous silicon layer.

(39) Further, to prevent complete oxidation of the amorphous silicon layer, and to oxidize the interface at a low temperature so as not to increase the interface state density, oxygen should not be supplied while the temperature is dropping.

(40) Referring now to FIGS. 7 to 11, the relationship between the conditions for adding oxygen to the amorphous silicon layer deposited on the SiO.sub.2 layer and the electrical characteristics is described. The silicon nitride layer of the transistor having the stack gate structure consisting of a Si layer, SiO.sub.2 layer, the silicon nitride layer, and an Au layer each having substantially the same capacitance C was formed by several different methods, and the electrical characteristics were examined. More specifically, the electrical characteristics were examined with respect to the case where the silicon nitride layer was formed by performing the nitridation after oxygen was added to the amorphous silicon layer at the oxidation temperature of 750 C. and in the oxidation time of ten seconds (in this case, the silicon nitride layer was a silicon oxynitride layer (SiON layer)) as in this embodiment, the case as Comparative Example 1 where the silicon nitride layer was formed by performing the nitridation without oxygen added to the amorphous silicon layer, and the case as Comparative Example 2 where the silicon nitride layer was formed in the same manner as in this embodiment, except that the oxidation temperature was as high as 850 C.

(41) FIG. 7 shows the results of examinations conducted on the dependence of the capacitance C on the gate voltage V.sub.g, or the C-V characteristics. FIG. 8 shows the results of examinations conducted on the dependence of the leakage current J.sub.g on the intensity of the electric field induced in the insulating film (=(V.sub.gV.sub.fb)/T.sub.eff). As can be seen from these graphs, in Comparative Example 1, or in a case where the oxidation time is ten seconds as in this embodiment but the oxidation temperature is as high as 850 C. as in Comparative Example 2, hysteresis occurs in the C-V characteristics, and the interface state density and the leakage current are higher than in this embodiment. These facts indicate that, since oxygen was not added to the amorphous silicon layer in Comparative Example 1, the amorphous silicon layer was agglomerated at the time of the nitridation at 700 C., irregularity was caused in the layer thickness, the nitridation became uneven to leave non-nitrided portions (to be more specific, Si dangling bonds), and the nitrogen penetrated through the SiO.sub.2 layer below the amorphous silicon layer. The above facts also indicate that, since the oxidation temperature was high in Comparative example 2, the amorphous silicon layer was agglomerated, irregularity was caused in the layer thickness, the nitridation became uneven to leave non-nitrided portions, and the nitrogen penetration occurred.

(42) Next, electrical characteristics were also examined with respect to a case as Comparative Example 3 where the oxidation temperature and the oxidation time were the same as those in this embodiment (750 C., ten seconds) but oxygen was not supplied while oxygen was added, and a case as Comparative Example 4 where the oxygen temperature was the same as that in this embodiment but the oxidation time was 15 seconds. FIG. 9 shows the results of examinations conducted on the dependence of the capacitance C on the gate voltage V.sub.g, or the C-V characteristics. FIG. 10 shows the results of examinations conducted on the dependence of the leakage current J.sub.g on the intensity of the electric field induced in the insulating film (=(V.sub.gV.sub.fb)/T.sub.eff).

(43) As can be seen from these graphs, in both Comparative Examples 3 and 4, large hysteresis occurred in the C-V characteristics, and the interface state density and the leakage current became higher than in this embodiment. These facts indicate that, since there was no oxygen while the temperature was rising in Comparative Example 3, the amorphous silicon layer was agglomerated, irregularity was caused in the layer thickness, the nitridation became uneven to leave non-nitrided portions, and the nitrogen penetration occurred. These facts also indicate that, since the oxidation time was long in Comparative example 4, the amorphous silicon layer was completely oxidized to form a SiO.sub.2 layer, the nitrogen penetrated through the SiO.sub.2 layer, and the Si substrate was nitrided.

(44) FIG. 11 shows the variation in leakage current observed where the applied voltage was 4 MV/cm, and the oxidation conditions were varied. FIG. 11 shows the ratio between the leakage current value observed where the nitridation was performed without the oxygen addition, and the leakage current value observed where the nitridation was performed after oxygen was added. For example, the ratio of 50% indicates that the leakage current was reduced by half where oxygen was added. As is apparent from the results shown in FIG. 11, the leakage current can be very effectively reduced by adding oxygen at a temperature between 700 C. to 800 C. in ten seconds or less. The reasons for this are as described above.

(45) In this manner, a high-quality tunnel insulating film having a stacked structure formed with a SiO.sub.2 layer, a SiON layer, and a SiO.sub.2 layer can be realized by adding oxygen to the amorphous silicon layer under appropriate conditions.

(46) The silicon oxynitride layer 3 has a layer thickness of 1.5 nm to 2.5 nm, and nitrogen concentration of 20 atomic % to 47 atomic %. In other words, 10 atomic % to 30 atomic % of oxygen is contained in the silicon oxynitride layer 3, and at least one of the second nearest neighbor atoms of the silicon is nitrogen. This is because oxygen is added to the amorphous silicon layer. In the silicon oxide layer 2, a small amount of nitrogen is diffused when the amorphous silicon layer is nitrided. Therefore, an average of 10 atomic % of nitrogen is contained at a maximum.

(47) Although an O.sub.2 gas is used when oxygen is added to the amorphous silicon layer in this embodiment, the gas used at the time of adding oxygen is not limited to an O.sub.2 gas, and it is possible to use any oxidizing gas such as NO, N.sub.2O, O.sub.3, O radicals, or O plasma. However, those gases differ from O.sub.2 in oxidation power. Therefore, when one of those gases is used, it is necessary to adjust the oxygen adding conditions in such a manner that the oxygen concentration in the amorphous silicon oxynitride layer 3 is in the range of 10 atomic % to 30 atomic %.

(48) Although a NH.sub.3 gas is used when the amorphous silicon layer is nitrided in this embodiment, the gas used at the time of nitridation is not limited to a NH.sub.3 gas, and it is possible to use any nitriding gas such as NO, N radicals, NH radicals, N.sub.2 radicals, N plasma, NH plasma, or N.sub.2 plasma.

(49) Although HTO is used in the process for forming the SiO.sub.2 layer 4 in this embodiment, some other technique such as CVD or ALD may be used, as long as the SiO.sub.2 layer 4 can be properly deposited.

(50) As described so far, this embodiment can provide a semiconductor device that has a high-quality tunnel insulating film in which defects are not easily formed. This semiconductor device experiences less leakage current.

Second Embodiment

(51) Referring to FIGS. 12A to 15B, a method for manufacturing a semiconductor device in accordance with a second embodiment of the present invention is described. FIGS. 12A, 12C, 12E, 13A, 13C, 14A, 14C, and 15A are cross-sectional views that are taken perpendicularly to the cross-sectional views of FIGS. 12B, 12D, 12F, 13B, 13D, 14B, 14D, and 15B.

(52) A semiconductor device manufactured by the manufacturing method in accordance with this embodiment is a MONOS (Metal-Oxide-Nitride-Oxide-Si) nonvolatile semiconductor memory that includes memory cells arranged in a matrix fashion. As shown in FIGS. 15A and 15B, each of the memory cells includes: source and drain regions 37a and 37b that are formed at a distance from each other in a silicon substrate 1; a tunnel insulating film 25 that is formed on a region 38 of the silicon substrate 1 located between the source region 37a and the drain region 37b to be channel; a charge storage film 26 that is formed on the tunnel insulating film 25 and is made of an insulating material in which charges can be stored; an interelectrode insulating film 30 that is formed on the charge storage film 26; and a control gate electrode 31 that is formed on the interelectrode insulating film 30.

(53) Next, the method for manufacturing the semiconductor device in accordance with this embodiment is described. The manufacturing method in accordance with this embodiment differs from the manufacturing method in accordance with the first embodiment, in further including the procedure for nitriding the silicon oxide layer serving as the base layer of the amorphous silicon layer before the amorphous silicon layer is formed.

(54) First, as shown in FIGS. 12A and 12B, the silicon substrate doped with desired impurities is subjected to diluted hydrofluoric acid treatment, so as to terminate the surface of the silicon substrate 1 with hydrogen. After that, the silicon substrate 1 is placed in the chamber of a film forming device (not shown). The chamber is filled only with a gas (such as a nitrogen gas) that does not react with or etch silicon during the manufacturing process. The temperature of the silicon substrate 1 is then heated to 700 C., so as to completely detach the hydrogen from the silicon substrate 1.

(55) The chamber is then filled with a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 3 Torr, for example. The surface of the silicon substrate 1 is heated to 1050 C., and is maintained at that temperature for ten seconds. In this manner, a silicon oxide layer 22a is formed on the silicon substrate 1, as shown in FIGS. 12C and 12D. The procedures described so far are the same procedures carried out in the first embodiment. Radical nitridation or plasma nitridation is then performed on the surface of the silicon oxide layer 22a. By doing so, a nitrogen-containing layer 22b is formed on the surface of the silicon oxide layer 22a, and nitrogen is introduced into the silicon oxide layer 22a so that the peak concentration in the profile becomes 10 atomic % or lower (see FIGS. 12C and 12D). In this manner, a nitrogen-added silicon oxide layer 22 having a two-layer structure consisting of the silicon oxide layer 22a and the nitrogen-containing layer 22b is formed. In this nitriding procedure, this embodiment differs from the first embodiment. Through this nitriding procedure, the hole injecting efficiency in each memory cell is increased, as will be described later. It should be noted here that, in the drawings illustrating the manufacturing procedures carried out after this nitriding procedure, the silicon oxide layer 22 having the two-layer structure consisting of the silicon oxide layer 22a and the nitrogen-containing layer 22b is shown as a single-layer silicon oxide layer 22.

(56) An amorphous silicon layer of 2 nm in thickness is then deposited on the silicon oxide layer 22 with the use of a disilane gas. It is preferable that the temperature of the silicon substrate 1 at this point is 550 C. or lower. The atmosphere at the time of deposition of the amorphous silicon layer may contain oxygen, NO, or N.sub.2O. If the atmosphere contains NO or N.sub.2O in this case, the resultant amorphous silicon layer contains a small amount of nitrogen. The temperature of the silicon substrate 1 is set at 750 C., and the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 3 Torr, for example. These conditions are maintained for ten seconds. In this manner, a small amount of oxygen is added to the amorphous silicon layer, and an oxygen-added amorphous silicon layer is formed. As in the first embodiment, the oxidizing temperature at this point should preferably be 700 C. or higher, at which the hydrogen in the amorphous silicon layer is detached. However, the oxidizing temperature cannot be too high, and should preferably be 800 C. or lower. Furthermore, it is preferable to supply oxygen while the temperature is rising. Also, as in the first embodiment, the time required for the temperature to rise to a point between 700 C. and 800 C. should preferably be ten seconds or less. Ideally, while oxygen is being supplied, the heating-up time is ten seconds or less, and the oxidation time is ten seconds or less. After that, the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and a NH.sub.3 gas having a partial pressure of 0.03 Torr, for example. The surface of the silicon substrate 1 is then set at 750 C., and is maintained at that temperature for 400 seconds. In this manner, the amorphous silicon layer is nitrided to form a silicon oxynitride layer 23 (see FIGS. 12E and 12F). As described in the first embodiment, the silicon oxynitride layer 23 formed by the manufacturing method in accordance with this embodiment is a high-quality silicon oxynitride layer having few defects.

(57) The temperature of the silicon substrate 1 is then set at 750 C. or higher, and a 2.5-nm thick silicon oxide layer 24 is deposited on the silicon oxynitride layer 23 by HTO. By doing so, the tunnel insulating film 25 including the silicon oxide layer 22, the silicon oxynitride layer 23, and the silicon oxide layer 24 is formed as shown in FIGS. 12E and 12F. It should be noted here that, in the drawings illustrating the manufacturing procedures carried out after this procedure, the tunnel insulating film 25 having the three-layer structure consisting of the silicon oxide layer 22, the silicon oxynitride layer 23, and the silicon oxide layer 24 is shown as a single-layer tunnel insulating film 25.

(58) A 6-nm thick nitride film 26 to be the charge storage film such as a Si.sub.3N.sub.4 film is then deposited on the tunnel insulating film 25 by CVD, and a mask material 27 for device isolation is deposited by CVD. After that, etching is performed on the mask material 27, the nitride film 26, and the tunnel insulating film 25 in this order by RIE with the use of a resist mask (not shown). Etching is further performed on the exposed regions of the silicon substrate 1, so as to form device isolation grooves 28 of 100 nm in depth (see FIGS. 13A and 13B).

(59) A silicon oxide film 29 for device isolation is then deposited on the entire surface, so as to completely fill the device isolation grooves 28. After that, the portion of the silicon oxide film 29 on the surface is removed by CMP, so that the surface is flattened. At this point, the mask material 27 is exposed (see FIGS. 13C and 13D).

(60) The exposed mask material 27 is selectively removed by etching, and the exposed surface portions of the silicon oxide film 29 are removed by etching with the use of a diluted hydrofluoric acid solution. After that, a 15-nm thick alumina layer 30a to be the interelectrode insulating film is formed on the entire surface by ALD. Due to the oxidizing agent used in the film formation by ALD, a very thin silicon oxide layer 30b is formed at the interface between the alumina layer 30a and the nitride film 26. As a result, a 16-nm thick interelectrode insulating film 30 having a two-layer structure consisting of the alumina layer 30a and the silicon oxide layer 30b is formed (see FIGS. 14A and 14B). It should be noted here that, in the drawings illustrating the manufacturing procedures carried out after this procedure, the interelectrode insulating film 30 having the two-layer structure of the silicon oxide layer 30b and the alumina layer 30a is shown as a single-layer interelectrode insulating film 30.

(61) A 100-nm thick conductive film 31 having a two-layer structure consisting of a polycrystalline silicon layer and a tungsten silicide layer is formed to be the control gate electrode on the interelectrode insulating film 30 in the same manner as in the first embodiment. Further, a mask material 32 for RIE is deposited by CVD. After that, etching is performed by RIE with the use of a resist mask (not shown) on the mask material 32, the conductive film 31, the interelectrode insulating film 30, the charge storage film 26, and the tunnel insulating film 25 in this order, so as to form the gate having a stacked structure. In this manner, the shape of the gate having the stacked structure is defined, and grooves 34 extending in the word-line direction (the direction in which the control gate electrode 31 extends) are formed on the side of this gate having the stacked structure (see FIGS. 14C and 14D).

(62) As shown in FIGS. 15A and 15B, a silicon oxide film 36 is then formed on the side faces and the upper face of the gate having the stacked structure by a thermal oxidation technique.

(63) After that, the source and drain regions 37a and 37b are formed by an ion injection technique. The region of the silicon substrate 1 located between the source region 37a and the drain region 37b is the channel region 38. Further, an interlayer insulating film 39 is formed to cover the entire surface by CVD. After that, a wiring layer and the likes are formed by known techniques, so as to complete the nonvolatile semiconductor memory (see FIGS. 15A and 15B).

(64) By performing nitridation on the surface of the SiO.sub.2 layer before the deposition of the amorphous silicon layer in the above described manner, the charge retention properties and the reliability described in the first embodiment can be further improved, and an increase in erasing efficiency can be expected. FIGS. 16A and 16B show the differences in the charge retention properties between a case with the surface nitridation and a case without the surface nitridation. FIG. 17 shows the differences in the erase characteristics. In FIGS. 16A and 16B, the abscissa axis indicates the charge retention time, and the ordinate axis indicates the difference between the flat-band voltage V.sub.fb and the initial flat-band voltage V.sub.fbni. In FIG. 17, the abscissa axis indicates the initial erase field, and the ordinate axis indicates the flat-band voltage. As can be seen from FIGS. 16A, 15B, and 17, by performing nitridation on the surface of the SiO.sub.2 layer before the amorphous silicon layer is deposited, the retention properties and the erase characteristics are both improved. The retention properties are improved, because dangling bonds are formed on the surface of the SiO.sub.2 layer, and the flatness of the amorphous silicon layer formed on the SiO.sub.2 layer is increased. Accordingly, the insulating properties are further improved. Also, diffusion of nitrogen into the SiO.sub.2 layer is prevented by introducing nitrogen into the surface of the SiO.sub.2 layer, and nitriding species are prevented from penetrating through the SiO.sub.2 layer and nitriding the Si substrate when the amorphous silicon layer is later nitrided. As a result, formation of interface states to be the origin of low-field leakage current is restricted. The erase characteristics are improved because, as nitrogen is introduced into the SiO.sub.2 layer, the hole barrier of the SiO.sub.2 layer becomes smaller, and the density of hole current tunneling from the substrate side to the charge storage film side becomes higher. As a result, the erasing efficiency of the electrons in the charge storage film becomes higher.

(65) In this manner, a high-quality tunnel insulating film having a three-layer stacked structure formed with a SiO.sub.2 layer, a SiON layer, and a SiO.sub.2 layer can be realized by nitriding the surface of the lower SiO.sub.2 layer before the amorphous silicon layer is deposited.

(66) The silicon oxynitride layer 23 has a layer thickness of 1.5 nm to 2.5 nm, and nitrogen concentration of 20 atomic % to 47 atomic %. In other words, 10 atomic % to 30 atomic % of oxygen is contained in the silicon oxynitride layer 23, and at least one of the second nearest neighbor atoms of the silicon is nitrogen. This is because oxygen is added to the amorphous silicon layer. In the silicon oxide layer 22, a small amount of nitrogen is diffused when the amorphous silicon layer is nitrided. Therefore, an average of 10 atomic % of nitrogen is contained at a maximum.

(67) In this embodiment, radical nitridation or plasma nitridation is performed on the surface of the silicon oxide layer 22. However, to prevent nitrogen from penetrating through the silicon oxide layer 22 and nitriding the silicon substrate, it is not necessary to perform radical nitridation or plasma nitridation, and NH.sub.3 or NO may be used instead.

(68) Although an O.sub.2 gas is used when oxygen is added to the amorphous silicon layer in this embodiment, the gas used at the time of adding oxygen is not limited to an O.sub.2 gas, and it is possible to use any oxidizing gas such as NO, N.sub.2O, O.sub.3, O radicals, or O plasma. However, those gases differ from O.sub.2 in oxidation power. Therefore, when one of those gases is used, it is necessary to adjust the oxygen adding conditions in such a manner that the oxygen concentration in the silicon oxynitride layer 23 is in the range of 10 atomic % to 30 atomic %.

(69) Although a NH.sub.3 gas is used when the amorphous silicon layer is nitrided in this embodiment, the gas used at the time of nitridation is not limited to a NH.sub.3 gas, and it is possible to use any nitriding gas such as NO, N radicals, NH radicals, N.sub.2 radicals, N plasma, NH plasma, or N.sub.2 plasma.

(70) Although HTO is used in the process for forming the SiO.sub.2 layer 24 in this embodiment, some other technique such as CVD or ALD may be used, as long as the SiO.sub.2 layer 24 can be properly deposited. As described so far, this embodiment can provide a semiconductor device that has a high-quality tunnel insulating film in which defects are not easily formed. This semiconductor device experiences less leakage current.

Third Embodiment

(71) Referring now to FIGS. 18A to 21B, a method for manufacturing a semiconductor device in accordance with a third embodiment of the present invention is described. FIGS. 18A, 18C, 18E, 19A, 19C, 20A, 20C, and 21A are cross-sectional views that are taken perpendicularly to the cross-sectional views of FIGS. 18B, 18D, 18F, 19B, 19D, 20B, 20D, and 21B.

(72) A semiconductor device in accordance with this embodiment is a MONOS nonvolatile semiconductor memory that includes memory cells arranged in a matrix fashion. As shown in FIGS. 21A and 21B, each of the memory cells includes:

(73) source and drain regions 57a and 57b that are formed at a distance from each other in a silicon substrate 1; a tunnel insulating film 45 that is formed on a region 58 of the silicon substrate 1 located between the source region 57a and the drain region 57b; a charge storage film 46 that is formed on the tunnel insulating film 45 and is made of an insulating material in which charges can be stored; an interelectrode insulating film 50 that is formed on the charge storage film 46; and a control gate electrode 51 that is formed on the interelectrode insulating film 50.

(74) Next, the method for manufacturing the semiconductor device in accordance with this embodiment is described. The manufacturing method in accordance with this embodiment differs from the manufacturing method in accordance with the second embodiment, in further including the procedure for oxidizing a silicon oxynitride layer before a silicon oxide layer is formed on the silicon oxynitride layer.

(75) First, as shown in FIGS. 18A and 18B, the silicon substrate 1 doped with desired impurities is subjected to diluted HF treatment, so as to terminate the surface of the silicon substrate 1 with hydrogen. After that, the silicon substrate 1 is placed in the chamber of a film forming device. The chamber is filled only with a gas (such as a nitrogen gas) that does not react with or etch silicon during the manufacturing process. The temperature of the silicon substrate 1 is then heated to 700 C., so as to completely detach the hydrogen from the silicon substrate 1.

(76) The chamber is then filled with a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 3 Torr, for example. The surface of the silicon substrate 1 is heated to 1050 C., and is maintained at that temperature for ten seconds. In this manner, a silicon oxide layer 42a is formed on the silicon substrate 1, as shown in FIGS. 18C and 18D. Radical nitridation or plasma nitridation is then performed on the surface of the silicon oxide layer 42a. By doing so, a nitrogen-containing layer 42b is formed on the surface of the silicon oxide layer 42a, and nitrogen is introduced into the silicon oxide layer 42a so that the peak concentration in the profile becomes 10 atomic % or lower (see FIGS. 18C and 18D). In the same manner as in the second embodiment, a nitrogen-added silicon oxide layer 42 having a two-layer structure consisting of the silicon oxide layer 42a and the nitrogen-containing layer 42b is formed. Through this nitriding procedure, the hole injecting efficiency in each memory cell is increased. It should be noted here that, in the drawings illustrating the manufacturing procedures carried out after this nitriding procedure, the silicon oxide layer 42 having the two-layer structure consisting of the silicon oxide layer 42a and the nitrogen-containing layer 42b is shown as a single-layer silicon oxide layer 42.

(77) An amorphous silicon layer of 2 nm in thickness is then deposited on the silicon oxide layer 42 with the use of a disilane gas. It is preferable that the substrate temperature at this point is 550 C. or lower. The atmosphere at the time of deposition of the amorphous silicon layer may contain oxygen, NO, or N.sub.2O. If the atmosphere contains NO or N.sub.2O in this case, the resultant amorphous silicon layer contains a small amount of nitrogen. The temperature of the silicon substrate 1 is set at 750 C., and the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 3 Torr, for example. These conditions are maintained for ten seconds. In this manner, a small amount of oxygen is added to the amorphous silicon layer, and an oxygen-added amorphous silicon layer is formed. As in the first embodiment, the oxidizing temperature at this point should preferably be 700 C. or higher, at which the hydrogen in the amorphous silicon layer is detached. However, the oxidizing temperature cannot be too high, and should preferably be 800 C. or lower. Furthermore, it is preferable to supply oxygen while the temperature is rising. Also, the time required for the temperature to rise to a point between 700 C. and 800 C. should preferably be ten seconds or less. Ideally, while oxygen is being supplied, the heating-up time is ten seconds or less, and the oxidation time is ten seconds or less. After that, the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and a NH.sub.3 gas having a partial pressure of 0.03 Torr, for example. The surface of the silicon substrate 1 is then set at 750 C., and is maintained at that temperature for 400 seconds. In this manner, the amorphous silicon layer is nitrided to form a silicon oxynitride layer 43 (see FIGS. 18E and 18F). As described in the first embodiment, the silicon oxynitride layer 43 formed by the manufacturing method in accordance with this embodiment is a high-quality silicon oxynitride layer having few defects.

(78) The temperature of the silicon substrate 1 is then set at 800 C., and the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 0.03 Torr. These conditions are maintained for 100 seconds. As a result, the SiNH in the silicon oxynitride layer 43 is oxidized, and the hydrogen radicals are reduced. Thus, a high-quality silicon oxynitride layer 43 having high reliability can be formed. This procedure is not carried out in the first and second embodiments.

(79) The temperature of the silicon substrate 1 is then set at 750 C. or higher, and a 2.5-nm thick silicon oxide layer 44 is deposited on the silicon oxynitride layer 43 by HTO. By doing so, the tunnel insulating film 45 including the silicon oxide layer 42, the silicon oxynitride layer 43, and the silicon oxide layer 44 is formed as shown in FIGS. 18E and 18F. It should be noted here that, in the drawings illustrating the manufacturing procedures carried out after this procedure, the tunnel insulating film 45 having the three-layer structure consisting of the silicon oxide layer 42, the silicon oxynitride layer 43, and the silicon oxide layer 44 is shown as a single-layer tunnel insulating film 45.

(80) A 6-nm thick nitride film to be the charge storage film 46 such as a Si.sub.3N.sub.4 film is then deposited on the tunnel insulating film 45 by CVD, and a mask material 47 for device isolation is deposited by CVD. After that, etching is performed on the mask material 47, the nitride film (the charge storage film) 46, and the tunnel insulating film 45 in this order by RIE with the use of a resist mask (not shown). Etching is further performed on the exposed regions of the silicon substrate 1, so as to form device isolation grooves 48 of 100 nm in depth, as shown in FIGS. 19A and 19B.

(81) A silicon oxide film 49 for device isolation is then deposited on the entire surface, so as to completely fill the device isolation grooves 48. After that, the portion of the silicon oxide film 49 on the surface is removed by CMP, so that the surface is flattened. At this point, the mask material 47 is exposed (see FIGS. 19C and 19D).

(82) The exposed mask material 47 is selectively removed by etching, and the exposed surface portions of the silicon oxide film 49 are removed by etching with the use of a diluted hydrofluoric acid solution. After that, a 15-nm thick alumina layer 50a to be the interelectrode insulating film is formed on the entire surface by ALD. Due to the oxidizing agent used in the film formation by ALD, a very thin silicon oxide layer 50b is formed at the interface between the alumina layer 50a and the nitride film (the charge storage film) 46. As a result, a 16-nm thick interelectrode insulating film 50 having a two-layer structure consisting of the alumina layer 50a and the silicon oxide layer 50b is formed (see FIGS. 20A and 20B).

(83) A 100-nm thick conductive film 51 having a two-layer structure consisting of a polycrystalline silicon layer and a tungsten silicide layer is formed to be the control gate electrode on the interelectrode insulating film 50 in the same manner as in the first embodiment. Further, a mask material 52 for RIE is deposited by CVD. After that, etching is performed by RIE with the use of a resist mask (not shown) on the mask material 52, the conductive film 51, the interelectrode insulating film 50, the charge storage film 56, and the tunnel insulating film 55 in this order, so as to form the gate having a stacked structure. In this manner, the shape of the gate having the stacked structure is defined, and grooves 54 extending in the word-line direction (the direction in which the control gate electrode 51 extends) are formed on the side of this gate having the stacked structure (see FIGS. 20C and 20D).

(84) As shown in FIGS. 21A and 21B, a silicon oxide film 56 is then formed on the side faces and the upper face of the gate having the stacked structure by a thermal oxidation technique. After that, the source and drain regions 57a and 57b are formed by an ion injection technique. The region of the silicon substrate 1 located between the source region 57a and the drain region 57b is the channel region 58. Further, an interlayer insulating film 59 is formed to cover the entire surface by CVD. After that, a wiring layer and the likes are formed by known techniques, so as to complete the nonvolatile semiconductor memory (see FIGS. 21A and 21B).

(85) By carrying out a heat treatment in an oxidizing atmosphere after the amorphous silicon layer is nitrided in the above described manner, the reliability described in the first embodiment can be further increased. FIG. 22 shows the differences in SILC properties or reliability between a case where a heat treatment is carried out in an oxidizing atmosphere after the nitridation, and a case where the heat treatment is not carried out. As can be seen from FIG. 22, the SILC is reduced by carrying out the heat treatment in an oxidizing atmosphere after the amorphous silicon layer is nitrided. This is because SiNH in the silicon oxynitride layer 43 is oxidized, and the hydrogen radicals are reduced.

(86) In this manner, a high-quality stacked structure formed with a SiO.sub.2 layer, a SiON layer, and a SiO.sub.2 layer can be realized by carrying out a heat treatment in an oxidizing atmosphere after the amorphous silicon layer is nitrided.

(87) The silicon oxynitride layer 43 has a layer thickness of 1.5 nm to 2.5 nm, and nitrogen concentration of 20 atomic % to 47 atomic %. In other words, 10 atomic % to 30 atomic % of oxygen is contained in the silicon oxynitride layer 43, and at least one of the second nearest neighbor atoms of the silicon is nitrogen. This is because oxygen is added to the amorphous silicon layer. In the silicon oxide layer 42, a small amount of nitrogen is diffused when the amorphous silicon layer is nitrided. Therefore, an average of 10 atomic % of nitrogen is contained at a maximum.

(88) In this embodiment, radical nitridation or plasma nitridation is performed on the surface of the silicon oxide layer 42. However, to prevent nitrogen from penetrating through the silicon oxide layer 42 and nitriding the silicon substrate, it is not necessary to perform radical nitridation or plasma nitridation, and NH.sub.3 or NO may be used instead.

(89) Although an O.sub.2 gas is used when oxygen is added to the amorphous silicon layer in this embodiment, the gas used at the time of adding oxygen is not limited to an O.sub.2 gas, and it is possible to use any oxidizing gas such as NO, N.sub.2O, O.sub.3, O radicals, or O plasma. However, those gases differ from O.sub.2 in oxidation power. Therefore, when one of those gases is used, it is necessary to adjust the oxygen adding conditions in such a manner that the oxygen concentration in the silicon oxynitride layer 43 is in the range of 10 atomic % to 30 atomic %.

(90) Although a NH.sub.3 gas is used when the amorphous silicon layer is nitrided in this embodiment, the gas used at the time of nitridation is not limited to a NH.sub.3 gas, and it is possible to use any nitriding gas such as NO, N radicals, NH radicals, N.sub.2 radicals, N plasma, NH plasma, or N.sub.2 plasma.

(91) Although HTO is used in the process for forming the SiO.sub.2 layer in this embodiment, some other technique such as CVD or ALD may be used, as long as the SiO.sub.2 layer can be properly deposited.

(92) As described so far, this embodiment can provide a semiconductor device that has a high-quality tunnel insulating film in which defects are not easily formed. This semiconductor device experiences less leakage current.

Fourth Embodiment

(93) Referring now to FIGS. 23A to 26B, a method for manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention is described. FIGS. 23A, 23C, 23E, 24A, 24C, 25C, and 26A are cross-sectional views that are taken perpendicularly to the cross-sectional views of FIGS. 23B, 23D, 23F, 24B, 24D, 25B, 25D, and 26B.

(94) A semiconductor device in accordance with this embodiment is a MONOS nonvolatile semiconductor memory that includes memory cells arranged in a matrix fashion. As shown in FIGS. 26A and 26B, each of the memory cells includes: source and drain regions 77a and 77b that are formed at a distance from each other in a silicon substrate 1; a tunnel insulating film 65 that is formed on a region 78 of the silicon substrate 1 located between the source region 77a and the drain region 77b; a charge storage film 66 that is formed on the tunnel insulating film 65 and is made of an insulating material in which charges can be stored; an interelectrode insulating film 70 that is formed on the charge storage film 66; and a control gate electrode 71 that is formed on the interelectrode insulating film 70.

(95) Next, the method for manufacturing the semiconductor device in accordance with this embodiment is described. The manufacturing method in accordance with this embodiment differs from the manufacturing method in accordance with the third embodiment, in further including the procedure for oxidizing the tunnel insulating film including a silicon oxide layer, a silicon oxynitride layer, and a silicon oxide layer immediately after the formation of the silicon oxide layer on the silicon oxynitride layer.

(96) First, as shown in FIGS. 23A and 23B, the silicon substrate 1 doped with desired impurities is subjected to diluted HF treatment, so as to terminate the surface of the silicon substrate 1 with hydrogen. After that, the silicon substrate 1 is placed in the chamber of a film forming device. The chamber is filled only with a gas (such as a nitrogen gas) that does not react with or etch silicon during the manufacturing process. The temperature of the silicon substrate 1 is then heated to 700 C., so as to completely detach the hydrogen from the silicon substrate 1.

(97) The chamber is then filled with a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 3 Torr, for example. The surface of the silicon substrate 1 is heated to 1050 C., and is maintained at that temperature for ten seconds. In this manner, a silicon oxide layer 62a is formed on the silicon substrate 1, as shown in FIGS. 23C and 23D. Radical nitridation or plasma nitridation is then performed on the surface of the silicon oxide layer 62a. By doing so, a nitrogen-containing layer 62b is formed on the surface of the silicon oxide layer 62a, and nitrogen is introduced into the silicon oxide layer 62a so that the peak concentration in the profile becomes 10 atomic % or lower (see FIGS. 23C and 23D). In the same manner as in the second embodiment, a nitrogen-added silicon oxide layer 62 having a two-layer structure consisting of the silicon oxide layer 62a and the nitrogen-containing layer 62b is formed. Through this nitriding procedure, the hole injecting efficiency in each memory cell is increased. It should be noted here that, in the drawings illustrating the manufacturing procedures carried out after this nitriding procedure, the silicon oxide layer 62 having the two-layer structure consisting of the silicon oxide layer 62a and the nitrogen-containing layer 62b is shown as a single-layer silicon oxide layer 62.

(98) An amorphous silicon layer of 2 nm in thickness is then deposited on the silicon oxide layer 62 with the use of a disilane gas. It is preferable that the substrate temperature at this point is 550 C. or lower. The atmosphere at the time of deposition of the amorphous silicon layer may contain oxygen, NO, or N.sub.2O. If the atmosphere contains NO or N.sub.2O in this case, the resultant amorphous silicon layer contains a small amount of nitrogen.

(99) The temperature of the silicon substrate 1 is then set at 750 C. and the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 3 Torr, for example. These conditions are maintained for ten seconds. In this manner, a small amount of oxygen is added to the amorphous silicon layer, and an oxygen-added amorphous silicon layer is formed. As in the first embodiment, the oxidizing temperature at this point should preferably be 700 C. or higher, at which the hydrogen in the amorphous silicon layer is detached. However, the oxidizing temperature cannot be too high, and should preferably be 800 C. or lower. Furthermore, it is preferable to supply oxygen while the temperature is rising. Also, as in the first embodiment, the time required for the temperature to rise to a point between 700 C. and 800 C. should preferably be ten seconds or less. Ideally, while oxygen is being supplied, the heating-up time is ten seconds or less, and the oxidation time is ten seconds or less. After that, the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and a NH.sub.3 gas having a partial pressure of 0.03 Torr, for example. The surface of the silicon substrate 1 is then set at 750 C., and is maintained at that temperature for 400 seconds. In this manner, the amorphous silicon layer is nitrided to form a silicon oxynitride layer 63 (see FIGS. 23E and 23F). As described in the first embodiment, the silicon oxynitride layer 63 formed by the manufacturing method in accordance with this embodiment is a high-quality silicon oxynitride layer having few defects.

(100) The temperature of the silicon substrate 1 is then set at 800 C., and the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 0.03 Torr. These conditions are maintained for 100 seconds. As a result, the SiNH in the silicon oxynitride layer 63 is oxidized, and the hydrogen radicals are reduced. Thus, a high-quality silicon oxynitride layer 63 having high reliability can be formed.

(101) The temperature of the silicon substrate 1 is then set at 750 C. or higher, and a 2.5-nm thick silicon oxide layer 64 is deposited on the silicon oxynitride layer 63 by HTO. By doing so, the tunnel insulating film 65 including the silicon oxide layer 62, the silicon oxynitride layer 63, and the silicon oxide layer 64 is formed as shown in FIGS. 23E and 23F. The temperature of the silicon substrate 1 is then set at 950 C., and the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 760 Torr and an O.sub.2 gas having a partial pressure of 3 Torr. These conditions are maintained for one hour. By doing so, the small amount of hydrogen radicals in the tunnel insulating film 65 is oxidized, and the defects in the film are oxygen-terminated. Thus, the tunnel insulating film 65 can have higher quality and reliability. It should be noted here that, in the drawings illustrating the manufacturing procedures carried out after this procedure, the tunnel insulating film 65 having the three-layer structure consisting of the silicon oxide layer 62, the silicon oxynitride layer 63, and the silicon oxide layer 64 is shown as a single-layer tunnel insulating film 65.

(102) A 6-nm thick nitride film 66 to be the charge storage film such as a Si.sub.3N.sub.4 film is then deposited on the tunnel insulating film 65 by CVD, and a mask material 67 for device isolation is deposited by CVD. After that, etching is performed on the mask material 67, the nitride film (the charge storage film) 66, and the tunnel insulating film 65 in this order by RIE with the use of a resist mask (not shown). Etching is further performed on the exposed regions of the silicon substrate 1, so as to form device isolation grooves 68 of 100 nm in depth, as shown in FIGS. 24A and 24B.

(103) A silicon oxide film 69 for device isolation is then deposited on the entire surface, so as to completely fill the device isolation grooves 68. After that, the portion of the silicon oxide film 69 on the surface is removed by CMP, so that the surface is flattened. At this point, the mask material 67 is exposed (see FIGS. 24C and 24D).

(104) The exposed mask material 67 is selectively removed by etching, and the exposed surface portions of the silicon oxide film 69 are removed by etching with the use of a diluted hydrofluoric acid solution. After that, a 15-nm thick alumina layer 70a to be the interelectrode insulating film is formed on the entire surface by ALD. Due to the oxidizing agent used in the film formation by ALD, a very thin silicon oxide layer 70b is formed at the interface between the alumina layer 70a and the nitride film 66. As a result, a 16-nm thick interelectrode insulating film 70 having a two-layer structure consisting of the silicon oxide layer 70b and the alumina layer 70a is formed (see FIGS. 25A and 25B).

(105) A 100-nm thick conductive film 71 having a two-layer structure consisting of a polycrystalline silicon layer and a tungsten silicide layer is formed to be the control gate electrode on the interelectrode insulating film 70 in the same manner as in the first embodiment. Further, a mask material 72 for RIE is deposited by CVD. After that, etching is performed by RIE with the use of a resist mask (not shown) on the mask material 72, the conductive film 71, the interelectrode insulating film 70, the charge storage film 66, and the tunnel insulating film 65 in this order, so as to form the gate having a stacked structure. In this manner, the shape of the gate having the stacked structure is defined, and grooves 73 extending in the word-line direction (the direction in which the control gate electrode 71 extends) are formed on the side of this gate having the stacked structure (see FIGS. 25C and 25D).

(106) As shown in FIGS. 26A and 26B, a silicon oxide film 74 is then formed on the side faces and the upper face of the gate having the stacked structure by a thermal oxidation technique. After that, the source and drain regions 77a and 77b are formed by an ion injection technique. The region of the silicon substrate 1 located between the source region 77a and the drain region 77b is the channel region 78. Further, an interlayer insulating film 79 is formed to cover the entire surface by CVD (see FIGS. 26A and 26B). After that, a wiring layer and the likes are formed by known techniques, so as to complete the nonvolatile semiconductor memory.

(107) By carrying out a heat treatment in an oxidizing atmosphere after the oxide layer is deposited by HTO in the above described manner, the reliability described in the first embodiment and the third embodiment can be further increased. However, just carrying out a heat treatment will not suffice. To achieve desired characteristics, it is essential that a heat treatment is carried out in an oxidizing atmosphere under certain heat treatment conditions. Referring now to FIGS. 27A and 27B, the relationship between the heat treatment conditions in an oxidizing atmosphere and the reliability is described. FIGS. 27A and 27B show the SILC properties, with the oxygen partial pressure and the oxidation time being varied. More specifically, FIG. 27A shows the dependence of the electric field on the oxidation time observed when a leakage current of 10.sup.7 A/cm.sup.2 flows before and after the 0.01 C/cm.sup.2 injection. FIG. 276 shows the electric field at the time of the 0.01 C/cm.sup.2 injection. The oxidation temperature is 950 C. As can be seen from FIG. 27A, no improvements are observed in a N.sub.2 atmosphere, but the electric field, which is 1 MV/cm where the heat treatment is not carried out, is increased to approximately 5.5 MV/cm by the heat treatment in an oxidizing atmosphere. This indicates that the SILC properties are greatly improved by performing oxidation at 950 C. for ten minutes or longer, regardless of the pressure.

(108) This result confirms that the heat treatment in an oxidizing atmosphere for ten minutes or longer is essential in improving the reliability. As for the oxidation temperature, the same effects as above can be expected when the oxidation temperature is in the range of 900 C. to 950 C.

(109) However, excessive oxidation is not preferable to achieve high injection efficiency, even though the reliability becomes higher. FIG. 28 shows the relationship between the oxidation time and the electric field required to inject 0.01 A/cm.sup.2 of electrons. As can be seen from FIG. 28, the induced electric field is increased by performing oxidation for one hour or longer. Also, the induced electric field is increased, if the oxygen partial pressure is too high. This is because the oxygen concentration in the oxide layer is reduced by the oxidation, and the electron injection efficiency becomes lower. Therefore, oxidation performed for ten minutes or longer, but not longer than one hour, is essential in increasing the reliability while maintaining high injection efficiency.

(110) In this manner, a high-quality stacked structure formed with a SiO.sub.2 layer, a SiON layer, and a SiO.sub.2 layer can be realized by carrying out a heat treatment in an optimum oxidizing atmosphere after an oxide layer is deposited by HTO.

(111) The silicon oxynitride layer 63 has a layer thickness of 1.5 nm to 2.5 nm, and nitrogen concentration of 20 atomic % to 47 atomic %. In other words, 10 atomic % to 30 atomic % of oxygen is contained in the silicon oxynitride layer 63, and at least one of the second nearest neighbor atoms of the silicon is nitrogen. This is because oxygen is added to the amorphous silicon layer. In the silicon oxide layer 62, a small amount of nitrogen is diffused when the amorphous silicon layer is nitrided. Therefore, an average of 10 atomic % of nitrogen is contained at a maximum.

(112) In this embodiment, radical nitridation or plasma nitridation is performed on the surface of the silicon oxide layer. However, to prevent nitrogen from penetrating through the silicon oxide layer, it is not necessary to perform radical nitridation or plasma nitridation, and NH.sub.3 or NO may be used instead.

(113) Although an O.sub.2 gas is used when oxygen is added to the amorphous silicon layer in this embodiment, the gas used at the time of adding oxygen is not limited to an O.sub.2 gas, and it is possible to use any oxidizing gas such as NO, N.sub.2O, O.sub.3, O radicals, or O plasma. However, those gases differ from O.sub.2 in oxidation power. Therefore, when one of those gases is used, it is necessary to adjust the oxygen adding conditions in such a manner that the oxygen concentration in the silicon oxynitride layer is in the range of 10 atomic % to 30 atomic %.

(114) Although a NH.sub.3 gas is used when the amorphous silicon layer is nitrided in this embodiment, the gas used at the time of nitridation is not limited to a NH.sub.3 gas, and it is possible to use any nitriding gas such as NO, N radicals, NH radicals, N.sub.2 radicals, N plasma, NH plasma, or N.sub.2 plasma.

(115) Although HTO is used in the process for forming the SiO.sub.2 layer 64 in this embodiment, some other technique such as CVD or ALD may be used, as long as the SiO.sub.2 layer 64 can be properly deposited.

(116) In this embodiment, a heat treatment is carried out in an oxidizing atmosphere after the oxide layer 64 is deposited by HTO. This greatly reduces the hydrogen in the stacked structure formed with a SiO.sub.2 layer, a SION layer, and a SiO.sub.2 layer. Accordingly, as long as a heat treatment is carried out in an oxidizing atmosphere after the oxide layer 64 is deposited by HTO, the temperature at which oxygen is added to the amorphous silicon layer and the temperature at which nitridation is performed on the amorphous silicon layer may not be very high, and may be 400 C. or higher.

(117) As described so far, this embodiment can provide a semiconductor device that has a high-quality tunnel insulating film in which defects are not easily formed. This semiconductor device experiences less leakage current.

Fifth Embodiment

(118) Referring now to FIGS. 29A to 32B, a method for manufacturing a semiconductor device in accordance with a fifth embodiment of the present invention is described. FIGS. 29A, 29C, 29E, 30A, 30C, 31A, 31C, and 32A are cross-sectional views that are taken perpendicularly to the cross-sectional views of FIGS. 29B, 29D, 29F, 30B, 30D, 31B, 31D, and 32B.

(119) A semiconductor device in accordance with this embodiment is a MONOS nonvolatile semiconductor memory that includes memory cells arranged in a matrix fashion. As shown in FIGS. 32A and 32B, each of the memory cells includes: source and drain regions 97a and 97b that are formed at a distance from each other in a silicon substrate 1; a tunnel insulating film 85 that is formed on a region 98 of the silicon substrate 1 located between the source region 97a and the drain region 97b to be channel; a charge storage film 86 that is formed on the tunnel insulating film 85 and is made of an insulating material in which charges can be stored; an interelectrode insulating film 90 that is formed on the charge storage film 86; and a control gate electrode 91 that is formed on the interelectrode insulating film 90.

(120) Next, the method for manufacturing the semiconductor device in accordance with this embodiment is described. The manufacturing method in accordance with this embodiment differs from the manufacturing method in accordance with the fourth embodiment, in further including the procedure for introducing Ge into the silicon oxide layer formed below the silicon oxynitride layer, before nitriding the surface.

(121) First, as shown in FIGS. 29A and 29B, the silicon substrate 1 doped with desired impurities is subjected to diluted HF treatment, so as to terminate the surface of the silicon substrate 1 with hydrogen. After that, the silicon substrate 1 is placed in the chamber of a film forming device. The chamber is filled only with a gas (such as a nitrogen gas) that does not react with or etch silicon during the manufacturing process. The temperature of the silicon substrate 1 is then heated to 700 C., so as to completely detach the hydrogen from the silicon substrate 1.

(122) The chamber is then filled with a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 3 Torr, for example. The surface of the silicon substrate 1 is heated to 1050 C., and is maintained at that temperature for ten seconds. In this manner, a silicon oxide layer is formed on the silicon substrate 1, as shown in FIGS. 29C and 29D. After that, Ge is diffused in the silicon oxide layer by a technique such as implantation or a heat treatment, so as to form a silicon oxide layer 82a having a Ge distribution with a peak of 110.sup.13 cm.sup.2 in the silicon oxide layer; The atmosphere in the chamber is then changed to an O.sub.2 gas having a partial pressure of 3 Torr, for example, and the surface of the silicon substrate 1 is heated to 750 C. and is maintained at that temperature for ten seconds. By doing so, the Ge in the silicon oxide layer 82a is oxidized, and a Ge level having an energy level approximately 0.7 eV below the conduction band of SiO.sub.2 is formed in the silicon oxide layer 82a. Radical nitridation or plasma nitridation is then performed on the surface of the silicon oxide layer 82a. By doing so, a nitrogen-containing layer 82b is formed on the surface of the silicon oxide layer 82a, and 10 atomic % or less of nitrogen is introduced into the silicon oxide layer 82a. Through this nitriding procedure, the hole injecting efficiency in each memory cell is increased. It should be noted here that, in the drawings illustrating the manufacturing procedures carried out after this procedure, the silicon oxide layer 82 having the two-layer structure consisting of the silicon oxide layer 82a and the nitrogen-containing layer 82b is shown as a single-layer silicon oxide layer 82.

(123) An amorphous silicon layer of 2 nm in thickness is then deposited on the silicon oxide layer 82 with the use of a disilane gas. It is preferable that the temperature of the silicon substrate 1 at this point is 550 C. or lower. The temperature of the silicon substrate 1 is then set at 750 C., and the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2 gas having a partial pressure of 3 Torr, for example. These conditions are maintained for ten seconds. In this manner, a small amount of oxygen is added to the amorphous silicon layer, and an oxygen-added amorphous silicon layer is formed. The oxidizing temperature at this point should preferably be 700 C. or higher, at which the hydrogen in the amorphous silicon layer is detached. However, the oxidizing temperature cannot be too high, and should preferably be 800 C. or lower. Furthermore, it is preferable to supply oxygen while the temperature is rising. Also, the time required for the temperature to rise to a point between 700 C. and 800 C. should preferably be ten seconds or less. Ideally, while oxygen is being supplied, the heating-up time is ten seconds or less, and the oxidation time is ten seconds or less. After that, the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and a NH.sub.3 gas having a partial pressure of 0.03 Torr, for example. The surface of the silicon substrate 1 is then set at 750 C., and is maintained at that temperature for 400 seconds. In this manner, the amorphous silicon layer is nitrided to form a silicon oxynitride layer 83 (see FIGS. 29E and 29F). The temperature of the silicon substrate 1 is then set at 800 C., and the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 30 Torr and an O.sub.2, gas having a partial pressure of 0.03 Torr. These conditions are maintained for 100 seconds. As a result, the SiNH in the silicon oxynitride layer 83 is oxidized, and the hydrogen radicals are reduced. Thus, a high-quality silicon oxynitride layer 83 having high reliability can be formed.

(124) The temperature of the silicon substrate 1 is then set at 750 C. or higher, and a 2.5-nm thick silicon oxide layer 84 is deposited by HTO. By doing so, the tunnel insulating film 85 including the silicon oxide layer 82, the silicon oxynitride layer 83, and the silicon oxide layer 84 is formed as shown in FIGS. 29E and 29F. The temperature of the silicon substrate 1 is then set at 950 C., and the atmosphere in the chamber is changed to a N.sub.2 gas having a partial pressure of 760 Torr and an O.sub.2 gas having a partial pressure of 3 Torr. These conditions are maintained for one hour. By doing so, the small amount of hydrogen radicals in the tunnel insulating film 85 is oxidized, and the defects in the tunnel insulating film 85 are oxygen-terminated. Thus, the tunnel insulating film 85 can have higher quality and reliability.

(125) A 6-nm thick nitride film to be the charge storage film 86 is then deposited on the tunnel insulating film 85 by CVD, and a mask material 87 for device isolation is deposited by CVD. After that, etching is performed on the mask material 87, the nitride film (the charge storage film) 86, and the tunnel insulating film 85 in this order by RIE with the use of a resist mask (not shown). Etching is further performed on the exposed regions of the silicon substrate 1, so as to form device isolation grooves 88 of 100 nm in depth, as shown in FIGS. 30A and 30B.

(126) A silicon oxide film 89 for device isolation is then deposited on the entire surface, so as to completely fill the device isolation grooves 88. After that, the portion of the silicon oxide film 89 on the surface is removed by CMP, so that the surface is flattened. At this point, the mask material 87 is exposed (see FIGS. 30C and 30D).

(127) The exposed mask material 87 is selectively removed by etching, and the exposed surface portions of the silicon oxide film 89 are removed by etching with the use of a diluted hydrofluoric acid solution. After that, a 15-nm thick alumina layer 90a to be the interelectrode insulating film is formed on the entire surface by ALD. Due to the oxidizing agent used in the film formation by ALD, a very thin silicon oxide layer 90b is formed at the interface between the alumina layer 90a and the charge storage film 86. As a result, a 16-nm thick interelectrode insulating film 90 having a two-layer structure consisting of the alumina layer 90a and the silicon oxide layer 90b is formed (see FIGS. 31A and 31B).

(128) A 100-nm thick conductive film 91 having a two-layer structure consisting of a polycrystalline silicon layer and a tungsten silicide layer is formed to be the control gate electrode in the same manner as in the first embodiment. Further, a mask material 92 for RIE is deposited by CVD. After that, etching is performed by RIE with the use of a resist mask (not shown) on the mask material 92, the conductive film 91, the interelectrode insulating film 90, the charge storage film 86, and the tunnel insulating film 85 in this order, so as to form the gate having a stacked structure. In this manner, the shape of the gate having the stacked structure is defined, and grooves 94 extending in the word-line direction are formed on the side of this gate having the stacked structure (see FIGS. 31C and 31D).

(129) As shown in FIGS. 32A and 32B, a silicon oxide film 96 is then formed on the side faces and the upper face of the gate having the stacked structure by a thermal oxidation technique, After that, the source and drain regions 97a and 97b are formed by an ion injection technique. The region of the silicon substrate 1 located between the source region 97a and the drain region 97b is the channel region 98. Further, an interlayer insulating film 99 is formed to cover the entire surface by CVD (see FIGS. 32A and 32B). After that, a wiring layer and the likes are formed by known techniques, so as to complete the nonvolatile semiconductor memory.

(130) Referring now to FIGS. 33 and 34, the effect of adding Ge to the silicon oxide layer 82 is described. FIG. 33 shows the variations in the electric field required to generate 0.1 A/cm.sup.2 of leakage current, with respect to a case where Ge is added to the silicon oxide layer, and a case where Ge is not added. As can be seen from FIG. 33, the induced electric field is reduced by 1 MV/cm or more through the Ge addition. This is because, as an electric field is induced, the energy level of the Ge level in the SiO.sub.2 layer 82 becomes lower than the Fermi level on the substrate side, and the electron tunneling probability becomes higher. In this manner, a high-quality stacked structure that has excellent electron injection efficiency and is formed with a SiO.sub.2 layer, a SiON layer, and a SiO.sub.2 layer can be realized by adding Ge to the silicon oxide layer 82.

(131) The silicon oxynitride layer 83 has a layer thickness of 1.5 nm to 2.5 nm, and nitrogen concentration of 20 atomic % to 47 atomic %. In other words, 10 atomic % to 30 atomic % of oxygen is contained in the silicon oxynitride layer 83, and at least one of the second nearest neighbor atoms of the silicon is nitrogen. This is because oxygen is added to the amorphous silicon layer. In the silicon oxide layer 82, a small amount of nitrogen is diffused when the amorphous silicon layer is nitrided. Therefore, an average of 10 atomic % of nitrogen is contained at a maximum.

(132) In this embodiment, radical nitridation or plasma nitridation is performed on the surface of the silicon oxide layer. However, to prevent nitrogen from penetrating through the silicon oxide layer, it is not necessary to perform radical nitridation or plasma nitridation, and NH.sub.3 or NO may be used instead.

(133) Although an O.sub.2 gas is used when oxygen is added to the amorphous silicon layer in this embodiment, the gas used at the time of adding oxygen is not limited to an O.sub.2 gas, and it is possible to use any oxidizing gas such as NO, N.sub.2O, O.sub.3, O radicals, or O plasma. However, those gases differ from O.sub.2 in oxidation power. Therefore, when one of those gases is used, it is necessary to adjust the oxygen adding conditions in such a manner that the oxygen concentration in the silicon oxynitride layer 83 is in the range of 10 atomic % to 30 atomic %.

(134) Although a NH.sub.3 gas is used when the amorphous silicon layer is nitrided in this embodiment, the gas used at the time of nitridation is not limited to a NH.sub.3 gas, and it is possible to use any nitriding gas such as NO, N radicals, NH radicals, N.sub.2 radicals, N plasma, NH plasma, or N.sub.2 plasma.

(135) Although HTO is used in the process for forming the silicon oxide layer 84 in this embodiment, some other technique such as CVD or ALD may be used, as long as the silicon oxide layer 84 can be properly deposited.

(136) In this embodiment, a heat treatment is carried out in an oxidizing atmosphere after the oxide layer is deposited by HTO.

(137) This greatly reduces the hydrogen in the stacked structure formed with a SiO.sub.2 layer, a SiON layer, and a SiO.sub.2 layer. Accordingly, as long as a heat treatment is carried out in an oxidizing atmosphere after the oxide layer is deposited by HTO, the temperature at which oxygen is added to the amorphous silicon layer and the temperature at which nitridation is performed on the amorphous silicon layer may not be very high, and may be 400 C. or higher.

(138) As described so far, this embodiment can provide a semiconductor device that has a high-quality tunnel insulating film in which defects are not easily formed. This semiconductor device experiences less leakage current.

(139) In the first to fifth embodiments, it is preferable that the amorphous silicon layer is thinner than 2.5 nm. If the layer thickness of the amorphous silicon layer is 2.5 nm or greater, the following two adverse effects appear. 1) Sufficient nitridation cannot be performed on the amorphous silicon in the later nitriding procedure, and Si atoms that are not bonded to nitrogen remains as defects in the film. As a result, the characteristics of the insulating film are degraded. 2) Since the Si defects are easily oxidized in the later oxidizing procedure, the oxygen concentration in the oxynitride layer, and the high injection efficiency as a feature of the insulating film of the SiO.sub.2/SiON/SiO.sub.2 stacked structure becomes lower.

(140) FIG. 35 shows the C-V characteristics observed in a case where samples each formed by depositing an amorphous silicon layer on a SiO.sub.2 layer on a silicon substrate are prepared, oxygen is added to each of the samples at 750 C. for ten seconds, and nitridation is performed on each of the samples until nitrogen penetrates through the SiO.sub.2 layer. In a case where the layer thickness of the amorphous silicon layer is 2.5 nm, the interface state is formed as the interface between the SiO.sub.2 layer and the silicon substrate is nitrided, but hysteresis is not observed in the C-V characteristics. This indicates that the amorphous silicon layer of 2.5 nm in layer thickness is nitrided, with only a very small number of defects being formed.

(141) In a case where the layer thickness of the amorphous silicon layer is 15 nm, not only the interface state is formed, but also large hysteresis occurs in the C-V characteristics. The existence of hysteresis means that a Si structure is locally formed in the nitride layer (or a Si bandgap exists locally in the bandgap of the nitride layer), and the Si structure functions as the charge storage source. This indicates that, if the layer thickness of the amorphous silicon layer is larger than 2.5 nm, nitrogen is diffused into the base layer while the amorphous silicon layer remains not completely nitrided.

(142) Accordingly, it is preferable that the layer thickness of the amorphous silicon layer is smaller than 2.5 nm, as shown in each embodiment of the present invention.

(143) In the tunnel insulating film having the SiO.sub.2/SiON/SiO.sub.2 stacked structure of each embodiment of the present invention, nitrogen shows the following distribution characteristics. As shown in FIG. 36, there is a continuous region having nitrogen concentration of 20 atomic % or higher in a region 5 nm or less from the surface of the SiO.sub.2/SiON/SiO.sub.2 stacked structure. This continuous region has a physical film thickness of 1 nm or more. In the lowermost SiO.sub.2 layer, a nitrogen distribution with concentration of 10 atomic % or less exists between the lower interface and the upper interface. Here, it is preferable that the nitrogen concentration in the lowermost SiO.sub.2 layer is 10 atomic % or less, because the leakage current on the low-and-medium field side increases as the nitrogen concentration becomes higher, as shown in FIG. 37.

(144) In the first to fifth embodiments, each semiconductor device is a nonvolatile semiconductor memory. However, the tunnel insulating film having the three-layer stacked structure formed with a silicon oxide layer, a silicon oxynitride layer, and a silicon oxide layer may be used as the gate insulating film of a MOS transistor. The tunnel insulating film may also be used as the interelectrode insulating film in each of the first to fifth embodiments. In any of those cases, a layer made of a high-k material (such as Hf, La, or a silicate of Hf or La) may be used in place of the silicon oxide layer as the insulating layer serving as the base layer on which the amorphous silicon layer to be the silicon oxynitride layer is formed.

(145) As described so far, each embodiment of the present invention can provide a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. Each embodiment can also provide a method for manufacturing such a semiconductor device.

(146) Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concepts as defined by the appended claims and their equivalents.