Method for producing a laterally structured phosphor layer and optoelectronic component comprising such a phosphor layer

Abstract

A method for producing a laterally structured phosphor layer and an optoelectronic component comprising such a phosphor layer are disclosed. In an embodiment the method includes providing a carrier having a first electrically conductive layer at a carrier top side, applying an insulation layer to the first electrically conductive layer and a second electrically conductive layer to the insulation layer, etching the second electrically conductive layer and the insulation layer, wherein the first electrically conductive layer is maintained as a continuous layer. The method further includes applying a voltage to the first electrically conductive layer and electrophoretically coating the first electrically conductive layer with a first material, and applying a voltage to the second electrically conductive layer and electrophoretically coating the second electrically conductive layer with a second material.

Claims

1. A method for producing a laterally patterned layer, the method comprising: providing a carrier with a first electrically conductive layer on a carrier top; applying an insulation layer onto the first electrically conductive layer; applying a second electrically conductive layer onto the insulation layer; applying and patterning an etching mask onto the second electrically conductive layer; etching the second electrically conductive layer and the insulation layer, wherein the first electrically conductive layer is retained as a continuous layer; applying a first voltage to the first electrically conductive layer; electrophoretically coating the first electrically conductive layer with a first material; applying a second voltage to the second electrically conductive layer; and electrophoretically coating the second electrically conductive layer with a second material.

2. The method according to claim 1, wherein the laterally patterned layer is a luminescent material plate, wherein the first material is a luminescent material or a luminescent material mixture, wherein the second material contains or is a material which reflects or absorbs visible light, and wherein, after etching, the second electrically conductive layer forms a grid when viewed in plan view such that the first electrically conductive layer, when viewed in plan view, is subdivided into a plurality of regions surrounded in the manner of a frame.

3. The method according to claim 1, wherein the first and the second materials are, in each case, deposited as particles, and wherein an average particle diameter of the particles of the second material is at least by a factor of 3 smaller than an average particle diameter of the particles of the first material.

4. The method according to claim 1, wherein, after etching, the first and the second electrically conductive layers taken together, when viewed in plan view, completely cover the carrier top.

5. The method according to claim 1, wherein the second electrically conductive layer and the insulation layer are selectively wet chemically etchable relative to the first electrically conductive layer.

6. The method according to claim 1, wherein, after coating, a matrix material is placed onto the first and second materials such that the laterally patterned layer is a single, contiguous plate, and wherein the matrix material contains at least one of a silicone, a silicone/epoxy hybrid material, a polysilazane and a parylene.

7. The method according to claim 6, wherein a third material in form of particles is added to the matrix material and the third material is a luminescent material or a luminescent material mixture.

8. The method according to claim 1, wherein the carrier is electrically insulating.

9. The method according to claim 1, wherein the first electrically conductive layer comprises a transparent conductive oxide and has a thickness between 50 nm and 400 nm inclusive, wherein the insulation layer is formed from a silicon oxide or a silicon nitride and has a thickness between 150 nm and 800 nm inclusive, wherein the second electrically conductive layer comprises a metallic layer with Ti, W, Al and/or Ca and has a thickness between 50 nm and 500 nm inclusive, wherein the first material is a luminescent material and has an average particle diameter of between 7 m and 13 m inclusive, wherein the second material has an average particle diameter of between 100 nm and 500 nm inclusive and is a titanium oxide, silicon oxide, aluminum oxide, carbon black or graphite, and wherein a thickness of a finished luminescent material plate is between 20 m and 150 m inclusive.

10. The method according to claim 1, wherein the first electrically conductive layer comprises a transparent conductive oxide and has a thickness between 50 nm and 400 nm inclusive.

11. The method according to claim 1, wherein the insulation layer is formed from a silicon oxide or a silicon nitride and has a thickness between 150 nm and 800 nm inclusive.

12. The method according to claim 1, wherein the second electrically conductive layer comprises a metallic layer with Ti, W, Al and/or Ca and has a thickness between 50 nm and 500 nm inclusive.

13. The method according to claim 1, wherein the first material is a luminescent material and has an average particle diameter of between 7 m and 13 m inclusive.

14. The method according to claim 1, wherein the second material has an average particle diameter of between 100 nm and 500 nm inclusive and is a titanium oxide, silicon oxide, aluminum oxide, carbon black or graphite.

15. The method according to claim 1, wherein the thickness of the finished luminescent material plate is between 20 m and 150 m inclusive.

16. The method according to claim 1, wherein the method is carried out in the stated order.

17. The method according to claim 1, further comprising, after coating with the first and the second materials, removing the carrier from the laterally patterned layer, wherein at least one of the first electrically conductive layer, the second electrically conductive layer and the insulation layer remain partially or completely on the laterally patterned layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) A method described herein and an optoelectronic semiconductor component described herein will be explained in greater detail below with reference to the drawings and with the aid of exemplary embodiments. Elements which are the same in the individual figures are indicated with the same reference numerals. The relationships between the elements are not shown to scale, however, but rather individual elements may be shown exaggeratedly large to assist in understanding.

(2) In the drawings:

(3) FIG. 1A-1C show several method steps for depositing layer(s) disposed on a carrier,

(4) FIG. 1D-IF show patterning the layer structure on the carrier,

(5) FIGS. 1G-1H show depositing first and second particles materials on the layers on the carrier,

(6) FIG. 1I-1J show forming a matrix material

(7) FIG. 2 shows a plan view of a patterned, electrically conductive layers structure disposed on a carrier, and

(8) FIG. 3 is a schematic sectional representation of an optoelectronic semiconductor component described herein.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(9) FIG. 1A-1J illustrate a production method for a laterally patterned layer. The finished laterally patterned layer is particularly preferably a luminescent material plate 1.

(10) According to FIG. 1A, a carrier 2 is provided with a carrier top 20. The carrier 2 is, for example, a sapphire wafer. Other electrically insulating materials may, however, likewise be used. A first electrically conductive layer 21 is applied onto the carrier top 20, for example by means of sputtering or gas-phase deposition. The first electrically conductive layer 21 is for example formed from ZnO and has a thickness of approximately 150 nm.

(11) Alternatively, it is also possible to use an electrically conductive substrate 2. In this case, the first electrically conductive layer 21 is part of the carrier 2 and the carrier top 20.

(12) FIG. 1B illustrates deposition of an insulation layer 23 onto the first electrically conductive layer 21. The insulation layer 23 is electrically insulating. For example, the insulation layer 23 is formed from Si.sub.3N.sub.4. The thickness of the insulation layer 23 is for example approximately 350 nm.

(13) FIG. 1C shows continuous deposition of a second electrically conductive layer 22 onto the insulation layer 23. For example, the second electrically conductive layer 22 is formed from Ti/TiW:N. The thickness of the second electrically conductive layer 22 amounts for example to approximately 300 nm.

(14) Layers 21, 23 and 22 follow one another in direct succession. The total thickness of layers 21, 23 and 22 is in particular at most 2 m or 1.5 m or 1 m. Layers 21, 23 and/or 22 may alternatively or additionally be patterned by laser machining or by mechanical scribing.

(15) As shown in FIG. 1D, a photoresist layer 30 is applied onto layers 21, 23 and 22. The photoresist layer 30 is photolithographically patterned in such a manner that a mask 3 is obtained which partially covers layers 21, 23 and 22. The mask 3 is illustrated schematically in FIG. 1E.

(16) FIG. 1F shows patterning of the insulation layer 23 and the second electrically conductive layer 22 by etching with the assistance of the mask 3. The resultant pattern of layers 22 and 23 here preferably corresponds to the pattern of the mask 3. The etching is for example wet chemical etching with buffered hydrofluoric acid, BOE for short, or dry chemical etching for instance with fluorine plasma. Layers 22 and 23 are here preferably selectively etchable relative to the first electrically conductive layer 21.

(17) An extent of layers 22 and 23 in a direction parallel to the carrier top 20 is here preferably greater at least by a factor of 5 or 10 or 50 than the total thickness of layers 22 and 23. An average extent of the exposed regions of the first conductive layer 21, in a direction parallel to the carrier top 20, is preferably at least 20 m or 50 m or 100 m. The average extent of the exposed regions of the first electrically conductive layer 21 in particular exceeds the average extent of the remaining regions of layers 22 and 23 at least by a factor of 5 or 10.

(18) The resultant pattern of the electrically conductive layers 21 and 22 from FIG. 1F is shown in the schematic plan view according to FIG. 2. The second electrically conductive layer 22 forms a grid in which island-like, for example rectangular, regions of the first electrically conductive layer 21 are exposed. Both electrically conductive layers 21 and 22 are preferably in each case contiguous and/or one-piece layers.

(19) It is optionally possible for a greater distance to be provided between some of the exposed regions of the first electrically conductive layer 21. A separation line S may be provided in such regions for subdividing the laterally patterned coating into individual luminescent material plates 1.

(20) According to FIG. 1G, a voltage U is applied to the first electrically conductive layer 21. Particles of a first material 4 are deposited onto exposed regions of the first electrically conductive layer 21 by electrophoresis, in particular in an electrophoresis dip bath. The first material 4 is preferably luminescent material particles.

(21) Unlike in the illustration, the average diameter of the luminescent material particles 4 is preferably distinctly greater than the height of the insulation layer 23 together with the second electrically conductive layer 22. A lateral extent, in a direction parallel to the carrier top 20, of the remaining regions of the insulation layer 23 and the second electrically conductive layer 22 is preferably likewise greater than or equal to the average diameter of the luminescent material particles 4.

(22) According to FIG. 1H, the voltage U is then applied to the second electrically conductive layer 22 and a second material 5 is selectively deposited over the second electrically conductive layer 22. The second material 5 is for example titanium dioxide particles. The particles of the second material 5 preferably have a smaller diameter than the particles of the first material 4.

(23) Unlike in the illustration, the second material 5 may also be deposited before the first material 4 is deposited. It is furthermore optionally possible for a thin, continuous layer of the second material 5 to be deposited on a side of the first material 4 remote from the carrier 2.

(24) According to FIG. 1I, a matrix material 6 is applied onto the first material 4 and onto the second material 5. The regions having the first and the second materials 4 and 5 are schematically divided from one another in FIG. 1I by dashed lines. Unlike in the illustration, it is possible for a side of the luminescent material plate 1 remote from the carrier 2 to have patterning and not a smooth top.

(25) In FIG. 1J, the carrier 2 has been removed from the luminescent material plate 1. The first electrically conductive layer 21 has preferably also been completely removed from the matrix material 6 having materials 4 and 5, unlike in the illustration.

(26) Optionally, however, it is also possible for the insulation layer 23 and/or the second electrically conductive layer 22 partially or completely to remain on the luminescent material plate 1, see FIG. 1J. Preferably, however, the materials of layers 22 and 23 are removed from the luminescent material plate 1. This removal is effected, for example, by selective etching. If layers 22 and 23 are removed, it is possible for a grid pattern to remain on the bottom of the luminescent material plate 1. This grid pattern then corresponds to a negative of the grid pattern, as shown in FIG. 2.

(27) FIG. 3 shows an optoelectronic semiconductor component 10. The semiconductor component 10 comprises a luminescent material plate 1, in particular as produced in connection with FIG. 1. To simplify the illustration, the grid-like pattern on the luminescent material plate 1 resulting from the removal of layers 22 and 23 is not shown.

(28) The semiconductor component 10 furthermore comprises a light-emitting diode chip 7. The light-emitting diode chip 7 comprises a semiconductor layer sequence 71 which has been patterned, for instance by etching, into individual pixels 70. The pixels 70 are located on a common chip carrier 72, which preferably also contains electrical interconnection of the pixels 70. The light-emitting diode chip 7 is, for example, a chip as is described in connection with documents US 2011/0241031 A1 or DE 10 2012 109 460 A1. The disclosure content of these documents is hereby included by reference.

(29) A distance D between adjacent pixels 70 is for example approximately 5 m and corresponds to the width of the regions of the luminescent material plate 1 having the second material 5. A interlayer 23 is preferably located between adjacent pixels 70. The pixels can be optically isolated from one another within the semiconductor layer sequence 71 by way of the interlayer 23.

(30) The luminescent material plate 1 is mounted on the semiconductor layer sequence 21, for example by way of an adhesive layer 8. The adhesive layer 8 is preferably thin, preferably with a thickness of at most 5 m or at most 1 m. The adhesive layer 8 preferably consists of at least one transparent, radiation-transmissive material. Alternatively, it is possible for the luminescent material plate 1 to be applied directly onto the semiconductor layer sequence 21, for example in a partially crosslinked state with subsequent complete crosslinking to form a bond.

(31) The regions having the first material 4 effect in particular partial wavelength conversion of radiation from the semiconductor layer sequence 71 into radiation of a different, further wavelength. The pixels 70 are optically isolated from one another by way of the regions having the second material 5, such that optical crosstalk between adjacent pixels is greatly reduced or prevented at least within the luminescent material plate 1.

(32) The invention described herein is not restricted by the description given with reference to the exemplary embodiments. Rather, the invention encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the claims or exemplary embodiments.