Digital delay unit and signal delay circuit

Abstract

An example of the invention provides a digital delay unit that is made up of a plurality of NAND gates. The digital delay unit includes a first delay path and a second delay path. The first delay path is coupled between a first input terminal and an output terminal to provide a basic time delay which is caused by one NAND gate. The second delay path is coupled between a second input terminal and the output terminal to provide at least three basic time delays.

Claims

1. A digital delay unit, comprising: an inverter to receive a first signal; a first signal input terminal coupled to a first input terminal of a first NAND gate; the first NAND gate having a second input terminal coupled to an output terminal of the inverter; a second NAND gate, having a first input terminal coupled to an output terminal of the first NAND gate; a third NAND gate, having a first input terminal coupled to an output terminal of the second NAND gate, and a second input terminal coupled to a second signal input terminal; and a fourth NAND gate having a first input terminal to receive the first signal, a second input terminal to receive a second signal, and an output terminal coupled to a second input terminal of the second NAND gate, wherein when the first signal input terminal receives an input signal that is a clock signal, a logic level of the first signal is set to be 0 and the logic level of the second signal input terminal is set to be 1, and when the input signal is sent to the digital delay unit via the second signal input terminal, the logic level of the first signal is set to be 1, and a logic level of the second signal is set to be 1.

2. A time-delay circuit, comprising: a delay control circuit to generate a control signal according to an input signal and a reference signal, wherein the input signal is a clock signal; and a digital delay circuit to receive the input signal, delay the input signal according to the control signal to generate a delayed input signal, wherein a minimum time delay of the digital delay circuit is a time delay of a NAND gate, wherein: the digital delay circuit comprises at least one digital delay unit; and the digital delay unit comprises: an inverter to receive a first signal; a first signal input terminal coupled to a first input terminal of a first NAND gate; the first NAND gate having a second input terminal coupled to an output terminal of the inverter; a second NAND gate, having a first input terminal coupled to an output terminal of the first NAND gate; a third NAND gate, having a first input terminal coupled to an output terminal of the second NAND gate, and a second input terminal coupled to a second signal input terminal; and a fourth NAND gate having a first input terminal to receive the first signal, a second input terminal to receive a second signal, and an output terminal coupled to a second input terminal of the second NAND gate, wherein when the input signal is sent to the digital delay unit via the first signal input terminal, a logic level of the first signal is set to be 0 and the logic level of the second signal input terminal is set to be 1, and when the input signal is sent to the digital delay unit via the second signal input terminal, the logic level of the first signal is set to be 1, and a logic level of the second signal is set to be 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

(2) FIG. 1A is a schematic diagram of a conventional digital delay line.

(3) FIG. 1B is a schematic diagram of another conventional digital delay line.

(4) FIG. 2 is a schematic diagram of a digital delay unit according to an embodiment of the invention.

(5) FIG. 3 is a schematic diagram of a digital delay line according to an embodiment of the invention.

(6) FIG. 4 is a schematic diagram of a digital delay line according to another embodiment of the invention.

(7) FIG. 5 is a schematic diagram of a signal delay circuit according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

(8) The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

(9) FIG. 2 is a schematic diagram of a digital delay unit according to an embodiment of the invention. The digital delay unit 20 of FIG. 2 can be applied in a digital delay line, the clock signal can be injected in the clock input terminal A or B, and a delayed clock signal is output by the out terminal Y. The digital delay unit 20 comprises a first NAND gate 21, a second NAND gate 22, a third NAND gate 23 and a fourth NAND gate 24. The first NAND gate 21 has a first input terminal coupled to the clock input terminal A and a second input terminal coupled to an output terminal of the inverter 25, wherein the inverter 25 receives a signal T. The fourth NAND gate 24 has a first input terminal to receive a signal P and a second input terminal to receive a signal T. The second NAND gate 22 has two input terminals coupled to an output terminal of the first NAND gate 21 and an output terminal of the fourth NAND gate 24 respectively. The third NAND gate 23 has two input terminals coupled to the clock input terminal B and the output terminal of the second NAND gate 22, respectively.

(10) When a first clock signal is injected in the clock input terminal A, a logic level of signal T is set to be 0 to ensure the second NAND gate 22 outputs the delayed first clock signal. The logic level of the clock input terminal B is set to be 1 to ensure the third NAND gate 23 outputs the delayed first clock signal. When the first clock signal in injected in the clock input terminal B, the logic level of signal T is set to be 1 and the logic level of the output terminal of the second NAND gate 22 is 1 to ensure the third NAND gate 23 outputs the delayed first clock signal. The operation of the digital delay unit 20 requires an extra control signal T, and signals for controlling the logic level of clock input terminal A or B.

(11) Assuming a delay time of each NAND gate is T.sub.d, the digital delay unit 20 provides two different phase delay times T.sub.d and 3T.sub.d. The digital delay unit 20 has a first delay path and a second delay path. The first delay path starts at the clock input terminal B and ends at the output terminal Y. The second delay path starts at the clock input terminal A and ends at the output terminal Y. When a clock signal passes through the first delay path, the clock signal is only delayed by the third NAND gate 23. When a clock signal passes through the second delay path, the clock signal is delayed by the first NAND gate 21, the second NAND gate 22, and the third NAND gate 23.

(12) If the clock signal needs to be delayed for the phase delay time T.sub.d, the clock signal is injected in the clock input terminal B. A phase delay time T.sub.d, caused by the first delay path, between the original clock signal and the clock signal output by the output terminal Y is generated. If the clock signal needs to be delayed for the phase delay time 3T.sub.d, the clock signal is injected in the clock input terminal A. A phase delay time 3T.sub.d, caused by the second delay path, between the original clock signal and the clock signal output by the output terminal Y is generated accordingly.

(13) Compared with the conventional digital delay line, the proposed digital delay line is able to provide a minimum phase delay time caused by only one NAND gate, and it significantly increases the operation frequency range of circuits.

(14) FIG. 3 is a schematic diagram of a digital delay line according to an embodiment of the invention. The digital delay line 30 comprises a first digital delay unit 31 and a second digital delay unit 32. Assuming that the delay time of each NAND gate is T.sub.d, the first digital delay unit 31 provides two different phase delay times T.sub.d and 3T.sub.d. The second digital delay unit 32 comprises a number of NAND gates, wherein the number is adjustable. In one embodiment, the number of NAND gates is determined based on a phase delay time required by the input clock signal.

(15) In FIG. 3, the input clock signal is output from the terminal Y, however, any output terminal of the NAND gate can serve as an output terminal to output the delayed signal according to a control circuit and corresponding control signal. For example, if the input clock signal needs to be delayed by delay time 2T.sub.d, the control circuit controls the second delay unit 32 to cause the delayed clock signal to be output by the output terminal of the NAND gate 321. Therefore, the phase delay between the input clock signal and the output clock signal is 2T.sub.d.

(16) Furthermore, each NAND gate of the second digital delay unit 32 comprises two input terminals, wherein one input terminal is coupled to an output terminal of a previous stage of the NAND gate, and another input terminal continuously receives a logic 1 signal.

(17) Moreover, assuming the digital delay line 30 is a 16-stage digital delay line, the minimum number of NAND gates is 19 according to the schematic structure of the proposed digital delay line 30. The proposed digital delay line 30 can reduce the number of NAND gates and the layout area of the digital delay line 30.

(18) FIG. 4 is a schematic diagram of a digital delay line according to another embodiment of the invention. The digital delay line 30 comprises a first digital delay unit 41 and a second digital delay unit 42, wherein a plurality of digital delay units are coupled between the first digital delay unit 41 and the second digital delay unit 42. In the embodiment, the details of the circuitry of the second digital delay unit 42 is the same as the circuits in the first digital delay unit 41, or the other digital delay units, and the NAND gates used in each digital delay unit are the same. In this embodiment, each digital delay unit provides a delay time T.sub.d caused by one NAND gate, and the total delay time for an input signal is determined by a control signal. In the embodiment, the signal to be delayed is input to the clock input terminal B, and a logic level of signal T is set to be 1.

(19) The output signal of the digital delay line 40 is transmitted to an input terminal of the multiplexer 43 and an inverter 44. Another input terminal of the multiplexer 43 is coupled to the output terminal of the inverter 44. Since the signal passing through each digital delay unit is only delayed by one NAND gate, the output signal of the digital delay line 40 may be inverted according to the number of NAND gates that the input signal has passed. If the delay time of the input signal is N*T.sub.d and N is an odd number, the multiplexer 43 transmits the output signal of the inverter 44 to the output terminal OUT.

(20) If the delay time of the input signal is 2N*T.sub.d and N is an integer, the multiplexer 43 transmits the output signal of the digital delay line 40 to the output terminal OUT. Furthermore, in the embodiment, the multiplexer is implemented by a plurality of NAND gates.

(21) FIG. 5 is a schematic diagram of a signal delay circuit according to an embodiment of the invention. The signal delay circuit comprises a delay control circuit 51 and a digital delay circuit 52. The delay control circuit 51 receives a reference clock signal RCLK and generates a control signal Sc. In this embodiment, the control signal Sc is a digital code. The control signal Sc is determined based on the phase difference between the input clock signal CLK and the reference clock signal RCLK. The digital delay circuit 52 delays the input clock signal CLK to generate an output signal CLK_d. In this embodiment, the implementation of the digital delay circuit 52 can be referred to in the design shown in FIGS. 24.

(22) While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.