IMAGE PICKUP DEVICE THAT IS PROVIDED WITH PERIPHERAL CIRCUITS TO PREVENT CHIP AREA FROM BEING INCREASED, AND IMAGE PICKUP APPARATUS

Abstract

An image pickup device which suppresses an increase in chip area of peripheral circuits without degrading the performance of a pixel section and makes it possible to prevent costs from being increased. The image pickup device includes a first semiconductor substrate and a second semiconductor substrate. A pixel section includes photo diodes each for generate electric charges by photoelectric conversion, floating diffusions each for temporarily storing the electric charges generated by the photo diode, and amplifiers each connected to the floating diffusion, for outputting a signal dependent on a potential of the associated floating diffusion. Column circuits are connected to vertical signal lines, respectively, for performing predetermined processing on signals output from the pixel section to vertical signal lines.

Claims

1.-17. (canceled)

18. A image pickup device comprising: a plurality of substrates which are stacked on top of another, including a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate; a pixel section including a plurality of pixels arranged in matrix form; a signal processing circuit including at least a plurality of AD converters, and configured to perform predetermined processing on signals output from the pixel section and to thereby generate digital signals; and a plurality of memories configured to store the digital signals generated by the signal processing circuit, wherein the pixel section is formed on an area of the first semiconductor substrate, the signal processing circuit is formed on an area of the second semiconductor substrate, and the plurality of memories are formed on an area of the third semiconductor substrate.

19. The image pickup device according to claim 18, wherein the signal processing circuit is also formed on the area of the third semiconductor substrate, so as to be divided between the area of the second semiconductor substrate and the area of the third semiconductor substrate.

20. The image pickup device according to claim 18, comprising a plurality of the signal processing circuits, wherein the plurality of signal processing circuits are provided corresponding to respective columns of the pixels of the pixel section.

21. The image pickup device according to claim 18, wherein the plurality of memories are provided corresponding to respective columns of the pixels of the pixel section.

22. The image pickup device according to claim 18, further comprising an output section configured to output, to outside of the image pickup device, the digital signals stored in the plurality of memories, wherein the output section is formed on the area of the third semiconductor substrate.

23. The image pickup device according to claim 18, wherein the first semiconductor substrate and the second semiconductor substrate face each other, and the second semiconductor substrate and the third semiconductor substrate face each other.

24. An image pickup apparatus comprising an image pickup device, the image pickup device comprising: a plurality of substrates which are stacked on top of another, including a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate; a pixel section including a plurality of pixels arranged in matrix form; a signal processing circuit including at least a plurality of AD converters, and configured to perform predetermined processing on signals output from the pixel section and to thereby generate digital signals; and a plurality of memories configured to store the digital signals generated by the signal processing circuit, wherein the pixel section is formed on an area of the first semiconductor substrate, the signal processing circuit is formed on an area of the second semiconductor substrate, and the plurality of memories are formed on an area of the third semiconductor substrate.

25. The image pickup apparatus according to claim 24, wherein the first semiconductor substrate and the second semiconductor substrate face each other, and the second semiconductor substrate and the third semiconductor substrate face each other.

26. An image pickup device comprising: a first semiconductor substrate and a second semiconductor substrate which are stacked on top of another; a pixel section including a plurality of pixels arranged in a matrix form, wherein the pixel section is formed on an area of the first semiconductor substrate; a plurality of column signal lines which have signals output thereto from the plurality of pixels of the pixel section; a plurality of column circuits, each of which is respectively connected to one of the plurality of column signal lines and configured to perform predetermined processing on the signals output from the column signal lines, wherein each of the plurality of column circuits includes an AD converter which generates digital signals; and a plurality of column memories each of which is respectively connected to one of the plurality of column circuits and which store the digital signals, wherein the plurality of column circuits and the plurality of column memories are formed on an area of the second semiconductor substrate, and wherein at least two column circuits and at least two column memories adjacent to each other, among the plurality of column circuits and the plurality of column memories, are arranged at different locations on the second semiconductor substrate with an offset in at least a column direction.

27. The image pickup device according to claim 26, further comprising a plurality of connection points that electrically connect the area of the first semiconductor substrate to the area of the second semiconductor substrate.

28. The image pickup device according to claim 27, wherein the plurality of connection points are respectively provided on the plurality of column signal lines.

29. The image pickup device according to claim 27, wherein the plurality of connection points are located within the area of the pixel section when the image pickup device is viewed from a light incident direction, and wherein at least one of the plurality of connection points is shifted from an adjacent connection point in a direction of the column signal lines so that said at least one of the plurality of connection points does not align with the adjacent connection point in the row direction.

30. The image pickup device according to claim 26, wherein the column circuits are arranged at respective different locations in a direction along each column.

31. The image pickup device according to claim 26, wherein the column circuits are arranged uniformly in a direction along each column.

32. The image pickup device according to claim 26, further comprising digital circuits which perform predetermined processing on the digital signals output from the column memories, wherein the digital circuits are formed on the area of the second semiconductor substrate.

33. The image pickup device according to claim 26, further comprising drive circuits which drive the pixel section, and wherein a portion of the drive circuits is formed on the area of the first semiconductor substrate and another portion of the drive circuits is formed on the area of the second semiconductor substrate.

34. The image pickup device according to claim 26, wherein the plurality of pixels of the pixel section include photoelectric conversion elements which generate electric charges by photoelectric conversion, floating diffusion areas which temporarily store the electric charges generated in the photoelectric conversion elements, and amplifiers which output signals dependent on potentials of the floating diffusion areas.

35. The image pickup device according to claim 34, wherein the plurality of pixels of the pixel section further includes transfer portions, each of which transfers the electric charges from one of the photoelectric conversion elements to one of the floating diffusion areas, and reset portions each connected to one of the floating diffusion areas and configured to reset the respective floating diffusion areas.

36. The image pickup device according to claim 26, wherein the plurality of column circuits are located in an overlapping manner with the pixel section when viewed in a direction perpendicular to a surface of the semiconductor substrates.

37. The image pickup device according to claim 26, wherein at least two column circuits and at least two column memories adjacent to each other, among the plurality of column circuits and the plurality of column memories, are arranged at different locations on the second semiconductor substrate with an offset in a column direction and a row direction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 is a block diagram useful in explaining the overall configuration of an image pickup device according to a first embodiment of the present invention.

[0027] FIG. 2 is a diagram showing pixels and the circuit configuration for reading out signals from the pixels, in the image pickup device according to the first embodiment.

[0028] FIG. 3 is a diagram showing a variation of the circuit configuration shown in FIG. 2.

[0029] FIG. 4 is a diagram showing another variation of the circuit configuration shown in FIG. 2.

[0030] FIG. 5 is a view showing a cross-sectional structure of the image pickup device according to the first embodiment.

[0031] FIG. 6 is a block diagram showing a variation of the overall configuration of the image pickup device shown in FIG. 1.

[0032] FIG. 7 is a block diagram showing another variation of the overall configuration of the image pickup device shown in FIG. 1.

[0033] FIG. 8 is a view showing a cross-sectional structure of an image pickup device according to a second embodiment of the present invention.

[0034] FIG. 9 is a block diagram showing still another variation of the overall configuration of the image pickup device shown in FIG. 1.

[0035] FIG. 10 is a schematic diagram of a digital camera as an example of an image pickup apparatus equipped with the image pickup device according to any of the first and second embodiments and variations thereof.

[0036] FIG. 11 is a diagram showing a configuration of a pixel and a circuit configuration for reading out a signal from the pixel, in an image pickup device according to a third embodiment of the present invention.

[0037] FIG. 12 is a diagram showing a variation of the circuit configuration of the image pickup device shown in FIG. 11.

[0038] FIG. 13 is a diagram showing another variation of the circuit configuration of the image pickup device shown in FIG. 11.

[0039] FIG. 14 is a diagram of the overall configuration of the image pickup device according to the third embodiment, as viewed from above.

[0040] FIG. 15 is a cross-sectional view of an image pickup device as a variation of the third embodiment.

[0041] FIG. 16 is a diagram of the overall configuration of an image pickup device according to a fifth embodiment of the present invention, as viewed from above.

[0042] FIG. 17 is a diagram of a variation of the overall configuration of the image pickup device according to the fifth embodiment, as viewed from above.

[0043] FIG. 18 is a diagram of another variation of the overall configuration of the image pickup device according to the fifth embodiment, as viewed from above.

[0044] FIG. 19 is a diagram of the overall configuration of an image pickup device according to a sixth embodiment of the present invention, as viewed from above.

[0045] FIG. 20 is a diagram of a variation of the overall configuration of the image pickup device according to the sixth embodiment, as viewed from above.

[0046] FIG. 21 is a diagram of another variation of the overall configuration of the image pickup device according to the sixth embodiment, as viewed from above.

[0047] FIG. 22 is a diagram of the overall configuration of an image pickup device according to a seventh embodiment of the present invention, as viewed from above.

[0048] FIG. 23 is a diagram of the overall configuration of an image pickup device according to an eighth embodiment of the present invention, as viewed from above.

[0049] FIG. 24 is a diagram of the overall configuration of an image pickup device according to a ninth embodiment of the present invention, as viewed from above.

[0050] FIG. 25 is a diagram of a variation of the overall configuration of the image pickup device according to the ninth embodiment, as viewed from above.

[0051] FIG. 26 is a diagram of another variation of the overall configuration of the image pickup device according to the ninth embodiment, as viewed from above.

[0052] FIG. 27 is a schematic block diagram useful in explaining a conventional image pickup device.

[0053] FIG. 28 is a diagram showing the configuration of one pixel in the conventional image pickup device, and a circuit configuration for reading out a signal from the pixel.

DESCRIPTION OF THE EMBODIMENTS

[0054] The present invention will now be described in detail below with reference to the accompanying drawings showing embodiments thereof.

[0055] FIG. 1 is a block diagram useful in explaining the overall configuration of an image pickup device according to a first embodiment of the present invention. It is assumed that in actuality, illustrated areas 1 and 2 overlap in a vertical direction.

[0056] In FIG. 1, the image pickup device includes a pixel section 101, a vertical selection circuit 102 which selects at least one of rows of pixels in the pixel section 101, and column circuits 103 each of which reads out signals from pixels on a pixel row in the pixel section 101 selected by the vertical selection circuit 102, and performs predetermined processing on the read signals. The image pickup device further includes column memories 104 each of which holds signals processed by the column circuits 103, on a column basis, horizontal selection circuits 105 each of which selects a signal held in the associated column memory 104, and output signal lines 106 each of which reads out signals from a column selected by the horizontal selection circuit 105 to an associated one of output circuits 107. Note that the image pickup device may further incorporate not only illustrated components but also a timing generator 1007, referred to hereinafter, which supplies a timing signal to each of the vertical selection circuit 102, the horizontal selection circuits 105, the column circuits 103, etc., a control circuit 1009, referred to hereinafter, a digital-to-analog converter, and so forth. However, these components are not necessarily required to be provided on the same chip as the image pickup device, but the timing generator 1007 and the control circuit 1009 may be provided separately from the image pickup device, as shown in FIG. 10.

[0057] The vertical selection circuit 102 sequentially selects a plurality of rows in the pixel section 101, and outputs signals from a selected row to the column memories 104 via the column circuits 103. Each horizontal selection circuits 105 sequentially selects signals held in the associated column memory 104, and outputs the selected signals to the associated output circuit 107 via the associated output signal line 106. The pixel section 101 is formed by arranging a plurality of pixels in a two-dimensional array to provide a two-dimensional image.

[0058] The pixel section 101, the vertical selection circuit 102, and the output circuits 107, which are included in the area 1, are formed on a first semiconductor substrate. On the other hand, the column circuits 103, the column memories 104, the horizontal selection circuits 105, and the output signal lines 106, which are included in the area 2, are formed on a second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are separately formed, and are laminated while providing interconnections requiring electrical connection, whereby both the substrates are mounted in the same package. That is, as viewed from an upper surface of the image pickup device package (from a side of the pixel section 101 where light enters), the column circuits 103, the column memories 104, the horizontal selection circuits 105, and the output signal lines 106, which are formed on the area 2 on the second semiconductor substrate, are disposed under the pixel section 101 formed on the area 1 on the first semiconductor substrate, in an overlapping manner. By disposing the timing generator 1007, the control circuit 1009, the digital-to-analog converter, etc. in the area 2 under the vertical selection circuit 102 and the output circuits 107 in the area 1, a high area efficiency is achieved. Note that although in a plurality of embodiments described hereinafter, the arrangement including the first semiconductor substrate and the second semiconductor substrate will be described by way of example, this is not limitative, but the arrangement may include still another semiconductor substrate.

[0059] FIG. 2 is a diagram showing a pixel and the circuit configuration for reading out a signal from the pixel in the image pickup device according to the first embodiment.

[0060] As shown in FIG. 2, a pixel array which provides a two-dimensional image is formed by arranging a plurality of pixels in a two-dimensional array. Each pixel 201 is configured to include a photo diode (hereinafter also referred to as the PD) 202, a transfer switch 203, a floating diffusion (hereinafter also referred to as the FD) 204, a reset switch 207, a MOS amplifier 205, and a selection switch 206.

[0061] The PD 202 functions as a photoelectric conversion element which converts light incident through an optical system to an electric signal by photoelectric conversion to thereby generate electric charges. The anode of the PD 202 is connected to a ground line, and the cathode of the PD 202 is connected to the source of the transfer switch 203. The transfer switch 203 is driven by a transfer pulse TX input to a gate terminal thereof to transfer the electric charges generated in the PD 202 to the FD 204. The FD 204 functions as a charge-voltage converting section which temporarily accumulates electric charges, and converts the accumulated electric charges to a voltage signal.

[0062] The MOS amplifier 205 is implemented by an amplification circuit, such as a MOSFET, functions as a source follower, and has a gate to which the voltage signal converted from the electric charges in the FD 204 is input. Further, the MOS amplifier 205 has a drain connected to a first power line VDD1 for supplying a first potential thereto, and a source connected to the selection switch 206. The selection switch 206 is driven by a vertical selection pulse SEL input to a gate thereof, and has a drain connected to the MOS amplifier 205, and a source connected to a vertical signal line 208. When the vertical selection pulse SEL becomes an active level (high level), the selection switch 206 of each pixel belonging to the corresponding row on the pixel array becomes conductive, whereby the source of the MOS amplifier 205 is connected to the vertical signal line 208.

[0063] The reset switch 207 has a drain connected to a second power line VDD2 for supplying a second potential (reset potential) as a constant potential, and a source connected to the FD 204. Further, the reset switch 207 is driven by a reset pulse RES input to a gate thereof to remove the electric charges accumulated in the FD 204. The pulses TX, SEL, and RES are supplied from the vertical selection circuit 102.

[0064] A floating diffusion amplifier is formed by not only the FD 204 and the MOS amplifier 205, but also a constant current source 209 for supplying a constant current to the vertical signal line 208. In each of pixels forming the row selected by the selection switch 206, the electric charges transferred from the PD 202 to the FD 204 is converted to the voltage signal, and the voltage signal is output to the vertical signal line (column signal line) 208 provided on a column basis through the floating diffusion amplifier.

[0065] The column circuits 103 connected to the vertical signal lines (column signal lines) 208 are each implemented e.g. by a CDS (correlated double sampling) circuit and a gain amplifier. The CDS circuit performs correlated double sampling processing on a signal output to the vertical signal line 208. The gain amplifier amplifies a signal output to the vertical signal line 208 with a predetermined gain. Further, the column circuits 103 are formed by respective circuits each having the same configuration on a column basis. A signal subjected to the above-mentioned processing by the column circuit 103 is held by an associated one of the column memories 104. The signal held by the column memory 104 is transferred to the output circuit 107 through the output signal line 106. The output circuit 107 performs amplification, impedance conversion, etc., on the input signal, and outputs the processed signal to the outside of the image pickup device.

[0066] Although the column circuit 103, the column memory 104, and the output circuit 107 can be configured to have the above-described circuit configuration, the column circuit 103 may be configured to have an analog-to-digital converter on a column basis. In this case, the column circuit 103 includes an analog-to-digital converter in addition to the CDS circuit and the gain amplifier. Further, each column memory 104 in this case is a digital memory, and each output circuit 107 is provided with components including an LVDS (low voltage differential signaling) driver.

[0067] The illustrated area 1, i.e. the first semiconductor substrate is configured to include the PD 202, the transfer switch 203, the FD 204, the reset switch 207, the MOS amplifier 205, and the selection switch 206, provided on a pixel basis, and the output circuits 107.

[0068] The illustrated area 2, i.e. the second semiconductor substrate is configured to include the vertical signal lines 208, the constant current sources 209, the column circuits 103, the column memories 104, and the output signal lines 106, provided on a column basis. The vertical signal lines (column signal lines) 208 are interconnections connecting between the pixel section 101 and the column circuits 103, and may be included in either the area 1 or the area 2. Further, each selection switch 206 may be included in the area 2.

[0069] Further, as in a variation of the circuit configuration shown in FIG. 3, the constant current source 209 may be included in the area 1. However, in this case, the constant current source 209 is disposed on the same board as that on which the pixels are disposed, and hence the area efficiency is not very high. This arrangement is effective only in a case where an area for arranging the column circuit 103, the column memory 104, and the output signal line 106 is larger than the area of the pixel section.

[0070] Further, as in another variation of the circuit configuration shown in FIG. 4, the selection switch 206 may be omitted. In the circuit configuration without the selection switch 206, each selected row and each non-selected row are set by controlling the reset pulse RES and the potential of the second power line VDD2.

[0071] FIG. 5 is a view showing a cross-sectional structure of the image pickup device according to the first embodiment of the present invention. FIG. 5 shows the structure in which the area 1 as the first semiconductor substrate is laminated on the area 2 as the second semiconductor substrate. The same components as those shown in FIG. 2 are denoted by the same reference numerals.

[0072] The area 1 indicating the first semiconductor substrate is formed on a semiconductor substrate 501. The area 1 includes a region 502 of a first conductivity type, a region 202 of the PDs, and a region 503 of the first conductivity type for reducing dark current of the PDs 202. The area 1 further includes the transfer switches 203, the FDs 204, and the MOS amplifiers 205. In addition to these, the area 1 includes the reset switches 207.

[0073] The area 1 further includes an element isolation region 504, a interconnection layer 505 formed in a multilayered manner, and an interlayer film 506 between the multiple layers of the interconnection layer 505. A through hole 507 electrically connects between the interconnections. Since the area 1 includes the pixel section, it also includes a color filter 508 for performing color separation, and a micro lens 509 for collecting light.

[0074] The area 2 indicating the second semiconductor substrate as a semiconductor substrate other than the first semiconductor substrate is formed on a semiconductor substrate 510. Each circuit of the column circuit 103 is formed by a plurality of types of switches in each of switch type groups 511. The area 2 further includes the column memories 104, the output signal lines 106, and so on. Connection points 115 of the vertical signal lines 208 are formed e.g. by micro bumps which electrically connect between the area 1 and the area 2. Further, in addition to the connection points 115 of the vertical signal lines 208, the area 2 includes connection points 512 formed e.g. by micro bumps which electrically connect interconnections for supplying power and various kinds of drive pulses. Although in the present embodiment, there is illustrated the first semiconductor substrate in which a light receiving section is formed by a back side illumination type, the light receiving section may be formed by a front side illumination type instead of the back side illumination type.

[0075] Although in the present embodiment, the pixel section 101, the vertical selection circuit 102, and the output circuits 107 are formed in the area 1, and the other drive circuits are disposed in the area 2, this is not limitative. For example, as in a variation of the overall configuration of the image pickup device shown in FIG. 6, the output circuits 107 may be disposed in the area 2.

[0076] Further, as in another variation of the overall configuration of the image pickup device shown in shown in FIG. 7, part of the vertical selection circuit 102 may be disposed in the area 1, and the rest of the vertical selection circuit 102 may be disposed in the area 2. Further, in this case, it is possible to improve the area efficiency by arranging the part and the rest of the vertical selection circuit 102 at approximately the same location, as viewed from above. That is, in the present invention, it is only required to arrange at least the transfer switches 203, the FDs 204, the reset switches 207, and the MOS amplifiers 205 of the pixel section 101 in the area 1 so as to prevent the FDs 204 from being divided between the area 1 and the area 2. The other drive circuits can be disposed in the area 1 or the area 2 depending on the area efficiency of the semiconductor substrate.

[0077] Although in the above-described embodiment, as shown in FIG. 5, the area 1 is set on the first semiconductor substrate, and the area 2 is set on the second semiconductor substrate, this is not limitative, but the areas 1 and 2 may be formed on the same semiconductor substrate, as shown in FIG. 8.

[0078] FIG. 8 is a view showing a cross-sectional structure of an image pickup device according to a second embodiment of the present invention. The same components as those shown in FIGS. 2 and 5 are denoted by same reference numerals, and description thereof is omitted.

[0079] In the second embodiment shown in FIG. 8, the area 1 and the area 2 are formed on the front side (first side or second side) and the back side (first side or second side) of the semiconductor substrate 501, respectively. In the present embodiment, a description will be given assuming that a side on which the area 1 is formed is the front side, and a side on which the area 2 is formed is the back side. A protective layer 801 protects the interconnection layer 505 on the back side. Plugs 802 electrically connect between the front side and the back side.

[0080] Further, although in the above-described embodiments, the description has been given of the area 1 and the area 2, the areas are not limited to two, but may be divided into a plurality of areas and have various components arranged thereon. For example, as in a variation shown in FIG. 9, the pixel section 101 and the vertical selection circuit 102 may be formed on the area 1, and the rest of the drive circuits may be formed in a manner divided between the areas 2 and 3. In the illustrated example, the rest of the vertical selection circuit 102 and the column circuits 103 are formed on the area 2, and the rest of the column circuits 103 and the other drive circuits are formed on the area 3, separately. As described above, by separately arranging the components across the plurality of areas, it is possible to mount an analog-to-digital converter and the like, on a column basis, and effectively arrange an increasing number of column circuits 103. Note that the areas 1, 2, and 3 may be formed on different semiconductor substrates, respectively.

[0081] FIG. 10 is a schematic diagram of a digital camera as an example of an image pickup apparatus equipped with the image pickup device according to any of the above-described embodiments and variations.

[0082] In FIG. 10, a lens unit 1001 which forms an optical image of an object into an image on a solid image pickup device (the image pickup device according to any of the above-described embodiments and variations) 1005 is driven by a lens drive unit 1002 so as to perform zoom control, focus control, aperture control, and so forth. A mechanical shutter 1003 is controlled by a shutter control unit 1004. The solid image pickup device 1005 converts an object image formed by the lens unit 1001 to an image signal, and outputs the image signal. An image pickup signal processing circuit 1006 performs various kinds of correction on an image signal output from the solid image pickup device 1005, and compresses data.

[0083] The timing generator 1007 is a drive unit which supplies various kinds of timing signals to the solid image pickup device 1005 and the image pickup signal processing circuit 1006. The control circuit 1009 controls various kinds of computations and the overall operation of the image pickup apparatus. A memory 1008 temporarily stores image data. An recording medium control interface 1010 records or reads out data in or from a removable storage medium 1011, such as a semiconductor memory. A display unit 1012 displays various information items and a shot image.

[0084] Next, a description will be given of the operation of the digital camera having the above-described arrangement during shooting.

[0085] When the main power, not shown, is switched on, the power of a control system turns on, and further, the power of image pickup system circuits, such as the image pickup signal processing circuit 1006, turns on. Subsequently, when a release button, not shown, is depressed, the control circuit 1009 extracts a high-frequency component based on a signal output from a distance measurement device 1014, and performs calculation of a distance to the object. Thereafter, the control circuit 1009 drives the lens unit 1001 by the lens drive unit 1002, and determines whether or not the object is in focus. If it is determined that the object is not in focus, the control circuit 1009 drives the lens unit 1001 again, and performs distance measurement. Then, when it is confirmed that the object is in focus, an image pickup operation is started.

[0086] When the image pickup operation is terminated, the image signal output from the solid image pickup device 1005 is subjected to image processing in the image signal processing circuit 1006, and is written into the memory 1008 by the control circuit 1009. The data accumulated in the memory 1008 is recorded in the removable storage medium 1011, such as a semiconductor memory, through the recording medium control interface 1010 by the control of the control circuit 1009. Note that the data may be directly input e.g. to a computer for image processing through an external interface section, not shown.

[0087] FIG. 11 is a diagram showing a configuration of a pixel and a circuit configuration for reading out a signal from the pixel, in an image pickup device according to a third embodiment of the present invention. The area 1 is a chip including circuits formed on the first semiconductor substrate, and the area 2 is a chip including circuits formed on the second semiconductor substrate.

[0088] The area 1 mainly includes the pixels 201, and the area 2 mainly includes the column circuit for processing a signal from each pixel 201.

[0089] The area 1 is formed by arranging a plurality of the pixels 201 in a two-dimensional array as a pixel array which provides a two-dimensional image. Each pixel 201 can be configured to include the photo diode (hereinafter also referred to as the PD) 202, the transfer switch 203, the floating diffusion (hereinafter also referred to as the FD) 204, the MOS amplifier 205, the selection switch 206, and the reset switch 207.

[0090] The PD 202 functions as a photoelectric conversion section which converts light incident through an optical system to an electric signal by photoelectric conversion to thereby generate electric charges. The anode of the PD 202 is connected to a ground line, and the cathode of the PD 202 is connected to a source of the transfer switch 203. The transfer switch 203 is driven by a transfer pulse TX input to a gate terminal thereof to transfer the electric charges generated in the PD 202 to the FD 204. The FD 204 functions as a charge-voltage converting section which temporarily accumulates electric charges, and converts the accumulated electric charges to a voltage signal.

[0091] The MOS amplifier 205 functions as a source follower, and has a gate to which the voltage signal converted from the electric charges in the FD 204 is input. Further, the MOS amplifier 205 has a drain connected to the first power line VDD1 for supplying a first potential thereto, and a source connected to the selection switch 206. The selection switch 206 is driven by a vertical selection pulse SEL input to a gate thereof, and has a drain connected to the MOS amplifier 205, and a source connected to the vertical signal line 208. When the vertical selection pulse SEL becomes an active level (high level), the selection switch 206 of each pixel belonging to the corresponding row on the pixel array becomes conductive, whereby the source of the MOS amplifier 205 is connected to the vertical signal line 208. The vertical signal line 208 is shared by a plurality of pixels 201 sharing a column.

[0092] The reset switch 207 has a drain connected to the second power line VDD2 for supplying a second potential (reset potential), and a source connected to the FD 204, and is driven by a reset pulse RES input to the gate thereof to remove electric charges accumulated in the FD 204.

[0093] A floating diffusion amplifier is formed by not only the FD 204 and the MOS amplifier 205, but also the constant current source 209 for supplying a constant current to the vertical signal line 208. In each of pixels forming the row selected by the selection switch 206, the electric charges transferred from the PD 202 to the FD 204 is converted to the voltage signal by the FD 204, and the voltage signal is output to the vertical signal line (column signal line) 208 provided on a column basis through the floating diffusion amplifier. The pulses TX, SEL, and RES are supplied from the vertical selection circuit, referred to hereinafter.

[0094] The column circuit 103 connected to each of the vertical signal lines (column signal line) 208 is implemented e.g. by a column amplifier 110. The column circuits 103 are formed by respective circuits each having the same configuration on a column basis. The column circuit 103 may have the configuration including only the column amplifier 110 appearing in FIG. 11, or may have a configuration including a CDS (correlated double sampling) circuit.

[0095] A signal subjected to the above-mentioned processing by the column circuit 103 is held by an associated one of the column memories 104. The signal held by the column memory 104 is transferred to the output circuit 107 through the output signal line 106. The output circuit 107 performs amplification, impedance conversion, etc., on the input signal, and outputs the processed signal to the outside of the image pickup device.

[0096] The area 1 and the area 2 are electrically connected via the connection points 115 of the vertical signal lines (column signal lines) 208. Each connection points 115 is disposed downstream of the MOS amplifier 205 as shown in FIG. 11, whereby it is possible to reduce PRNU (photo response non-uniformity) and DSNU (dark signal non-uniformity). The constant current source 209 may be disposed in the area 2 or in the area 1.

[0097] FIG. 12 is a diagram showing a variation of the circuit configuration of the image pickup device shown in FIG. 11.

[0098] In FIG. 12, a column AD 111 is mounted at a location downstream of the column amplifier 110. The column AD 111 is an analog-to-digital converter provided on a column basis, which performs analog-to-digital conversion. In this case, the column circuit 103 is formed by the column amplifier 110 and the column AD 111. The column circuit 103 may further include the above-mentioned CDS circuit, etc. In the case of the configuration including the column AD 111, the column memory 104 is a digital memory, and the output circuit 107 is provided with components including an LVDS (low voltage differential signaling) driver.

[0099] Further, as shown in another variation shown in FIG. 13, the circuit configuration may exclude the selection switch 206.

[0100] FIG. 14 is a schematic diagram of the image pickup device according to the third embodiment, as viewed from above. The area 1 and the area 2 are chips formed on different semiconductor substrates, respectively, and are mounted on the same package by providing interconnections requiring electrical connection. That is, as viewed from an upper surface of the package, the area 2 is disposed under the area 1, in an overlapping manner.

[0101] The area 1 has the pixels 201 formed on a plurality of rows and columns in an array. The above-mentioned pulses TX, SEL, and RES for driving the pixels 201 are supplied from the vertical selection circuit 102, on a row basis. The vertical signal line 208 for taking out a signal from a pixel is shared by pixels in the same column. Here, the vertical signal lines 208 in the first to fourth columns are denoted by reference numerals 208_1, 208_2, 208_3, and 208_4. The area 1 and the area 2 each have the connection points 115 for connecting the vertical signal lines 208 to the column circuits 103. The connection point 115 included in the vertical signal line 208_1 is denoted by reference numeral 115_1. Further, the column circuit 103 connected to the vertical signal line 208_1 is denoted by reference numeral 103_1, and the column memory 104 connected to the column circuit 103_1 is denoted by reference numeral 104_1. The area 2 includes the horizontal selection circuits 105 each for transferring signals from the column memory 104 to the output circuit 107. Each horizontal selection circuit 105 transfers signals from the column memory 104 to the output circuit 107 on a time-series basis.

[0102] Although not shown, one of the area 1 and the area 2 includes the above-mentioned constant current source 209 in addition to the illustrated components. The constant current source 209 may be included in the column circuit 103. Further, in addition, for example, one of the area 1 and the area 2 includes a timing generator or a control circuit which provides a timing signal to the vertical selection circuit 102, the horizontal selection circuit 105, and the column circuit 103, etc., and a serial communication interface, and a digital-to-analog converter.

[0103] Various kinds of pulses are supplied from the timing generator etc., to each horizontal selection circuit 105, and hence it is desirable that the horizontal selection circuits 105 are disposed close to respective ends of the chip. As shown in FIG. 14, by arranging the connection point 115 in the vicinity of the center of the chip in a direction along each column, it is possible to arrange the horizontal selection circuits 105 in the vertical direction.

[0104] A cross-sectional structure of the image pickup device according to the present embodiment is substantially the same as that according to the first embodiment shown in FIG. 5, and hence illustration and description thereof are omitted.

[0105] As shown in FIG. 14, by sharing the connection point 115 on each vertical signal line (column signal line) between pixels, the number of connection points is smaller than in a case where the connection points are provided on a pixel basis, so that it is possible to solve a problem that yields are reduced due to a formation error of connection points. It is to be understood that the number of connection points is not limited to one, but the connection point may be provided in plurality taking into account the yields. In the present embodiment, each vertical signal line in the area 1 is shared between the pixels, whereby it is not necessary to connect the area 1 and the area 2, on a pixel-by-pixel basis.

[0106] Although in the present embodiment, there is illustrated the first semiconductor substrate in which a light receiving section is formed by a back side illumination type, the light receiving section may be formed by a front side illumination type instead of the back side illumination type. FIG. 15 is a view showing a cross-sectional structure of the front side illumination type as a variation of the present embodiment. FIG. 15 shows the structure in which the area 1 as the first semiconductor substrate is laminated on the area 2 as the second semiconductor substrate. Description of components denoted by the same reference numerals as those shown in FIG. 5 is omitted. In the front side illumination type, the micro lens 509 is disposed on top of the interconnection layer 505 with respect to the semiconductor substrate 501. In the front side illumination type, through vias 601 are formed to connect the connection points 115 and the components in the area 1.

[0107] A cross-sectional structure according to a fourth embodiment of the present invention in which the area 1 and the area 2 of the front side illumination type are formed on the same substrate 501 is substantially the same as the cross-sectional structure of the second embodiment shown in FIG. 8, and hence illustration and description thereof are omitted, but as described above, in this case, the connection points 115 are formed by the through vias 601 to connect the vertical signal lines 208 and the circuits on the backside.

[0108] FIG. 16 is a diagram of the overall configuration of an image pickup device according to a fifth embodiment of the present invention, as viewed from above. FIGS. 17 and 18 are diagrams of respective variations thereof.

[0109] Differently from FIG. 14, in the overall configuration of the image pickup device according to the fifth embodiment shown in FIG. 16, the connection points 115_1 and 115_2 as the connection points 115 are displaced in the direction along each column, whereby it is possible to dispose the connection points 115 immediately close to the column circuits 103_1 and 103_2. This reduces the length of interconnections in the area 2, and makes it possible to further efficiently arrange the column circuits 103 etc.

[0110] In the variation shown in FIG. 17, the connection points 115_1, 115_2, 115_3, and 115_4 are displaced, whereby it is possible to arrange the column circuits 103_1 to 103_4 in a sparse or unconcentrated manner. In the case of the arrangement shown in FIG. 14, in which the column circuits 103 are concentrated in a particular area, heat generated in the column circuits 103 is concentrated, whereby non-uniformity of dark current within a screen-associated region of a shot image is caused by the PDs 202 which receive heat from the column circuits 103. However, with the arrangement of the circuit configuration shown in FIG. 17, it is possible to reduce non-uniformity of dark current within the screen-associated region due to heat generation in the column circuits 103. In FIG. 17, by reversing the arrangement of the column circuit 103_1 and the column memory 104_1, and the column circuit 103_3 and the column memory 104_3, the column circuits 103 are dispersed. To this end, the arrangement is improved such that an output signal line 106 is also disposed in the center along the direction of each column. However, in the case of the arrangement illustrated in FIG. 18 in which the column circuits 103 and the column memories 104 can be sufficiently reduced in size, it is not necessary to dispose the output line in the center, and the column circuits 103_1 and 103_3 may be arranged in the same direction.

[0111] As described above, by displacing the connection points 115 on a column-by-column basis, it is possible to efficiently arrange the circuits, and realize the arrangement which reduces the influence of heat generation by the column circuits 103.

[0112] FIG. 19 is a diagram of the overall configuration of an image pickup device according to a sixth embodiment of the present invention, as viewed from above. FIGS. 20 and 21 are diagrams of respective variations thereof.

[0113] Although in FIGS. 14, 16, 17, and 18, the column circuit 103 and the column memory 104 are illustrated as the circuits having a width corresponding to two columns in the direction along each row, this is not limitative, but the column circuit 103 and the column memory 104 can be differently configured in the present invention. For example, as shown in FIG. 19, the column circuit 103 and the column memory 104 may have a width corresponding to one column in the direction along each row. However, the column circuit 103 and the column memory 104 are increased in length in the direction along each column, and become vertically still longer. The column circuit 103 and the column memory 104 are isolated from the adjacent column circuit 103 and the column memory 104 in the element isolation region, and hence it is possible to achieve a more excellent area efficiency when the column circuit 103 and the column memory 104 are formed in an area closer to a square in shape. In the variation shown in FIG. 20, the column circuit 103 and the column memory 104 have a width corresponding to four columns in the direction along each row. Although the column circuit 103 and the column memory 104 look horizontally long in the schematic diagram, in actuality, to make the area for the circuits closer to a square in shape, by displacing the connection points 115 on a column-by-column basis, it is possible to provide such a layout. As shown the variation in FIG. 21, with the increase in the width of the column circuit 103 and the column memory 104 in the direction along each line, it is possible to dispose a plurality of output signal lines 106. The output signal lines 106 do not consume electric power, and hence by increasing the number of the output signal lines 106 and disposing them between the column circuits 103 and the column memories 104, it is possible to disperse heat generation.

[0114] FIG. 22 is a diagram of the overall configuration of an image pickup device according to a seventh embodiment of the present invention, as viewed from above. Although the arrangement shown in FIG. 22 is configured based on the same concept as that of the arrangement shown in FIG. 17, if the column circuit 103 and the column memory 104 are small in size, vacant space is formed between the circuits. In a case where the column AD is mounted as in the case illustrated in FIG. 12, it is possible to dispose digital circuits 1401. Each digital circuit 1401 is capable of performing various kinds of correction processing, such as gamma correction, and image processing, such as white balance adjustment, on signals output from the column memories 104. The arrangement is not limited to the examples shown in FIGS. 17 and 21, but by arranging the column circuits 103 in a dispersed manner, the digital circuits 1401 may be also arranged in a dispersed manner, whereby it is also possible to reduce non-uniformity of dark current due to heat generation by the digital circuits 1401. Further, when the column ADs are mounted, the horizontal selection circuits 105 are not necessarily required.

[0115] FIG. 23 is a diagram of the overall configuration of an image pickup device according to an eighth embodiment of the present invention, as viewed from above. In FIG. 23, the connection points 115 are disposed at vertically one-sided locations. In this case, although it is not possible to reduce non-uniformity of dark current, the arrangement is effective for forming the through vias, as shown in FIGS. 15 and 8. When the characteristics of the pixels 201 in the vicinity of the connection points 115 are degraded due to formation of the through vias, it is possible to make the corresponding pixels having low characteristics unnoticeable as an image, by displacing the connection points 115 toward the upper and lower regions which are relatively unnoticeable within the screen.

[0116] FIG. 24 is a diagram of the overall configuration of an image pickup device according to a ninth embodiment of the present invention, as viewed from above. FIGS. 25 and 26 are diagrams of respective variations thereof.

[0117] Although in the above-described circuit configuration, the vertical selection circuit 102 is formed in the area 1, and the output circuits 107 are formed in the area 2, this is not limitative. As shown in FIG. 24, the output circuits 107 may be formed in the area 1. In this case, the output signal lines 106 and the output circuits 107 are connected between the area 1 and the area 2. As schematically shown in FIG. 24, the area 1 and the area 2 are not required to be the same in size. Further, as shown in the variation in FIG. 25, part of the vertical selection circuit 102 may be formed in the area 2. In this configuration, a drive buffer of the vertical selection circuit 102 for driving the pixels 201 can be moved to the area 1, and the digital section of the same can be moved to the area 2. Further, as shown in the variation in FIG. 26, it is possible to arrange the output circuits 107 such that they do not extend in the horizontal direction, but extend in the vertical direction. When the column circuits are small in the vertical direction, it is possible to make the area 1 and the area 2 nearly equal in size by adopting such a layout.

[0118] The configuration and operations of the digital camera as an image pickup apparatus using the image pickup device according to any of the above-described embodiments and variations thereof are the same as those described with reference to FIG. 10, and hence description thereof is omitted.

[0119] Aspects of the present invention can also be realized by a computer of a system or apparatus (or devices such as a CPU or MPU) that reads out and executes a program recorded on a memory device to perform the functions of the above-described embodiment(s), and by a method, the steps of which are performed by a computer of a system or apparatus by, for example, reading out and executing a program recorded on a memory device to perform the functions of the above-described embodiment(s). For this purpose, the program is provided to the computer for example via a network or from a recording medium of various types serving as the memory device (e.g., computer-readable medium).

[0120] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

[0121] This application claims the benefit of Japanese Patent Application No. 2011-169291 filed Aug. 2, 2011, and Japanese Patent Application No. 2012-159605 filed Jul. 18, 2012, which are hereby incorporated by reference herein in their entirety.