LOW LEAKAGE RESISTIVE RANDOM ACCESS MEMORY CELLS AND PROCESSES FOR FABRICATING SAME

Abstract

A resistive random access memory device is formed in an integrated circuit between a first metal layer and a second metal layer and includes a first barrier layer disposed over the first metal layer, a tunneling dielectric layer disposed over the first barrier layer, a solid electrolyte layer disposed over the tunneling dielectric layer, an ion source layer disposed over the solid electrolyte layer, and a second barrier layer disposed over the ion source layer.

Claims

1. A resistive random access memory device formed in an integrated circuit between a first metal layer and a second metal layer and comprising: a first barrier layer disposed over the first metal layer; a tunneling dielectric layer disposed over the first barrier layer; a solid electrolyte layer disposed over the tunneling dielectric layer; an ion source layer disposed over the solid electrolyte layer; and a second barrier layer disposed over the ion source layer.

2. A resistive random access memory device formed in an integrated circuit and comprising: a first metal layer; a first barrier layer disposed over the first metal layer; a tunneling dielectric layer disposed over the first barrier layer; a solid electrolyte layer disposed over the tunneling dielectric layer; an ion source layer disposed over the solid electrolyte layer; a second barrier layer disposed over the ion source layer; and a second metal layer disposed over the second barrier layer.

3. A resistive random access memory device formed in an integrated circuit between a first metal layer and a second metal layer and comprising: a first barrier layer disposed over the first metal layer; a solid electrolyte layer disposed over the first barrier layer; a dielectric layer disposed over the solid electrolyte layer; an ion source layer disposed over the dielectric layer; and a second barrier layer disposed over the ion source layer and beneath the second metal layer.

4. A resistive random access memory device formed in an integrated circuit between a first metal layer and a second metal layer and comprising: a first barrier layer disposed over the first metal layer; a tunneling dielectric layer disposed over the first barrier layer; a solid electrolyte layer disposed over the tunneling dielectric layer; a dielectric layer disposed over the solid electrolyte layer; an ion source layer disposed over the dielectric layer; and a second barrier layer disposed over the ion source layer and beneath the second metal layer.

5. A method for forming a resistive random access memory device in an integrated circuit between a first metal layer and a second metal layer comprising: forming a first barrier layer disposed over the first metal layer; forming a tunneling dielectric layer disposed over the first barrier layer; forming a solid electrolyte layer disposed over the tunneling dielectric layer; forming an ion source layer disposed over the solid electrolyte layer; and forming a second barrier layer disposed over the ion source layer.

6. The method of claim 5, further including: forming a dielectric layer over the solid electrolyte layer before forming the ion source layer.

7. A method for forming a resistive random access memory device in an integrated circuit between a first metal layer and a second metal layer comprising: forming a first barrier layer disposed over the first metal layer; forming a tunneling dielectric layer disposed over the first barrier layer; forming a solid electrolyte layer disposed over the tunneling dielectric layer; forming an ion source layer disposed over the solid electrolyte layer; forming a second barrier layer disposed over the ion source layer; and forming a second metal layer disposed over the second barrier layer.

8. A method for forming a resistive random access memory device in an integrated circuit between a first metal layer and a second metal layer comprising: forming a first barrier layer disposed over the first metal layer; forming a solid electrolyte layer disposed over the first barrier layer; forming a dielectric layer disposed over the solid electrolyte layer; forming an ion source layer disposed over the dielectric layer; and forming a second barrier layer disposed over the ion source layer and beneath the second metal layer.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0033] FIG. 1 is a schematic diagram of an illustrative push-pull ReRAM cell of the prior art to show the environment in which the present invention will typically function.

[0034] FIG. 2 is a cross sectional view of an illustrative semiconductor layout for a ReRAM cell of the prior art like that shown in FIG.1.

[0035] FIG. 3 is a cross-sectional view of an illustrative prior-art ReRAM device.

[0036] FIG. 4 is a cross-sectional view of an illustrative ReRAM device in accordance with a first aspect of the present invention.

[0037] FIG. 5 is a cross-sectional view of an illustrative ReRAM device in accordance with another aspect of the present invention.

[0038] FIG. 6 is a cross-sectional view of an illustrative ReRAM device in accordance with yet another aspect of the present invention.

[0039] FIGS. 7A through 7G are cross-sectional views of an illustrative ReRAM device showing the structure resulting after various steps in the semiconductor fabrication process have been performed.

[0040] FIG. 8 is a schematic diagram depicting four illustrative ReRAM cells in an array to show a method for programming and erasing the ReRAM cells.

[0041] FIG. 9 is a table showing voltages to be applied to the ReRAM memory array of FIG. 8 to erase and program the cells.

DETAILED DESCRIPTION

[0042] Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

[0043] Referring now to FIG. 4, a diagram shows a cross-sectional view of an illustrative ReRAM device 110 in accordance with a first aspect of the present invention. For convenience, structures in the embodiment of FIG. 4 that are similar to structures shown in FIG. 3 will be designated using the same reference numerals used in FIG. 3.

[0044] ReRAM device 110 is formed over a metal interconnect layer which, in the illustrative embodiment shown in FIG. 4 is formed as a damascene copper interconnect layer or a deposited tungsten via 84 in an interlayer dielectric layer 82. The damascene copper interconnect layer or deposited tungsten via 84 formed in the interlayer dielectric layer 82 is surrounded by a Cu or W barrier layer 86 as is known in the art. Persons of ordinary skill in the art will appreciate that the metal interconnect layer could also be a conventional deposited metal interconnect layer.

[0045] The tungsten via or damascene copper metal line 84 is shown surrounded by a barrier layer 86. A CMP stop layer may be formed over the top of the inter-metal dielectric layer 82 and is used in the process employed to planarize the top of damascene copper interconnect layer or tungsten via 84 as is known in the art. SiN or SiC are commonly employed as CMP stop layers.

[0046] Persons of ordinary skill in the art will appreciate that the CMP stop layers may not be required and are optional. Their use or non-use will depend on the CMP technology used by the manufacturer. Some CMP processes may be able to have a timed polish step and do not need the CMP stop layer. This is preferred because it makes the process of depositing the dielectric layers simpler. In addition, the removal of SiN which has a dielectric constant of 7 and its replacement with silicon oxide which has a dielectric constant of 4 is preferred and will reduce the coupling capacitance of the metal layers, thus improving the speed performance of the device.

[0047] In the ReRAM device depicted in FIG. 4, a layer 88 of a barrier metal is formed above the tungsten via or damascene copper metal line 84 (or other metal interconnect line). The barrier metal layer 88 may be formed from a material such as Ta, TaN, Ti or TiN, W or other suitable material.

[0048] It is known that electrons can be made to tunnel across an ultra-thin dielectric layer, i.e., one that is less than 35 . According to one aspect of the present invention, an tunneling dielectric layer 102 formed from a material such as SiN, is deposited over the barrier metal layer 88, as an ultra-thin layer. This tunneling dielectric layer will reduce leakage in the off state. During the on state it will limit current flow through the ReRAM, although current sufficient to bias the switch node to the proper voltage will still flow.

[0049] A solid electrolyte layer 90 is formed above tunneling dielectric layer 102. The solid electrolyte layer 90 may be formed from a deposited layer of amorphous silicon. Other materials, such as chalcogenides (e.g., Ge.sub.2Sb.sub.2Te.sub.5 or AgInSbTe), NiO or TiO2, Ge or GeSe, TaOx may also be used. The thickness of the solid electrolyte layer 90 may range from about 50 to about 500 , a typical thicknesses being from about 200 to about 300 .

[0050] An ion source layer 92 is formed over the solid electrolyte layer 90 and is formed from a material such as Ag. Other materials, such as copper, and TiO.sub.2 may be used. The thickness of the ion source layer 92 may range from about 100 to about 2,000 , typical thicknesses being from about 300 to about 500 .

[0051] The stack of layers 88, 102, 90, and 92 is etched to form an aligned stack using conventional stack etching techniques. A dielectric barrier layer 94 formed from a material such as deposited SiN or SiC is formed over the defined stack. A via is formed in the dielectric barrier layer 94 to expose the upper surface of ion source layer 92. A barrier metal layer 100 is then formed over the dielectric barrier layer and makes contact with ion source layer 92. A top metal may be formed as a damascene copper or tungsten plug 98 or from Al or another metal used for interconnect layers in integrated circuits. The embodiment shown in FIG. 4 employs another inter-layer dielectric 96 in which the tungsten via or damascene copper metal line 98 is formed.

[0052] During the on state, the electrolyte is well populated with ions and has a relatively low resistance, allowing electrons to flow through it. Because electrons will tunnel through the tunneling dielectric layer 102, the tunneling dielectric layer 102 will act as a resistance. It is expected that, for a 1V cell, about 1 A will pass through the dielectric tunneling layer 102.

[0053] During the off state, the electrolyte layer 90 is not well populated with ions and has a relatively high resistance, so there will be few electrons flowing through it. Under these conditions, the tunneling dielectric layer 102 will then act as a very high resistance, thus reducing the off state leakage. It is important to note that the current through the tunneling dielectric 102 is a function of the number of electrons present at the potential barrier and the e-field across the barrier. The tunneling dielectric layer 102 presents a high resistance during the off state because the lower population of electrons at the potential barrier in the tunneling dielectric 102 causes a lower probability of electron tunneling. Conversely the tunneling dielectric 102 presents a much lower resistance during the on state because the presence of more electrons as a result of the ion density in the solid electrolyte 90 increases the probability of electron tunneling.

[0054] Referring now to FIG. 5, a diagram shows a cross-sectional view of an illustrative ReRAM device 120 in accordance with another aspect of the present invention. According to the aspect of the present invention illustrated in FIG. 5, ReRAM device 120 is in some respects similar to the embodiment depicted in FIG. 4. Thus ReRAM device 120 is formed over a damascene copper interconnect layer or a deposited tungsten via 84 in an interlayer dielectric layer 82 (or over any other metal interconnect structure) and includes a stacked structure including a barrier metal layer 88, a solid electrolyte layer 90, and an ion source layer 92.

[0055] A thin dielectric layer 104 formed from a material such as SiO.sub.2 is placed between the top of the solid electrolyte layer 90 and the ion source layer 92. Other materials, such as SiN, doped SiO.sub.2, SiOxyNitride, may be used. The thickness of the thin dielectric layer 104 may range from about 5 to about 100 , typical thicknesses being from about 20 to about 30 .

[0056] The use of the thin dielectric layer 104 will reduce leakage of ReRAM device 120 in the off state, since the area of the metal/electrolyte interconnect is reduced, as described below.

[0057] In the off state, some electrons do pass through the solid electrolyte layer 90 as leakage. The number of electrons that get through the solid electrolyte layer 90 is a function of the interface between the ion source layer 92 and the solid electrolyte layer 90. Given the present state of integrated circuit fabrication technology, a square area of interface between ion source layer 92 and the solid electrolyte layer 90 having an area of about 32 nm32 nm is possible to achieve. By placing the thin dielectric layer 104 at this interface, a portion of the dielectric layer is punched through during the initial programming process. In particular, during initial programming some tunneling occurs, but some destructive punch through also occurs.

[0058] Because of the nature of the punch-through mechanism, the initial punch-through process occurs over only a portion of the thin dielectric layer 104, since the punch through follows the path of least resistance. This results in a reduced area of contact (much less than 32 nm32 nm) between the solid electrolyte layer 90 and the ion source layer 92.

[0059] Referring now to FIG. 6, a diagram shows a cross-sectional view of an illustrative ReRAM device 130 in accordance with another aspect of the present invention.

[0060] ReRAM device 130 is a combination of the embodiments depicted in FIG. 4 and FIG. 5. ReRAM device 130 is formed over a metal layer 84 (shown for illustration as a damascene copper or tungsten plug structure) and includes a stacked structure including a barrier metal layer 88, an tunneling dielectric layer 102, a solid electrolyte layer 90, a thin dielectric layer 104, and an ion source layer 92.

[0061] ReRAM device 130 thus includes both the ultra-thin dielectric tunneling layer 102 of FIG. 5 and the thin dielectric layer 104 of FIG. 5.

[0062] Referring now to FIGS. 7A through 7G, cross-sectional views of an illustrative ReRAM device depicting an illustrative process for fabricating the memory devices described above by showing the structure resulting after various steps in the semiconductor fabrication process have been performed.

[0063] The processes for fabricating the ReRAM devices shown in FIG. 4 through FIG. 6 include individual conventional deposition, etching, and other process steps performed in CMOS processes for fabricating integrated circuit devices.

[0064] FIG. 7A shows the structure resulting after prior steps have been performed to form a damascene copper metal line or tungsten plug 84 having a barrier metal lining 86 in an inter-layer dielectric layer 82 and to planarize the upper surface of the structure using known techniques such as CMP planarization.

[0065] Next, as shown in FIG. 7B, barrier metal layer 88, ultra-thin tunneling dielectric layer 102, solid electrolyte layer 90, and ion source layer 92 are blanket deposited over the planarized surface of inter-layer dielectric layer 82 and damascene copper metal line or tungsten plug 84. FIG. 7B shows the structure resulting after barrier metal layer 88, ultra-thin tunneling dielectric layer 102, solid electrolyte layer 90, and ion source layer 92 have been blanket deposited.

[0066] Next, as shown in FIG. 7C the surface is masked and an etching step is performed to etch the stack including barrier metal layer 88, tunneling dielectric layer 102, solid electrolyte layer 90, and ion source layer 92. FIG. 7C shows the etching step being performed through the photoresist layer 140.

[0067] Next, as shown in FIG. 7D, the photoresist layer 140 is removed and the resulting structure includes the stack of barrier metal layer 88, ultra-thin tunneling dielectric layer 102, solid electrolyte layer 90, and ion source layer 92.

[0068] Next, as shown in FIG. 7E, a dielectric barrier layer 94 is formed to seal and isolate the side edges of the stack including barrier metal layer 88, ultra-thin tunneling dielectric layer 102, solid electrolyte layer 90, and ion source layer 92. An interlayer dielectric layer 96 is deposited over dielectric barrier layer 94. A masking step is performed to form photoresist layer 142 to define an aperture in regions 144 for the upper metal layer. An etching step is performed to expose the top surface of ion source layer 92. FIG. 7E shows the etching step being performed through the photoresist layer 142.

[0069] Next, as shown in FIG. 7F, the photoresist layer 142 is removed and the top surface of ion source layer 92 is exposed at the bottom of aperture 144.

[0070] Next, as shown in FIG. 7G, aperture 144 is lined with a barrier metal layer 100 and a damascene copper layer or a tungsten plug 98 is formed in aperture 144. FIG. 7G shows the structure remaining after these process steps have been performed. Persons of ordinary skill in the art will appreciate that a conventional metal line, formed from a blanket deposited and etched layer of Al can be utilized instead of a damascene copper layer or a tungsten plug 98.

[0071] Persons of ordinary skill in the art will readily observe that FIGS. 7A through 7G illustrate an exemplary process for forming the ReRAM device structure of FIG. 4. Such ordinarily skilled persons will readily understand that the embodiments of the ReRAM device depicted in FIG. 5 and FIG. 6 can be fabricated using essentially the same process, the differences being that a deposition step for forming the thin dielectric layer 104 between the electrolyte layer 90 and the ion source layer 92 is performed either instead of or in addition to the deposition step for forming ultra-thin tunneling dielectric layer 102, depending on whether it is desired to fabricate the ReRAM device of FIG. 5 or the ReRAM device of FIG. 6.

[0072] Referring now to FIG. 8, a schematic diagram depicts four illustrative ReRAM cells in an array to show a method for programming and erasing the ReRAM cells. The cells are identified by row and column location, R1C1 being the cell in the first row and first column, R1C2 being the cell in the first row second column, R2C1 being the cell in the second row and first column, and R2C2 being the cell in the second row second column.

[0073] The table of FIG. 9 shows the voltages to apply to the column lines, bit lines and word lines to perform the operations associated with each column of the table. The reference numeral designations used for the elements in FIG. 8 are the reference numerals used for these elements in FIG. 1, followed by -x-y where x is the row of the array containing the element and y is the column of the array containing the element.

[0074] The voltages listed in FIG. 9 are nominal values and may vary in different designs as a function of the technology used. For example, 2.5V is applied to one of WL1 and WL2 for certain operations. The voltage actually necessary to perform these operations depends on the V.sub.t of the programming transistors 28 (e.g., about 0.4V) and will therefore normally be less than 2.5V, but 2.5V is chosen because it is a voltage that usually present anyway in the integrated circuit and so is a convenient choice. The same is true for the 1.8V voltage values, which are normally present in integrated circuits, 1.8V being a typical voltage available to overdrive transistor gates to eliminate the V.sub.t voltage drop across a turned on transistor.

[0075] Before programming any of the ReRAM cells, they are all erased by placing both of the ReRAM devices in the ReRAM cells to their off states.

[0076] Column A represents the voltages applied to erase (turn off) all upper ReRAM devices in the cells. When the voltages listed in column A of the table are applied to the array of FIG. 5,each of the programing transistors 28-1-1, 28-1-2, 28-2-1, and 28-2-2 in the four ReRAM memory cells R1C1, R1C2, R2C1, and R2C2 has 0V on its source and 1.8V on its gate and is turned on, placing each switch node 22-1-1, 22-1-2, 22-2-1, and 22-2-2 at 0V. The upper bitlines BL1 and BL2 each have 1.8V on them. Thus, the upper ReRAM devices 12-1-1, 12-1-2, 12-2-1, and 12-2-2 each have 1.8V across them, allowing current to flow through them to draw ions out of the electrolyte layer back to the ion source layer. The lower bitlines BL1! and BL2! each have 0V on them. Thus, the lower ReRAM devices 14-1-1, 14-1-2, 14-2-1, and 14-2-2 each have 0V across them, thus not allowing any current to flow through them.

[0077] Column B represents the voltages applied to erase all lower ReRAM devices in the cells. When the voltages listed in column B of the table are applied to the array of FIG. 5, each of the programing transistors 28-1-1, 28-1-2, 28-2-1, and 28-2-2 in the four ReRAM memory cells R1C1, R1C2, R2C1, and R2C2 has 1.8V on its source and 2.5V on its gate and is turned on, placing each switch node 22-1-1, 22-1-2, 22-2-1, and 22-2-2 at 1.8V. The lower bitlines BL1! and BL2! each have 0V on them. Thus, the lower ReRAM devices 14-1-1, 14-1-2, 14-2-1, and 14-2-2 each have 1.8V across them, allowing current to flow through them to draw ions out of the electrolyte layer back to the ion source layer. The upper bitlines BL1 and BL2 each have 1.8V on them. The upper ReRAM devices 12-1-1, 12-1-2, 12-2-1, and 12-2-2 thus each have 0V across them, not allowing any allowing current to flow through them.

[0078] Once all of the ReRAM cells have been erased, each ReRAM cell may be programmed to turn it on thereby turning on its associated switch transistor or to turn it off thereby turning off its associated switch transistor. As described below, the programming is accomplished responsive to the proper bias of the bitlines, word lines and respective programming transistor.

[0079] Column C represents the voltages applied to turn on the ReRAM cell at R1C1 by turning on the upper ReRAM device 12-1-1 in that cell to pull up the switch node to turn on the switch transistor. When the voltages listed in column C of the table are applied to the array of FIG. 5, programming transistor 28-1-1 has 1.8V on its source, 2.5V on its gate and will be turned on, driving the switch node 22-1-1 in ReRAM cell R1C1 to 1.8V. Bitline BL1 has 0V on it, and ReRAM device 12-1-1 will therefore have a voltage of 1.8V across it, the bottom end being more positive than the top end. This is the condition for programming ReRAM device 12-1-1. ReRAM device 14-1-1 will also have a voltage of 1.8V across it, but the bottom end is more negative than the top end and therefore ReRAM device 14-1-1 will not be programmed.

[0080] Programming transistor 28-1-2 has 0V on its source, 2.5V on its gate and will be turned on, driving the switch node 22-1-2 in ReRAM cell R1C2 to 0V. Because both BL2 and BL2! have 0V on them, both ReRAM devices 12-1-2 and 14-1-2 in ReRAM cell R1C2 will have 0V across them and will not be programmed.

[0081] Programming transistors 28-2-1 and 28-2-2 each has 0V on its gate and will be turned off. The switch nodes 22-2-1 and 22-2-2 in ReRAM cells R2C1 and R2C2 will be either floating or at the potential on both bitlines BL2 and BL2! if one of the ReRAM devices in those cells has been programmed. Since bitlines BL2 and BL2! are both at 0V, no ReRAM devices in cells R2C1 and R2C2 in the second row of the array will be programmed.

[0082] Column D represents the voltages applied to turn off the ReRAM cell at R1C1 by turning on the lower ReRAM device 14-1-1 in that cell to pull down the switch node 22-1-2 to turn off the associated switch transistor. When the voltages listed in column D of the table are applied to the array of FIG. 5, programming transistor 28-1-1 has 0V on its source, 2.5V on its gate and will be turned on, driving the switch node 22-1-1 in ReRAM cell R1C1 to 0V. Bitline BL1 has 1.8V on it, and ReRAM device 14-1-1 will have a voltage of 1.8V across it, the bottom end being more positive than the top end. This is the condition for programming ReRAM device 14-1-1. ReRAM device 12-1-1 will also have a voltage of 1.8V across it, but the bottom end is more negative than the top end and therefore ReRAM device 12-1-1 will not be programmed.

[0083] Programming transistor 28-1-2 has 1.8V on its source, 2.5V on its gate and will be turned on, driving the switch node 22-1-2 in ReRAM cell R1C2 to 1.8V. Because BL2 and BL2! both have 1.8V on them, both ReRAM devices 12-1-2 and 14-1-2 in ReRAM cell R1C2 will have 0V across them and will not be programmed.

[0084] Programming transistors 28-2-1 and 28-2-2 each has 0V on its gate and will be turned off. The switch nodes 22-2-1 and 22-2-2 in ReRAM cells R2C1 and R2C2 will be either floating or at the potential on both bitlines BL2 and BL2! if one of the ReRAM devices in those cells has been programmed. All bitlines are at 1.8V, but because the switch nodes 22-2-1 and 22-2-2 are either floating or at the potential of bitlines BL2 and BL!2, no ReRAM devices in cells R2C1 and R2C2 in the second row of the array will be programmed.

[0085] Column E represents the voltages applied to turn on the ReRAM cell at R1C2 by turning on the upper ReRAM device 12-1-2 in that cell to pull up the switch node 22-1-2 to turn on the associated switch transistor. The conditions are similar to those for column C, except that the source of programming transistor 28-1-2 is now at 1.8V and is turned on (and the source of transistor 28-1-1 is now at 0V) and ReRAM device 12-1-2 is programmed because it has 0V at its top end and 1.8V on its bottom end. ReRAM device 14-1-2 will also have a voltage of 1.8V across it, but its bottom end is more negative than its top end and therefore ReRAM device 14-1-2 will not be programmed. Persons of ordinary skill in the art will appreciate that the ReRAM cells in the second row of the array are not programmed for the reasons set forth in the explanation of the column C conditions.

[0086] Column F represents the voltages applied to turn off the ReRAM cell at R1C2 by turning on the lower ReRAM device 14-1-2 in that cell to pull down the switch node 22-1-2 to turn off the associated switch transistor. When the voltages listed in column F of the table are applied to the array of FIG. 9, programming transistor 28-1-2 has 0V on its source, 2.5V on its gate and will be turned on, driving the switch node 22-1-2 in ReRAM cell R1C2 to 0V. Bitline BL2 has 1.8V on it, and ReRAM device 14-1-2 will have a voltage of 1.8V across it, since bitline BL2 has 1.8V on it, the bottom end being more positive than the top end. This is the condition for programming ReRAM device 14-1-2. ReRAM device 12-1-2 will also have a voltage of 1.8V across it, but the bottom end is more negative than the top end and therefore ReRAM device 12-1-2 will not be programmed.

[0087] Programming transistor 28-1-1 has 1.8V on its source, 2.5V on its gate and will be turned on, driving the switch node 22-1-1 in ReRAM cell R1C1 to 1.8V. Because BL1 and BL1! both have 1.8V on them, both ReRAM devices 12-1-1 and 14-1-1 in ReRAM cell R1C1 will have 0V across them and will not be programmed.

[0088] Programming transistors 28-2-1 and 28-2-2 each has 0V on its gate and will be turned off. The switch nodes 22-2-1 and 22-2-2 in ReRAM cells R2C 1 and R2C2 will be either floating or at the potential on both bitlines BL1 and BL1! if one of the ReRAM devices in those cells has been programmed. All bitlines are at 1.8V, but because the switch nodes 22-2-1 and 22-2-2 are either floating or at the potential of bitlines BL1 and BL2!, no ReRAM devices in cells R2C1 and R2C2 in the second row of the array will be programmed.

[0089] Column G represents the voltages applied to turn on the ReRAM cell at R2C1 by turning on the upper ReRAM device 12-2-1 in that cell to pull up the switch node 22-2-1 to turn on the associated switch transistor. Column H represents the voltages applied to turn off the ReRAM cell at R2C1 by turning on the lower ReRAM device 14-2-1 in that cell to pull down the switch node 22-2-1 to turn off the associated switch transistor. Column I represents the voltages applied to turn on the ReRAM cell at R2C2 by turning on the upper ReRAM device 12-2-2 in that cell to pull up the switch node 22-2-2 to turn on the associated switch transistor. Column J represents the voltages applied to turn off the ReRAM cell at R2C1 by turning on the lower ReRAM device 14-2-2 in that cell to pull down the switch node 22-2-1 to turn off the associated switch transistor. From the conditions described with reference to columns C through F for programming the ReRAM cells in the first row of the array to either their on or off states, persons of ordinary skill in the art will readily appreciate from FIG. 8 and FIG. 9 how the programming of ReRAM cells R2C1 and R2C2 in the second row of the array is accomplished.

[0090] While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.