GATE DRIVING CIRCUIT AND DISPLAY DEVICE USING THE SAME

Abstract

Provided are a gate driving circuit and a display device using the same. The gate driving circuit includes: a plurality of stages, each stage sequentially receiving a phase-delayed clock and sequentially generating an output. An nth stage (n is a positive integer) includes: a first inverter including a first PMOS transistor and a first NMOS transistor; a second inverter including a second PMOS transistor and a second NMOS transistor; and a reset signal line connected to a source terminal of the second NMOS transistor and supplying a reset signal to initiate the nth stage.

Claims

1. A gate driving circuit comprising: a plurality of stages including an nth stage (n is a positive integer), each stage sequentially receiving a phase-delayed clock and sequentially generating an output, wherein the nth stage includes: a first inverter including a first PMOS transistor and a first NMOS transistor; a second inverter including a second PMOS transistor and a second NMOS transistor; and a reset signal line connected to a source terminal of the second NMOS transistor and supplying a reset signal to initiate the nth stage.

2. The gate driving circuit according to claim 1, wherein the reset signal discharges a Q node Q to a low-potential voltage VGL and charges a Q Bar node QB to a high-potential voltage VGH.

3. The gate driving circuit according to claim 1, wherein the reset signal is an inverted phase reset signal which increases from a low-potential voltage VGL to a high-potential voltage VGH and then decreases to the low-potential voltage VGL.

4. The gate driving circuit according to claim 1, wherein the first inverter and the second inverter constitute a latch as being connected by a closed loop-shaped feedback circuit.

5. The gate driving circuit according to claim 4, wherein the latch controls a voltage to be applied to the Q Bar node QB in a state in which a voltage applied to the Q node Q is inverted.

6. The gate driving circuit according to claim 2, wherein the first PMOS transistor includes a gate connected to the Q node, a drain connected to the QB node, and a source connected to a high-potential voltage line, the first NMOS transistor includes a gate connected to the Q node, a drain connected to the QB node, and a source connected to a low-potential voltage line, the second PMOS transistor includes a gate connected to the QB node, a drain connected to the Q node, and a source connected to the high-potential voltage line, and the second NMOS transistor includes a gate connected to the QB node, a drain connected to the Q node, and a source connected to the reset signal line.

7. The gate driving circuit according to claim 2, wherein the nth stage further includes: a first switch receiving a carry signal from an n1th stage (n is a positive integer) and controlling the QB node to a low voltage and the Q node to a high voltage when the carry signal has a high voltage; a second switch receiving a carry signal from an n+1th stage (n is a positive integer) and controlling the QB node to a high voltage and the Q node to a low voltage when the carry signal has a high voltage; and a buffer outputting the clock as an output voltage when a voltage of the Q node is a high voltage and outputting a low voltage as an output voltage when a voltage of the QB node is a high voltage.

8. The gate driving circuit according to claim 7, wherein the buffer includes: a pull-up transistor supplying the clock to an output terminal in response to the voltage of the Q node to increase the output voltage; and a pull-down transistor supplying the low voltage to the output terminal in response to the voltage of the QB node to decrease the output voltage.

9. The gate driving circuit according to claim 8, wherein the pull-up transistor is a transmission gate.

10. The gate driving circuit according to claim 9, wherein the transmission gate includes: a third PMOS transistor including a gate connected to the QB node, a drain connected to the output terminal, and a source to which the clock is input; and a third NMOS transistor including a gate connected to the Q node, a source connected to the output terminal, and a drain to which the clock is input.

11. The gate driving circuit according to claim 8, wherein the pull-down transistor is a fourth NMOS transistor including a gate connected to the QB node, a drain connected to the output terminal, and a source connected to the low-potential voltage line.

12. The gate driving circuit according to claim 7, wherein the first switch is a fifth NMOS transistor including a gate connected to a carry signal transmission line from the n1th stage (n is a positive integer), a drain connected to the QB node, and a source connected to the low-potential voltage line.

13. The gate driving circuit according to claim 7, wherein the second switch is a sixth NMOS transistor including a gate connected to a carry signal transmission line from the n+1th stage (n is a positive integer), a drain connected to the Q node, and a source connected to the low-potential voltage line.

14. A display device comprising: a display region including a plurality of pixels on a substrate: a non-display region disposed at least one side of the display region; and a GIP (Gate In Panel) circuit on the non-display region, electrically connected to the plurality of pixels, Wherein the GIP circuit comprises: a plurality of stages including an nth stage (n is a positive integer), each stage sequentially receiving a phase-delayed clock and sequentially generating an output, wherein the nth stage includes: a first inverter including a first PMOS transistor and a first NMOS transistor; a second inverter including a second PMOS transistor and a second NMOS transistor; and a reset signal line connected to a source terminal of the second NMOS transistor and supplying a reset signal to initiate the nth stage.

15. The display device according to claim 14, wherein the reset signal discharges a Q node Q to a low-potential voltage VGL and charges a Q Bar node QB to a high-potential voltage VGH.

16. The display device according to claim 14, wherein the reset signal is an inverted phase reset signal which increases from a low-potential voltage VGL to a high-potential voltage VGH and then decreases to the low-potential voltage VGL.

17. The display device according to claim 14, wherein the first inverter and the second inverter constitute a latch as being connected by a closed loop-shaped feedback circuit.

18. The display device according to claim 14, wherein the latch controls a voltage to be applied to the Q Bar node QB in a state in which a voltage applied to the Q node Q is inverted.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0033] FIG. 1 is a waveform diagram illustrating a reset operation period of a shift register in a gate driving circuit of a conventional display device;

[0034] FIG. 2 is a block diagram illustrating a driving circuit of a display device according to an exemplary embodiment of the present disclosure;

[0035] FIG. 3 is a block diagram illustrating a relationship between a plurality of stages of a gate driving circuit and a control signal of the gate driving circuit according to an exemplary embodiment of the present disclosure;

[0036] FIG. 4 is a circuit diagram specifically illustrating an nth stage STn illustrated in FIG. 3;

[0037] FIG. 5 is a circuit diagram illustrating the nth stage STn illustrated in FIG. 3 as a configuration of switch elements; and

[0038] FIG. 6 is a waveform diagram illustrating a reset operation period of the nth stage illustrated in FIG. 4.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

[0039] Advantages and features of the present disclosure, and methods for accomplishing the same will be more clearly understood from exemplary embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following exemplary embodiments but may be implemented in various different forms. The exemplary embodiments are provided only to complete disclosure of the present disclosure and to fully provide a person having ordinary skill in the art to which the present disclosure pertains with the category of the disclosure, and the present disclosure will be defined by the appended claims.

[0040] The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Further, in the following description, a detailed explanation of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. The terms such as including, having, and consist of used herein are generally intended to allow other components to be added unless the terms are used with the term only. Any references to singular may include plural unless expressly stated otherwise.

[0041] Components are interpreted to include an ordinary error range even if not expressly stated.

[0042] When the position relation between two parts is described using the terms such as on, above, below, and next, one or more parts may be positioned between the two parts unless the terms are used with the term immediately or directly.

[0043] When an element or layer is referred to as being on another element or layer, it may be directly on the other element or layer, or intervening elements or layers may be present.

[0044] Although the terms first, second, and the like are used for describing various components, these components are not confined by these terms. These terms are merely used for distinguishing one component from the other components. Therefore, a first component to be mentioned below may be a second component in a technical concept of the present disclosure.

[0045] Throughout the whole specification, the same reference numerals denote the same elements.

[0046] Since size and thickness of each component illustrated in the drawings are represented for convenience in explanation, the present disclosure is not necessarily limited to the illustrated size and thickness of each component.

[0047] The features of various embodiments of the present disclosure can be partially or entirely bonded to or combined with each other and can be interlocked and operated in technically various ways as can be fully understood by a person having ordinary skill in the art, and the embodiments can be carried out independently of or in association with each other.

[0048] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to FIG. 2 through FIG. 6.

[0049] FIG. 2 is a block diagram illustrating a driving circuit of a display device according to an exemplary embodiment of the present disclosure.

[0050] Referring to FIG. 2, a display device according to an exemplary embodiment of the present disclosure includes a display panel 160, a data driving circuit 120, a level shifter 150, a shift register 130, a PCB 140, and a timing controller 110.

[0051] The display panel 160 includes data lines DL and gate lines GL intersecting with each other and pixels disposed in a matrix shape. The display panel 160 may be a liquid crystal display (LCD), an organic light emitting diode (OLED), an electrophoretic display (EPD), or the like.

[0052] The data driving circuit 120 includes a plurality of source drive ICs. The data driving circuit 120 receives digital video data RGB from the timing controller 110. The data driving circuit 120 converts the digital video data RGB into a gamma correction voltage to generate a data voltage, in response to a source timing control signal from the timing controller 110. Then, the data driving circuit 120 supplies the data voltage to the data lines of the display panel 160 in synchronization with a gate pulse. The data driving circuit 120 may be connected to the data lines DL of the display panel 160 through a Chip On Glass (COG) process or a Tape Automated Bonding (TAB) process.

[0053] A gate driving circuit includes the level shifter 150 and the shift register 130 connected between the timing controller 110 and the gate lines GL of the display panel 160.

[0054] The level shifter 150 level-shifts a transistor-transistor-logic (TTL) level voltage of a shift clock CLK input from the timing controller 110 to a high voltage VGH and a low voltage VGL. In the following exemplary embodiment of the present disclosure, driving using the shift clock CLK will be exemplified.

[0055] The shift register 130 includes stages which shift a start pulse VST according to the shift clock CLK and sequentially output a carry signal and a gate pulse Gout.

[0056] The gate driving circuit may be directly formed on a lower substrate of the display panel 160 by a Gate In Panel (GIP) method. According to the GIP method, the level shifter 150 may be mounted on the PCB 140 and the shift register 130 may be formed on the lower substrate of the display panel 160.

[0057] The timing controller 110 receives digital video data RGB from an external host computer through an interface such as a Low Voltage Differential Signaling (LVDS) interface, a Transition Minimized Differential Signaling (TMDS) interface, or the like. The timing controller 110 transmits the digital video data RGB input from the host computer to the source drive ICs 120.

[0058] The timing controller 110 receives timing signals, such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK from the host computer through an LVDS or TMDS interface receiving circuit. The timing controller 110 generates timing control signals to control an operation timing of the data driving circuit and the gate driving circuit based on the timing signals from the host computer. The timing control signals include a scan timing control signal to control an operation timing of the gate driving circuit and a data timing control signal to control an operation timing of the data driving circuit 120 and the polarity of a data voltage.

[0059] A gate timing control signal includes a start pulse VST, a shift clock CLK, and a gate output enable signal GOE. The start pulse VST is input to the shift register 130 and controls a shift start timing.

[0060] The shift clock CLK is level-shifted by the level shifter 150 and then input to the shift register 130 and used as a clock signal for shifting the start pulse VST. The gate output enable signal GOE controls an output timing of the gate shift register 130.

[0061] The data timing control signal includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, and a source output enable signal SOE, and the like. The source start pulse SSP controls a shift start timing of the source drive ICs 120. The source sampling clock SSC is a clock signal that controls a sampling timing of data within the source driver ICs 120 based on a rising or falling edge thereof.

[0062] FIG. 3 is a block diagram illustrating a relationship between a plurality of stages of a gate driving circuit and a control signal of the gate driving circuit according to an exemplary embodiment of the present disclosure.

[0063] The gate driving circuit may be formed on one edge or both edges of the display panel 160 outside a pixel array. The GIP-type gate driving circuit and the pixel array may be formed on the substrate of the display panel 160 at the same time. The gate driving circuit includes a plurality of stages ST1 to STn to which the start pulse VST and the shift clock CLK are input.

[0064] The stages ST1 to STn generate outputs in response to the start pulse VST and shift the outputs according to the shift clock CLK.

[0065] A shift register SR according to an exemplary embodiment of the present disclosure is configured as a latch circuit. Each of the stages ST1 to STn of the shift register SR includes a Q node Q for charging a gate line, a Q Bar node QB for discharging the gate line, and a switch circuit connected to the Q node Q and the Q Bar node QB. The switch circuit charges the Q node Q in response to a start pulse or an output of a previous stage to increase a voltage of the gate line. Then, the switch circuit discharges the Q Bar node QB in response to an output of a subsequent stage or a reset signal. The switch circuit includes TFTs of configuration as a metal oxide semiconductor field effect transistor (MOSFET).

[0066] If the shift register SR is powered on, potentials of the Q node Q and the Q Bar node QB are randomly set to a high-potential voltage VGH or a low-potential voltage VGL. Therefore, it may be necessary to reset the shift register SR to a state for an operation of the shift register SR. That is, the Q node Q is maintained at the low-potential voltage VGL and the Q Bar node QB is set to the high-potential voltage VGH.

[0067] Referring to FIG. 3, the shift register SR according to an exemplary embodiment of the present disclosure includes a plurality of stages ST1 to STn (n is a natural number equal to or greater than 2) connected in a cascade manner. The stages ST1 to STn output first to nth gate pulses Gout1 to Goutn, respectively. While the gate pulses Gout1 to Goutn are applied to the gate lines of the display device, the gate pulses Gout1 to Goutn also serve as first carry signals Gout_pre and second carry signals Gout_post transferred to a previous stage and a subsequent stage. In the following, the term previous stage refers to a stage positioned above a reference stage.

[0068] For example, on the basis of a kth stage STk (k is a natural number satisfying 1<k<n), the previous stage refers to any one of a first stage ST1 to a k1th stage ST (k1).

[0069] Further, the term subsequent stage refers to a stage positioned under the reference stage. For example, on the basis of the kth stage STk (1<k<n), the subsequent stage refers to any one of a k+1th stage ST (k+1) to an nth stage.

[0070] Referring to FIG. 3, the shift register according to an exemplary embodiment of the present disclosure subsequently outputs gate pulses Gout(1) to Gout(n). In order to do so, sequentially delayed shift clocks CLK are input to the first stage ST1 to the nth stage STn.

[0071] The stages ST1 to STn of the shift register SR start outputting the gate pulses Gout1 to Goutn in response to the start pulse VST and shift the gate pulses Gout1 to Goutn in response to the shift clock CLK. The gate pulses Gout1 to Goutn respectively output from the stages ST1 to STn are supplied to the gate lines while being input to following stages as the first carry signals Gout_Pre. The first carry signals Gout_Pre are used for pre-charging the Q node in order for the stages ST1 to STn to respectively generate outputs. However, the first carry signal Gout_Pre is not input to the first stage ST1, but the gate start pulse VST is input to the first stage ST1.

[0072] Further, after generating output signals, the stages ST1 to STn respectively receive the second carry signals Gout_Post for discharging the Q node. However, the second carry signal Gout_Post is not input to the nth stage STn which is the last stage.

[0073] Referring to FIG. 3, the gate shift register according to an exemplary embodiment of the present disclosure further includes dummy stages which do not generate outputs but supply the second carry signals Gout_Post to the other stages. For example, an nth stage (n is a positive integer equal to or greater than 2) outputting the last gate pulse is connected to an n+1th stage (or end generator). The n+1th stage does not output a gate pulse but supplies the second carry signal Gout_Post to the nth stage.

[0074] FIG. 4 is a circuit diagram specifically illustrating an nth stage STn illustrated in FIG. 3. FIG. 5 is a circuit diagram illustrating the nth stage STn illustrated in FIG. 3 as a configuration of switch elements.

[0075] In FIG. 4 and FIG. 5, M1, M3, M5, M6, M7, and M9 are implemented with an n-type MOSFET (hereinafter, referred to as NMOS), and M2, M4, and M8 are implemented with a p-type MOSFET (hereinafter, referred to as PMOS). Hereinafter, referring to FIG. 4 and FIG. 5, an nth stage STn of the shift register will be described.

[0076] Referring to FIG. 4 and FIG. 5, an nth stage (STn) 200 of the shift register according to an exemplary embodiment of the present disclosure includes a latch 210 and a buffer 220.

[0077] A reset signal RST, a shift clock CLK, a carry signal Gout_Pre or start pulse VST received from a previous stage, a gate high voltage VGH, and a gate low voltage VGL are input to each shift register 130. The first carry signal Gout_Pre input to an nth stage except a first stage is an output Gout of an n1th stage. The first carry signal Gout_Pre is not input to the first stage ST1, but the start pulse VST is input to the first stage ST1.

[0078] The latch 210 includes two inverters INV1 and INV2 connected by a closed loop-shaped feedback circuit and adjusts a voltage of the Q Bar node QB in a state in which a voltage of the Q node Q is inverted.

[0079] The latch 210 is formed by the two inverters configured as CMOS transistors in a feedback manner. The Q Bar node QB of the latch 210 is connected to a drain terminal of a third NMOS M5 and controlled by the first carry signal Gout_Pre connected to a gate terminal of the third NMOS M5. Further, the Q node Q of the latch 210 is connected to a drain terminal of a fourth NMOS M6 and controlled by the second carry signal Gout_post connected to a gate terminal of the fourth NMOS M6.

[0080] A first inverter INV1 includes a first NMOS M1 and a first PMOS M2. A second inverter INV2 includes a second NMOS M3 and a second PMOS M4. The first inverter INV1 supplies an inverted signal of the Q Bar node QB to the Q node Q. The first NMOS M1 includes a gate connected to the Q node Q, a drain connected to the Q Bar node QB, and a source connected to a VGL line VGL_SL. The first PMOS M2 includes a gate connected to the Q node Q, a drain connected to the Q Bar node QB, and a source connected to a VGH line VGH_SL.

[0081] The second inverter INV2 supplies an inverted signal of the Q node Q to the Q Bar node QB. The second NMOS M3 includes a gate connected to the Q Bar node QB, a drain connected to the Q node Q, and a source connected to a reset signal line RST_SL. The second PMOS M4 includes a gate connected to the Q Bar node QB, a drain connected to the Q node Q, and a source connected to the VGH line VGH_SL. The buffer 220 includes a pull-up transistor that supplies a shift clock CLK to an output terminal in response to a voltage of the Q node Q, for the rising of an output voltage Gout. Further, the buffer 220 includes a pull-down transistor that discharges the output terminal in response to a voltage of the Q Bar node QB, for the falling of the output voltage Gout.

[0082] The pull-up transistor includes a transmission gate TG in which a sixth NMOS M9 and a third PMOS M8 are connected in parallel. The pull-down transistor includes a fifth NMOS M7. The output voltage Gout is a gate pulse supplied to a gate line.

[0083] The third PMOS M8 of the transmission gate TG includes a gate connected to the Q Bar node QB, a drain connected to the output terminal, and a source to which the shift clock CLK is input. Further, the sixth NMOS M9 of the transmission gate TG includes a gate connected to the Q node Q, a source connected to the output terminal, and a drain to which the shift clock CLK is input.

[0084] The fifth NMOS M7 includes a gate connected to the Q Bar node QB, a drain connected to the output terminal, and a source connected to the VGL line VGL_SL.

[0085] If a high-potential voltage VGH is applied to the Q node Q, the buffer 220 increases a gate pulse of the shift clock CLK to the output voltage Gout. Further, if the high-potential voltage VGH is applied to the Q Bar node QB, the buffer 220 decreases a low-potential voltage VGL transmitted from the VGL line VGL_SL to the output voltage Gout through the fifth NMOS M7.

[0086] Therefore, in the shift register 130 according to an exemplary embodiment of the present disclosure, the latch includes the two inverters configured in a feedback manner and the Q node Q and the Q Bar node QB are connected to the drains of the NMOS M5 and M6. Thus, the Q node Q and the Q Bar node QB are controlled by the first carry signal Gout_pre and the second carry signal Gout_post. Therefore, the output voltage Gout of the shift register is controlled by a gate pulse of the shift clock CLK.

[0087] FIG. 6 is a waveform diagram illustrating a reset operation period of the nth stage illustrated in FIG. 4.

[0088] Each of the stages ST1 to STn of the shift register includes a Q node Q for charging a gate line, a Q Bar node QB for discharging the gate line, and a switch circuit connected to the Q node Q and the Q Bar node QB. The switch circuit charges the Q node Q in response to a start pulse or an output of a previous stage to increase a voltage of the gate line. Then, the switch circuit discharges the Q Bar node QB in response to an output of a subsequent stage or a reset signal RST.

[0089] Referring to FIG. 6, if the shift register according to an exemplary embodiment of the present disclosure is powered on, the Q node Q and the Q Bar node QB connected to the two inverters INV1 and INV2 connected by the closed loop-shaped feedback circuit are in a random state in which potentials thereof are any one of a high-potential voltage VGH or a low-potential voltage VGL. Then, a reset signal RST is input to the second NMOS M3 of the second inverter INV2. That is, the reset signal is converted from a low voltage VGL to a high voltage VGH through the reset signal line RST_SL and then input to the second NMOS M3 of the second inverter INV2. As a result, the Q node Q is maintained at the low-potential voltage VGL and the Q Bar node QB is set to the high-potential voltage VGH.

[0090] Therefore, if the gate driving circuit is powered on, the Q node Q and the Q Bar node QB are reset to a state for starting an operation of the gate driving circuit.

[0091] When the gate driving circuit according to an exemplary embodiment of the present disclosure starts an operation, the reset signal RST increases from the low-potential voltage VGL to the high-potential voltage VGH and then decreases to the low-potential voltage VGL. Therefore, the reset signal RST has a phase inverted to that of a conventional reset signal. Unlike the conventional reset signal RST which is input to the second PMOS M4 of the first inverter INV1, the inverted phase reset signal RST according to an exemplary embodiment of the present disclosure initiates the shift register of the gate driving circuit using the second NMOS M3 of the second inverter INV2.

[0092] As described above, in the gate driving circuit according to an exemplary embodiment of the present disclosure, an inverted phase reset signal RST is input to each stage to initiate the stage. As a result, a reset period of the shift register of the gate driving circuit has a high reliability. Further, any additional switch is not needed to initiate the shift register.

[0093] The exemplary embodiments of the present disclosure can also be described as follows:

[0094] According to an aspect of the present disclosure, there is provided a gate driving circuit. The gate driving circuit includes: a plurality of stages which sequentially receives a phase-delayed clock and sequentially generates an output. An nth stage (n is a positive integer) includes: a first inverter including a first PMOS transistor and a first NMOS transistor; a second inverter including a second PMOS transistor and a second NMOS transistor; and a reset signal line connected to a source terminal of the second NMOS transistor and supplying a reset signal to initiate the stage.

[0095] The reset signal may discharge a Q node Q to a low-potential voltage VGL and may charge a Q Bar node QB to a high-potential voltage VGH.

[0096] The reset signal may be an inverted phase reset signal which increases from a low-potential voltage VGL to a high-potential voltage VGH and then decreases to the low-potential voltage VGL.

[0097] The first inverter and the second inverter may constitute a latch as being connected by a closed loop-shaped feedback circuit.

[0098] The latch may control a voltage to be applied to the Q Bar node QB in a state in which a voltage applied to the Q node Q is inverted.

[0099] The first PMOS transistor may include a gate connected to the Q node, a drain connected to the QB node, and a source connected to a high-potential voltage line. The first NMOS transistor may include a gate connected to the Q node, a drain connected to the QB node, and a source connected to a low-potential voltage line. The second PMOS transistor may include a gate connected to the QB node, a drain connected to the Q node, and a source connected to the high-potential voltage line. The second NMOS transistor may include a gate connected to the QB node, a drain connected to the Q node, and a source connected to the reset signal line.

[0100] The nth stage may further include: a first switch receiving a carry signal from an n1th stage (n is a positive integer) and controlling the QB node to a low voltage and the Q node to a high voltage when the carry signal has a high voltage; a second switch receiving a carry signal from an n+1th stage (n is a positive integer) and controlling the QB node to a high voltage and the Q node to a low voltage when the carry signal has a high voltage; and a buffer outputting the clock as an output voltage when a voltage of the Q node is a high voltage and outputting a low voltage as an output voltage when a voltage of the QB node is a high voltage.

[0101] The buffer may include: a pull-up transistor supplying the clock to an output terminal in response to the voltage of the Q node to increase the output voltage; and a pull-down transistor supplying the low voltage to the output terminal in response to the voltage of the QB node to decrease the output voltage.

[0102] The pull-up transistor may be a transmission gate.

[0103] The transmission gate may include: a third PMOS transistor including a gate connected to the QB node, a drain connected to the output terminal, and a source to which the clock is input; and a third NMOS transistor including a gate connected to the Q node, a source connected to the output terminal, and a drain to which the clock is input.

[0104] The pull-down transistor may be a fourth NMOS transistor including a gate connected to the QB node, a drain connected to the output terminal, and a source connected to the low-potential voltage line.

[0105] The first switch may be a fifth NMOS transistor including a gate connected to a carry signal transmission line from the n1th stage (n is a positive integer), a drain connected to the QB node, and a source connected to the low-potential voltage line.

[0106] The second switch may be a sixth NMOS transistor including a gate connected to a carry signal transmission line from the n+1th stage (n is a positive integer), a drain connected to the Q node, and a source connected to the low-potential voltage line.

[0107] It will be apparent to a person having ordinary skill in the art that various changes and modifications can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the technical scope of the present disclosure should not be limited to the descriptions given above but should be determined by the following claims.