METHOD FOR PRODUCING A HIGH-VOLTAGE TRANSISTOR WITH REDUCED FOOTPRINT, AND CORRESPONDING INTEGRATED CIRCUIT

Abstract

An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.

Claims

1. A method, comprising; forming an initial trench in a top surface of a semiconductor substrate; filling the initial trench with a dielectric material; etching an opening that extends through the dielectric material, while leaving an upper insulating sidewall made from the dielectric material, and into the semiconductor substrate to form an extended trench below said initial trench; lining sidewalls and a bottom of the extended trench with a dielectric liner; filling the opening with a gate material to form a gate electrode insulated from the semiconductor substrate by the upper insulating sidewall and the dielectric liner; and forming source and drain regions in the semiconductor substrate on opposite sides of the initial trench.

2. The method of claim 1, wherein the upper insulating sidewall has a first thickness and wherein the dielectric liner has a second thickness that is less than the first thickness.

3. The method of claim 1, wherein the trench has a depth greater than a depth of the source and drain regions.

4. The method of claim 1, wherein lining sidewalls and the bottom of the extended trench with the dielectric liner comprises oxidizing a surface of the semiconductor substrate exposed by the extended trench.

5. A method, comprising; forming a trench in a top surface of a substrate; filling the trench with a dielectric material; etching an initial part of an opening through the dielectric material leaving an upper insulating sidewall made from the dielectric material; etching a further part of said opening extending into the substrate; lining sidewalls and a bottom of the further part of said opening with a dielectric liner; filling the initial part of the opening and the further part of said opening with a gate material to form a gate electrode separated from the substrate by an insulating layer made from the upper insulating sidewall having a first thickness and made from the dielectric liner made having a second thickness less than the first thickness; and forming source and drain regions on opposite sides of the trench.

6. The method of claim 5, wherein the trench has a depth greater than a depth of the source and drain regions.

7. The method of claim 5, wherein lining sidewalls and the bottom of the further part of said opening with the dielectric liner comprises oxidizing a surface of the semiconductor substrate exposed by the further part of said opening.

8. An integrated circuit, comprising: a substrate; a metal oxide semiconductor transistor comprising: a gate region buried in a trench of the substrate and emerging on a top face of the substrate, said gate region surrounded by a dielectric region covering internal walls of the trench; a source region and a drain region situated respectively in the substrate on opposite sides of the trench in a vicinity of said top face; said dielectric region having an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions, and a lower dielectric zone, which is less thick than the upper dielectric zone, situated between a lower part of the gate region and the substrate, wherein the dielectric region comprises a dielectric setback zone between the lower dielectric zone and the upper dielectric zone.

9. A integrated circuit, comprising: a substrate having a top surface; a trench extending into the substrate from the top surface, said trench having sidewalls and a bottom; a dielectric layer covering said sidewalls and bottom; a gate electrode filling said trench and separated from the substrate by said dielectric layer; source and drain regions in said substrate on opposite sides of the trench; wherein said dielectric layer covering said sidewalls has a first sidewall thickness in an upper portion of said trench and a second sidewall thickness in a lower portion of said trench, said second sidewall thickness being greater than said first sidewall thickness; and wherein the dielectric layer includes a dielectric setback zone at a depth of the trench where the thickness of the dielectric layer changes from the first sidewall thickness to the second sidewall thickness.

10. The integrated circuit of claim 9, wherein the dielectric setback zone defines a step change in a lateral width of the dielectric layer thickness.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other advantages and features of the invention will become apparent on studying the detailed description of embodiments, taken as non-limiting examples and illustrated by the attached drawings in which:

[0023] FIGS. 1 to 11 schematically illustrate process steps for a first implementation and embodiment;

[0024] FIGS. 12-16 schematically illustrate process steps for a second implementation and embodiment.

DETAILED DESCRIPTION

[0025] FIG. 1 illustrates a substrate S, for example of silicon and with a thickness E of the order of 2 m, provided for the production of at least one MOS transistor with buried gate TGE according to the invention.

[0026] First of all, a sacrificial layer CS, of SiO.sub.2 type known to those skilled in the art by the name sacrificial oxide SACOX, for example of the order of a few nanometers, is formed by oxidation over the entire top face FS of the substrate S (FIG. 2).

[0027] Next, a layer of silicon nitride CNS is produced in a conventional manner that is known per se.

[0028] This layer of nitride CNS is used then as a hard mask in a subsequent step of anisotropic etching to form a trench T in the substrate S. The opening OUV of the trench T in proximity to the top face FS of the substrate S is, for example, of the order of 200 nm and the depth of the trench T is, for example, of the order of 0.5 m.

[0029] Then, a first dielectric layer CD1, for example of the order of a few nanometers, is formed by re-oxidation, covering the entire internal wall of the trench T (sidewalls and bottom), as can be seen in FIG. 3.

[0030] FIG. 4 illustrates a step of deposition of a sacrificial gate region RSG, for example of poly-silicon, in the trench T, and over the entire substrate S. Such deposition is conventional and known per se.

[0031] In FIG. 5, the sacrificial gate region RSG deposited in the preceding step is partially removed by a conventional step of anisotropic dry etching so as to obtain a lower part PI. This lower part PI is surrounded by a lower dielectric zone ZDI covering the internal wall of the trench T.

[0032] Oxide growth is then used to reform a second dielectric layer CD2 covering the upper zone of the first dielectric layer CD1 and the lower part PI, as illustrated in FIG. 6.

[0033] Then, a partial removal of the second dielectric layer CD2 is performed, by an anisotropic dry etching, in order to obtain an upper dielectric zone ZDS, situated above the lower dielectric zone ZDI, and thicker than the lower dielectric zone ZDI (FIG. 7).

[0034] This difference in thickness between the upper dielectric zone ZDS and the lower dielectric zone ZDI offers a two-fold advantage to the electrical performance levels of the future MOS transistor, as will be seen in more detail hereinbelow.

[0035] For the formation of an upper part PS of the gate region RG, it is possible to completely remove, in a first step, the lower part PI of the gate region RG situated in the trench (FIG. 8) and to form, in a second step, by a conventional gate deposition step, the complete gate region RG comprising the lower part PI surrounded by the lower dielectric zone ZDI and the upper part PS surrounded by the upper dielectric zone ZDS, as shown in FIG. 9.

[0036] As a variant, it would be possible to directly form, by a conventional gate deposition step, an upper part PS of the gate region RG situated above the lower part PI to obtain the same gate region RG as that illustrated in FIG. 9.

[0037] After mechanical-chemical polishing, the gate region RS is obtained (FIG. 10) having a lower part PI and an upper part PS respectively surrounded by the lower ZDI and upper ZDS dielectric zones covering the trench T.

[0038] It should be noted that, since the upper dielectric zone ZDS is thicker than the lower dielectric zone ZDI, the gate region RS comprises a gate setback zone ZDG between the lower part PI and the upper part PS having a step change in lateral width of the gate region.

[0039] Then, conventional steps that are known per se are used to form a source region RS and a drain region RD situated respectively in the substrate S on either side of the trench T in the vicinity of said top face FS of the substrate S.

[0040] An MOS transistor with buried gate TGE is thereby finally obtained, implemented in an integrated circuit IC, as illustrated in FIG. 11.

[0041] It should be noted that the upper dielectric zone ZDS is situated at least partially between the upper part PS of the gate region RG and the source RS and drain RD regions.

[0042] The transistor TGE therefore comprises a buried gate with a U-shaped channel CNL.

[0043] The fact that the upper dielectric zone ZDS is relatively thicker, for example with a maximum thickness of the order of 20 nm, makes it possible to obtain a high breakdown voltage between drain and gate.

[0044] The fact that the lower dielectric zone ZDI remains thin, for example 9 nm thick, over most of the channel CNL ensures good electrical performance levels for the MOS transistor TGE.

[0045] It is possible to obtain an imprint reduction of up to 30% relative to a planar MOS transistor.

[0046] In a possible variant illustrated in FIGS. 12 to 19, an MOS transistor with buried gate TGE can be formed from a conventional shallow trench isolation (STI).

[0047] FIG. 12 illustrates such an isolation trench TS emerging on the top face FS of the substrate S and filled by an insulating material MI, for example silicon dioxide.

[0048] The edges of this isolation trench TS form, de facto, an initial part PINT of the future trench T of the MOS transistor with buried gate TGE.

[0049] First of all an anisotropic etching is used to remove a part of the insulating material MI and a part of the substrate S situated under the initial part PINT so as to obtain an additional part PSUP of the trench T (FIG. 13).

[0050] A part ZDINI of the material MI remains on the edges (sidewalls) of the initial part PINI of the trench T and forms a first dielectric layer.

[0051] Then, oxidation is used to form a second dielectric layer CDS covering the part ZDINI and covering the additional part PSUP of the trench T so as to obtain a lower dielectric zone ZDI covering the additional part PSUP of the trench T and an upper dielectric zone ZDS covering the initial part PINT of the trench T (FIG. 14).

[0052] It will be noted that the dielectric region RDI comprises a dielectric setback zone ZDD between the lower dielectric zone ZDI and the upper dielectric zone ZDS having a step change in the lateral dielectric layer thickness.

[0053] After a conventional step of deposition of the gate material, for example poly-silicon, the gate region RG is formed, surrounded by the upper dielectric zone ZDS in the initial part PINT of the trench T and by the lower dielectric zone ZDI in the additional part PS of the trench T, as illustrated in FIG. 15.

[0054] FIG. 16 shows the MOS transistor with buried gate TGE produced in the integrated circuit IC after the conventional formation of the drain RD and source RS regions.