OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT

Abstract

An optoelectronic component (1) is specified having: an optoelectronic semiconductor chip (2) which generates electromagnetic radiation during operation, and a metallic layer (3) which is arranged on the semiconductor chip (2), wherein an outer surface of the metallic layer (4) has a structuring (5), identification of the component (1) is made possible by means of the structuring (5), and the metallic layer (3) is formed continuously.

Furthermore, a method for producing an optoelectronic component (1) is specified.

Claims

1. Optoelectronic component (1) having, an optoelectronic semiconductor chip (2) which generates electromagnetic radiation during operation, and a metallic layer (3) which is arranged on the semiconductor chip (2), wherein an outer surface of the metallic layer (4) has a structuring (5), identification of the component (1) is made possible by means of the structuring (5), and the metallic layer (3) is formed continuously.

2. Optoelectronic component (1) according to the preceding claim, in which no non-metallic elements are applied on the outer surface of the metallic layer (4).

3. Optoelectronic component (1) according to one of the preceding claims, in which the metallic layer (3) is formed as a heat sink.

4. Optoelectronic component (1) according to one of the preceding claims, in which the metallic layer (3) is formed as a contact layer for electrically contacting the semiconductor chip (2).

5. Optoelectronic component (1) according to one of the preceding claims, in which the metallic layer (3) is a functional layer of the component (1) and has several functions.

6. Optoelectronic component (1) according to one of the preceding claims, in which the semiconductor chip (2) comprises a ridge waveguide (6) having a top surface (6a) and side surfaces (6b) adjacent thereto, and a passivation layer (7) covers the side surfaces of the ridge waveguide (6b).

7. Optoelectronic component (1) according to the preceding claim, in which the metallic layer (3) is in direct contact with the top surface of the ridge waveguide (6a).

8. Optoelectronic component (1) according to one of the two preceding claims, in which the structuring (5) extends without overlapping with the top surface of the ridge waveguide (6a) in top view.

9. Optoelectronic component (1) according to one of the preceding claims, in which the structuring (5) comprises recesses (11).

10. Optoelectronic component (1) according to the preceding claim, in which at least a part of the recesses (11) completely penetrates the metallic layer (3).

11. Optoelectronic component (1) according to one of the two preceding claims, in which at least a part of the recesses (11) partially penetrates the metallic layer (3).

12. Optoelectronic component (1) according to one of the preceding claims, in which the structuring (5) comprises roughened regions (12).

13. Optoelectronic component (1) according to one of the preceding claims, in which the structuring (5) forms a bar code for identifying the component.

14. Optoelectronic component (1) according to one of the preceding claims, in which the metallic layer (3) is a metallic layer stack, and the layer stack comprises a first metallic layer (13) and a second metallic layer (14).

15. Optoelectronic component (1) according to the preceding claim 14, wherein the first metallic layer comprises a metallic adhesion promoter layer (15) and a metallic barrier layer (16).

16. Method for producing an optoelectronic component (1) according to one of the preceding claims, comprising the steps, providing the optoelectronic semiconductor chip (2), applying a metallic layer (3) on the optoelectronic semiconductor chip (2), and producing a structuring (5) on an outer surface of the metallic layer (4).

17. Method according to the preceding claim, wherein the metallic layer (3) is a metallic layer stack, and a first metallic layer (13) and a second metallic layer (14) are subsequently applied on top of one another on the semiconductor chip (2).

18. Method according to the preceding claim 16, wherein at least a part of recesses (11) penetrates the second metallic layer (14) up to the first metallic layer (13), a perturbation layer (20) is applied on the exposed first metallic layer (13), and a further second metallic layer (14a) is applied on the perturbation layer (20).

19. Method according to one of the preceding claims 16 and 17, wherein a stop layer (21) is applied on the metallic layer (3) in regions, and a further metallic layer is galvanically applied on the region not covered by the stop layer (21).

Description

[0078] In the following, the optoelectronic components described herein as well as the method described herein will be explained in more detail with reference to exemplary embodiments and the associated figures. They show:

[0079] FIGS. 1A and 1B schematic top view of an exemplary embodiment of an optoelectronic component described herein, respectively,

[0080] FIGS. 2A and 2B schematic sectional views of an exemplary embodiment of an optoelectronic component described herein,

[0081] FIG. 3 schematic sectional views of an exemplary embodiment of an optoelectronic component described herein,

[0082] FIG. 4 schematic sectional views in top view of an exemplary embodiment of an optoelectronic component described herein,

[0083] FIG. 5 schematic sectional views of an exemplary embodiment of an optoelectronic component described herein,

[0084] FIGS. 6A, 6B, 6C, 6D schematic sectional views of method steps of an exemplary embodiment of a method for producing an optoelectronic component described herein,

[0085] FIGS. 7A, 7B, 7C, 7D schematic sectional views of method steps of an exemplary embodiment of a method for producing an optoelectronic component described herein,

[0086] FIG. 8 schematic top view of an exemplary embodiment of an optoelectronic component described herein.

[0087] Identical, similar or similar acting elements are provided with the same reference signs in the Figures. The Figures and the proportions of the elements shown in the Figures are not to be regarded as true to scale. Rather, individual elements can be shown exaggeratedly large for better representability and/or for better comprehensibility.

[0088] The schematic top views of FIGS. 1A and 1B each show an exemplary embodiment of an optoelectronic component described herein.

[0089] According to FIG. 1A, the optoelectronic component 1 has an optoelectronic semiconductor chip 2 which generates electromagnetic radiation during operation. A metallic layer 3 is arranged on the semiconductor chip 2. An outer surface of the metallic layer 4 has a structuring 5. The structuring 5 is arranged over an edge region of the optoelectronic semiconductor chip 17 or in an edge region of the metallic layer 18. The optoelectronic semiconductor chip 2 and the metallic layer 3 overlap completely in top view. The structuring 5 makes it possible to identify the component 1.

[0090] The structuring is formed by recesses 11 in the metallic layer 3. The recesses 11 penetrate the metallic layer 3 completely in the vertical direction. A bottom surface of the recesses is formed by the optoelectronic semiconductor chip 2. In this case, the metallic layer does not have any recesses 11 which are completely surrounded by the metallic layer 3 and which completely penetrate the metallic layer 3. In other words, the metallic layer is simply connected. Furthermore, the outer surface of the metallic layer 4 is integrally formed with the structuring 5.

[0091] The recesses 11 form a plurality of strips 19, each having a width and a length. The plurality of strips 19 each have a rectangular shape, and the length of each of the plurality of strips 19 is the same. For example, the strips of the plurality of strips have a length between 5 μm to 100 μm inclusive, preferably 6 μm to 20 μm inclusive.

[0092] The widths of each of the strips of the plurality of strips 19 are different. For example, the strips of the plurality of strips have a width between 1 μm and 50 μm inclusive, preferably between 2 μm to 15 μm inclusive and more preferably between 3 μm and 10 μm.

[0093] By means of the different widths of the strips of the plurality of strips 19, a bar code is formed with which the component 1 can be uniquely identified.

[0094] In contrast to FIG. 1A, the exemplary embodiment of FIG. 1B shows recesses which do not completely break through the metallic layer 3. In this case, a bottom surface of the recesses 11 is formed by the metallic layer 3.

[0095] The schematic sectional view of FIG. 2A shows the exemplary embodiment of an optoelectronic component 1 described here along the sectional line A-A shown in FIG. 1B.

[0096] According to FIG. 2, the semiconductor chip 2 of the optoelectronic component 1 is a laser diode which has a semiconductor layer sequence 8 and an active layer 9. Furthermore, the semiconductor chip 2 has a ridge waveguide 6 with a top surface 6a and adjoining side surfaces 6b. The ridge waveguide 6 is formed by a ridge-shaped elevated region of the semiconductor layer sequence 8. The ridge waveguide 6 protrudes as a protrusion from a recessed outer surface of the semiconductor layer sequence 8a.

[0097] The top surface of the ridge waveguide 6a is directly connected to the recessed outer surface of the semiconductor layer sequence 8a, which is arranged lateral to the ridge waveguide 6, via the side surfaces 6b adjacent thereto. The top surface 6a and the side surfaces 6b of the ridge waveguide and the recessed outer surface of the semiconductor layer sequence 8a lateral to the ridge waveguide 6 form a step profile. Furthermore, a first main surface of the semiconductor chip 2a comprises the top surface 6a and the side surface 6b of the ridge waveguide as well as the recessed outer surface of the semiconductor layer sequence 8a lateral to the ridge waveguide 6. A second main surface 2a is arranged opposite the first main surface 2a.

[0098] Furthermore, the semiconductor chip 2 has a passivation layer 7 which completely covers the side surfaces of the ridge waveguide 6b. A contact 9 is arranged on the top surface of the ridge waveguide 6a, the side surfaces of which are also covered by the passivation layer 7. The passivation layer 7 additionally covers the recessed outer surface of the semiconductor layer sequence 8a lateral to the ridge waveguide 6. A top surface of the contact 9 is not covered with the passivation layer 7.

[0099] The metallic layer 3 is in direct contact with the top surface of the contact 9. Furthermore, the metallic layer 3 completely covers the passivation layer 7 of the semiconductor chip 2. The metallic layer has, for example, a thickness in the vertical direction of at least 1 micrometre and at most 5 micrometres. The thickness along the cut line A-A is substantially constant over the entire metallic layer. Essentially constant means that the thickness can vary due to manufacturing tolerances.

[0100] The schematic sectional view of FIG. 2B shows the exemplary embodiment of an optoelectronic component 1 described here along the sectional line B-B shown in FIG. 1B.

[0101] In the edge region of the metallic layer 18, the metallic layer between the recesses 11, i.e., along the line of section B-B, has a thickness which is smaller than the thickness of the metallic layer 3 in the region having no recesses 11. A top surface and a side surface of the metallic layer adjacent thereto in the region of the recesses 11 and the bottom surface of the recesses 11 form a step profile.

[0102] The schematic sectional view of FIG. 3 shows the exemplary embodiment of an optoelectronic component 1 described herein along the sectional line B-B shown in FIG. 1B.

[0103] In contrast to the exemplary embodiment in connection with FIG. 2b, the metallic layer 3 of the optoelectronic component 1 according to FIG. 3 is a metallic layer stack. The metallic layer stack comprises a first metallic layer 13 and a second metallic layer 14. Furthermore, the metallic layer 3 is in direct contact with the top surface of the ridge waveguide 6a.

[0104] The first metallic layer 13 covers the side surfaces 6b and the top surface 6a of the ridge waveguide. Further, the first metallic layer is partially arranged on the passivation layer 7 over the recessed outer surface of the semiconductor layer sequence 8a. The first metallic layer 13 embeds the ridge waveguide 6.

[0105] The second metallic layer 14 embeds the first metallic layer. The second metallic layer 14 further covers the passivation layer 7 over the recessed outer surface of the semiconductor layer sequence 8a being not covered by the first metallic layer 13. In this case, the second metallic layer 14 has the recesses 11. In top view, the recesses 11 extend without overlapping with the first metallic layer 13.

[0106] The schematic sectional view in top view of FIG. 4 shows an embodiment of an optoelectronic component 1 described here.

[0107] According to FIG. 4, in contrast to the exemplary embodiment in connection with FIGS. 1A and 1B, the structuring is formed by roughened regions 12 of the metallic layer 3. The roughened regions 12 are formed from the same material as the metallic layer 3.

[0108] The schematic sectional view of FIG. 5 shows the exemplary embodiment of an optoelectronic component 1 described here along the sectional line C-C shown in FIG. 4.

[0109] In contrast to the exemplary embodiment in connection with FIG. 3, the first metallic layer 13 comprises a metallic adhesion promoter layer 15 and a metallic barrier layer 16. A perturbation layer is arranged on the first metallic layer 13 in the edge region of the metallic layer 18. Roughened regions 12 are arranged above the perturbation layer 20. In these regions, the second metallic layer 14 is roughened and has elevations and depressions.

[0110] The schematic sectional views of FIGS. 6A, 6B, 6C and 6D show method steps of an exemplary embodiment of a method described herein for producing an optoelectronic component 1.

[0111] First, an optoelectronic semiconductor chip 2 is provided (not shown here). A metallic layer 3 is then applied on the semiconductor chip 2 as shown in FIG. 6A. The metallic layer 2 is a metallic layer stack and comprises a first metallic layer 13 and a second metallic layer 14. The second metallic layer 14 is arranged on the first metallic layer 13.

[0112] In this exemplary embodiment, the first metallic layer 13 can comprise, for example, three layers. The layer sequence of the first metallic layer 13 is for example as follows: Ti—Pt—Pd, with the second metallic layer being deposited on the Pd layer. In this exemplary embodiment, the second metallic layer 14 can for example comprise Au or be formed thereof.

[0113] In a next method step, a structuring 5 is produced on an outer surface of the second metallic layer 14. As shown in FIG. 6B, recesses 11 are formed in the second metallic layer 14 in the edge region 18 of the second metallic layer 14. The recesses 11 penetrate the second metallic layer 14 completely up to the first metallic layer 13.

[0114] According to FIG. 6C, a perturbation layer 20 is applied on the exposed first metallic layer 13. For example, the exposed first metallic layer 13 can be oxidised by means of an oxygen plasma treatment. Alternatively, it is possible that the exposed first metallic layer 13 is heated in an oxygen atmosphere. A surface of the exposed first metallic layer 13 is thus oxidised and forms, for example, the perturbation layer 20.

[0115] In a further method step, a further second metallic layer 14a is applied on the perturbation layer 20. An outer surface of the further second metallic layer 14a applied on the perturbation layer 20 has an increased roughness compared to an outer surface of the second metallic layer 14. The further second metallic layer 14a can be formed from the same metal as the second metallic layer 14. Alternatively, the further second metallic layer 14a can be formed of TiPtAu, for example.

[0116] In the exemplary embodiment according to FIG. 6D, a thickness of the further second metallic layer 14a is formed smaller than the thickness of the second metallic layer 14.

[0117] The schematic sectional views of FIGS. 7A, 7B, 7C and 7D show method steps of an exemplary embodiment of a method described herein for producing an optoelectronic component 1.

[0118] Analogous to the exemplary embodiment in connection with FIG. 6A, an optoelectronic semiconductor chip 2 is provided (not shown here), to which a metallic layer 3 is applied according to FIG. 7A.

[0119] Subsequently, according to FIG. 7B, a stop layer 21 is applied on the metallic layer 3 or on the second metallic layer 14 regionally.

[0120] According to FIG. 7C, in a next method step, a further metallic layer or a further second metallic layer 14a is galvanically applied on the regions not covered by the stop layer 21. An outer surface of the further second metallic layer 14a, which is galvanically applied, has an increased roughness compared to an outer surface of the second metallic layer 14.

[0121] Subsequently, FIG. 7D, the stop layer 21 is removed. In this exemplary embodiment, the thickness of the further second metallic layer 14 is greater than the thickness of the second metallic layer 14.

[0122] In contrast to the exemplary embodiment of FIG. 1A, the metallic layer according to FIG. 8 has recesses 11 which are completely surrounded by the metallic layer 3 and which completely penetrate the metallic layer 3.

[0123] This patent application claims the priority of the German patent application DE 10 2018 131 579.1, the disclosure of which is hereby incorporated by reference.

[0124] The invention is not limited to the exemplary embodiments by the description based thereon. Rather, the invention encompasses any new feature as well as any combination of features, which in particular includes any combination of features in the claims, even if this feature or combination itself is not explicitly indicated in the claims or exemplary embodiments.

REFERENCES

[0125] 1 optoelectronic component [0126] 2 optoelectronic semiconductor chip [0127] 2a first main surface of the semiconductor chip [0128] 2b second main surface of the semiconductor chip [0129] 3 metallic layer [0130] 4 outer surface of the metallic layer [0131] 5 structuring [0132] 6 ridge waveguide [0133] 6a top surface of the ridge waveguide [0134] 6b side surfaces of the ridge waveguide [0135] 7 passivation layer [0136] 8 semiconductor layer sequence [0137] 8a recessed outer surface of the semiconductor layer sequence [0138] 9 active layer [0139] 10 contact [0140] 11 recesses [0141] 12 roughened regions [0142] 13 first metallic layer [0143] 14 second metallic layer [0144] 14a further second metallic layer [0145] 15 metallic adhesion promoter layer [0146] 16 metallic barrier layer [0147] 17 edge region of the semiconductor chip [0148] 18 edge region of the metallic layer [0149] 19 plurality of stripes [0150] 20 perturbation layer [0151] 21 stop layer