METHOD OF ADDRESSING FILM LIFTOFF IN MEMS FABRICATION

Abstract

A method of fabricating a MEMS device. A first spacer is formed above a CMOS substrate containing circuitry. Vias are formed within the first spacer. A first metal is formed above the first spacer and vias and patterned to form a MEMS element. A second spacer is formed above the MEMS element and first spacer. A via is formed within the second spacer. A second metal is formed above the second spacer and the via. A capping layer is formed above the second metal. The second metal is patterned to form a second MEMS element. The device is cleaned using a developer solution while the capping layer protects the second MEMS element. The first and second spacers are removed to release the first and second MEMS elements.

Claims

1. A method of fabricating a digital micromirror device, the method comprising: forming a first spacer above a CMOS substrate containing circuitry; forming hinge vias within the first spacer; depositing a first metal above the first spacer and hinge vias and patterning the first metal to form a hinge; forming a second spacer above the hinge and first spacer; forming a mirror via within the second spacer; depositing a second metal above the second spacer and the mirror via; forming a sacrificial dielectric capping layer on a surface of the second metal; patterning the second metal to form a mirror; cleaning the device using a developer solution; and removing the first and second spacer layers to release the hinge and mirror.

2. A method of fabricating a digital micromirror device, the method comprising: forming a first spacer above a CMOS substrate containing circuitry and patterning the first spacer to form openings for the hinge vias; depositing a hinge liner metal above the first spacer and hinge vias to form a hinge via liner; depositing a hinge via plug material above the hinge via liner to form a hinge via plug; removing hinge via liner metal and hinge via plug material from above the first spacer; depositing a hinge metal above the first spacer and hinge vias and patterning the hinge metal to form a hinge; forming a second spacer above the hinge and first spacer and patterning the second spacer to form a mirror via; depositing a mirror metal above the second spacer and mirror; depositing an anti-reflective layer within a central indentation in the mirror via; forming a sacrificial dielectric capping layer on a surface of the mirror metal; depositing, patterning and exposing patterning layers above the capping layer; etching the mirror metal to form a mirror; cleaning the device using a developer solution; removing patterning layers using a descum process; and removing the first and second spacer layers to release the hinge and mirror.

3. The method of claim 2, wherein the capping layer is deposited using chemical vapor deposition.

4. The method of claim 2, wherein a thickness of the capping layer is 10 to 100 Angstroms.

5. The method of claim 2, wherein the capping layer comprises an oxynitride.

6. The method of claim 2, wherein the capping layer is deposited using sputtering.

7. The method of claim 2, wherein at least a majority of the capping layer is removed using an ash process.

8. The method of claim 2, wherein the capping layer comprises a metal oxide.

9. The method of claim 7, wherein a portion of the capping layer is not removed from the mirror metal surface.

10. A method of fabricating a microelectromechanical systems (MEMS) device, the method comprising: forming a first spacer above a CMOS substrate containing circuitry; forming vias within the first spacer; depositing a first metal above the first spacer and vias and patterning the first metal to form a first MEMS element; forming a second spacer above the first MEMS element and first spacer; forming a via within the second spacer; depositing a second metal above the second spacer and the via; forming a sacrificial dielectric capping layer on a surface of the second metal; patterning the second metal to form a second MEMS element; cleaning the device using a developer solution; and removing the first and second spacer layers to release the first and second MEMS elements.

11. The method of claim 10, wherein the capping layer is deposited using chemical vapor deposition.

12. The method of claim 10, wherein the capping layer is deposited using sputtering.

13. The method of claim 10, wherein a thickness of the capping layer is 10 to 100 Angstroms.

14. The method of claim 10, wherein the capping layer comprises an oxynitride.

15. (canceled).

16. The method of claim 10, wherein at least a majority of the capping layer is removed using an ash process.

17. The method of claim 10, wherein the capping layer comprises a metal oxide.

18. The method of claim 16, wherein a portion of the capping layer is not removed from the second metal surface.

19. The method of claim 1, wherein the capping layer is deposited using chemical vapor deposition.

20. The method of claim 1, wherein the capping layer is deposited using sputtering.

21. The method of claim 1, wherein a thickness of the capping layer is 10 to 100 Angstroms.

22. The method of claim 1, wherein the capping layer comprises an oxynitride.

23. The method of claim 1, wherein the capping layer comprises a metal oxide.

24. The method of claim 1, wherein at least a majority of the capping layer is removed using an ash process.

25. The method of claim 8, wherein a portion of the capping layer is not removed from the mirror metal surface.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Example embodiments are described with reference to accompanying drawings, wherein:

[0016] FIG. 1 (Prior Art) is a cross-sectional view of a micromirror.

[0017] FIG. 2 (Prior Art) is a top view of delaminated squares re-deposited above an array of micromirrors.

[0018] FIG. 3 (Prior Art) is a top view of delaminated squares re-deposited above the periphery of an array of micromirrors.

[0019] FIG. 4 is a cross-sectional image of a micromirror.

[0020] FIGS. 5A through 5E illustrate cross-sections of a micromirror during fabrication.

[0021] FIG. 6 depicts an image of an intersection of micromirrors.

[0022] FIG. 7 depicts a wafer level image.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0023] The steps described below are typically undertaken on a wafer level scale, with multiple instances of the illustrated structures simultaneously formed to define arrays of such structures formed at respective die areas of corresponding simultaneously formed DMDs. Although discussed in terms of a DMD, aspects of the example embodiments may be applied to other MEMS devices and elements.

[0024] FIG. 4 illustrates a micromirror 400, including a CMOS portion 402 and a MEMS portion 404.

[0025] The CMOS portion 402 includes a substrate 406 with transistors. As an example, a first metal layer 408 may be deposited above the substrate 406 and transistors and patterned. A first dielectric layer 410 may be deposited above the patterned metal layer 408. A second metal layer 412 may deposited above the dielectric layer 410 and patterned. A second dielectric 414 may deposited above the patterned metal layer 412. A first via 416 is patterned within the dielectric layer 414 and filled with a metal such as tungsten. A third metal 420 is deposited above the dielectric layer 414. An anti-reflective layer 422 of one or more films is deposited above the metal layer 420. The anti-reflective layer 422 aids in reducing light reflectance from the metal layer 420 below and in improving contrast of the micromirror device 400.

[0026] A layer, typically of a metal such as titanium, is deposited to form hinge vias 426 and a hinge 428 above the third metal 420. A metal layer is deposited to form a centrally placed mirror via 432 above the hinge 428. The mirror via 432 and micromirror 434 include a reflective material, such as an alloy including 99% aluminum and 1% titanium. A central indentation 436 within the top surface of the micromirror 434 remains after deposition of the metal within the mirror via 432 opening, and is filled with an antireflective BARC layer 438 to improve system contrast.

[0027] FIGS. 5A through 5E illustrate cross-sections (indicated generally at 500) of the micromirror 400 during fabrication.

[0028] FIG. 5A illustrates fabrication of the MEMS portion 404 of the micromirror above the CMOS portion 402.

[0029] After deposition of the anti-reflective layer 422, a spacer layer 502 is deposited above the anti-reflective layer 422. Layer 502 is a sacrificial layer including a material such as photoresist and is removed at a later step.

[0030] In FIG. 5B, the spacer layer 502 is patterned to form vias 504. A metal is deposited within the patterned vias 504 to form the hinge vias 426 and above the spacer layer 502 to form the hinge 428.

[0031] In FIG. 5C, a spacer layer 508, typically a material such as photoresist, is deposited above the hinge 428. A via is patterned centrally within the layer 508 to form the mirror via 432. A mirror metal is deposited on the spacer layer 508 to form the micromirror 434 and within the via to form the mirror via 432. A central indentation 436 results from deposition of the mirror metal in the mirror via 432. The indentation 436 is filled with an anti-reflective layer 438.

[0032] FIG. 5D shows a capping layer 512 deposited above the mirror 434 surface. The capping layer 512 may be deposited using a process such as chemical vapor deposition or sputtering. The layer 512 includes a dielectric such as silicon oxynitride, nitride, or oxide, which is sacrificial, or a metal oxide such as a titanium oxide. The thickness of layer 512 is approximately 10 to 100 Angstroms and limited by the amount of tensile stress placed on the mirror 434 surface by the layer 512 and by the time required to ash it if the layer 512 is a sacrificial dielectric.

[0033] In an example embodiment, the layer 512 is an oxynitride film of thickness of about 100 Angstroms deposited using chemical vapor deposition. The layer 512 is sacrificial and is removed when the spacer layers 502 and 508 are removed using an O.sub.2 and CF.sub.4 ash during undercut. The layer 512 blocks the developer solution of a subsequent cleaning process from coming in contact with layer 434 and lifting the photoresist and BARC layered squares.

[0034] In FIG. 5E, a layer 514 such as a photoresist (or ARC and resist) is deposited above layer 512. Layer 514 is patterned and used to etch the mirror metal to form individual mirror 434 structures. After the etch, a developer solution including tetramethyl ammonium hydroxide is used to clean the device 500. During this clean, layer 512 protects the mirror 434 from the developer solution. The layer 514 is then removed.

[0035] The developer cleaning process can delaminate patterned areas of layer 514 (BARC and photoresist) from the device 500 surface. These delaminated portions of layer 514 can redeposit above the mirrors 436 and across scribe lines to form defects. The protective layer 512 forms an adhesive for the BARC and photoresist of layer 514 as well as a protective shield against re-deposition of delaminated areas of layer 514 onto the mirror 434 surface.

[0036] The spacer layers 502 and 508 are removed using an oxygen ash to release the hinge 428 and micromirror 434. The hinge vias 426 forms a free-standing support for the hinge 428, and mirror via 432 forms a free-standing support for the micromirror 434 as shown in FIG. 4. This ash may also be used to remove layer 512.

[0037] The described methodology may offer many advantages.

[0038] The layer 512 forms a protective layer on the mirror metal layer surface, which prevents the chemical and physical reactants from the developer cleaning process from coming in contact with the mirror metal.

[0039] The layer 512 may be a sacrificial dielectric layer and removed in an oxygen based ash.

[0040] The layer 512 may be a metal oxide, which remains on the surface of layer 434.

[0041] The layer 512 addresses the delamination of photoresist and BARC layers from the mirror surface.

[0042] Experimental data has shown that the layer 512 is effective against delamination of photoresist and BARC layers and reduces yield loss.

[0043] FIG. 6 shows an image 600 of an intersection of micromirrors 602. The image 600 demonstrates the lack of delaminated squares 604 across the intersection 602.

[0044] FIG. 7 shows a wafer level image 700. The wafer 702 includes multiple micromirror devices 704. The image demonstrates the lack of delaminated squares 706 across the wafer 702.

[0045] Modifications are possible in the described example embodiments, and other embodiments are possible, within the scope of the claims.