Method for operating a conductive bridging memory device

Abstract

A method is disclosed for operating a Conductive Bridge Random Access Memory (CBRAM) device that includes an electrolyte element sandwiched between a cation supply top electrode and a bottom electrode. The method comprises conditioning the CBRAM device by applying a forming current pulse having a pulse width (t.sub.f) of 100 ns or less and a pulse amplitude (I.sub.f) of 10 uA or less, and when programming, setting the conditioned CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (t.sub.s) of 100 ns or less and a pulse amplitude (I.sub.s) equal to or larger than the forming current pulse amplitude (I.sub.f).

Claims

1. A method for operating a memory comprising at least one Conductive Bridge Random Access Memory (CBRAM) device, the at least one CBRAM device comprising an electrolyte element sandwiched between a cation supply top electrode and an inert bottom electrode, the method comprising: conditioning the at least one CBRAM device by applying a forming current pulse having a pulse amplitude (I.sub.f) of 10 uA or less.

2. The method of claim 1, wherein the pulse amplitude (I.sub.f) is 1 uA or less.

3. The method of claim 2, wherein the forming current pulse has a pulse width (t.sub.f) of 100 ns or less.

4. The method of claim 1, wherein the memory comprises an array of the CBRAM devices, whereby the CBRAM devices in the array are conditioned in parallel.

5. The method of claim 1, further comprising setting the conditioned at least one CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (t.sub.s) of 100 ns or less, and a current pulse amplitude (I.sub.s) equal to or higher than the forming current pulse amplitude (I.sub.f).

6. The method claim 5, wherein the set current pulse amplitude (I.sub.s) is above 10 uA.

7. The method claim 5, wherein the set current pulse amplitude (I.sub.s) is less than the forming current pulse amplitude (I.sub.f).

8. The method of claim 5, further comprising determining the set current pulse amplitude (I.sub.s) based on a LRS selected from a set of LRSs.

9. The method of claim 1, wherein the cation supply top electrode comprises copper or silver.

10. The method of claim 1, wherein the inert bottom electrode comprises tungsten or titanium-nitride.

11. The method of claim 1, wherein the electrolyte element comprises alumina-oxide, silicon-oxide, tungsten-oxide, silicon-nitride, or a combination thereof.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) For the purpose of teaching, drawings are added. These drawings illustrate some aspects and embodiments of the disclosure. They are only schematic and non-limiting. The size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the disclosure. Like features are given the same reference number.

(2) FIG. 1 illustrates a CBRAM device according to the disclosure.

(3) FIG. 2 illustrates a forming and set programming step according to the disclosure.

(4) FIG. 3 illustrates the impact of the amplitude (I.sub.s) of the set current on the Low Resistive State (LRS) and on the High Resistive State (HRS) state.

DETAILED DESCRIPTION

(5) The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto. Furthermore, the terms first, second and the like in the description, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other sequences than described or illustrated herein. Moreover, the terms top, under and the like in the description are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other orientations than described or illustrated herein.

(6) The present disclosure relates to the forming of a CBRAM device using a forming current pulse of lower width (t.sub.f) and height (I.sub.f) than in conventional techniques, which reduces the time required to condition a pristine CBRAM device. As this programming current (I.sub.f) is reduced, multiple pristine CBRAM (1) devices can be conditioned in parallel. This parallel conditioning of an array of CBRAM (1) devices may be executed while the pristine memory devices (1) are still on the wafer. After being conditioned, the wafer is diced into memory chips. The diced memory chip containing the array of conditioned memory devices (1) is packaged while the Low Resistance State (LRS) or set state of the packaged and conditioned memory device (1) is essentially unaffected by this packaging process.

(7) Such CBRAM device (1) is illustrated in FIG. 1. Here a Conductive Bridge Random Access Memory (CBRAM) device (1) is shown comprising an insulating electrolyte element (2) sandwiched between a cation supply top metal electrode (3) and an inert bottom electrode (4). The bottom electrode (4) is labelled inert as it does not provide cations during the filament forming process.

(8) As discussed in the following paragraphs, the CBRAM device (1) may be formed using materials and methods compatible with CMOS processing. This compatibility allows integration of the CBRAM device (1) on a CMOS substrate, i.e. a semiconductor substrate comprising logic devices, such as field effect transistors, for controlling the operation of the memory device (1).

(9) The dielectric material (5) of the electrolyte element (2) may be selected from the group of alumina oxides, hafnium oxides, tantalum oxides, silicon oxides, tungsten oxides, silicon nitrides, or combinations thereof.

(10) The cation supply electrode (3) can comprise Cu or Ag, supplying respectively Cu.sup.+ and Ag.sup.+ cations during programming. In one example, the cation supply electrode (3) is a Cu alloy, such as CuTe, CuGe, CuGeTe, CuTeC, CuTi, and the like.

(11) Optionally, a metallic liner (6) is formed, separating the cation supply electrode (3) from the electrolyte element (2). In case a Cu or Ag containing top electrode (3) is formed, this metallic layer (6) contains Ta or TiW.

(12) In one example, the bottom electrode (4) comprises tungsten. For instance, the bottom electrode (4) may be formed of tungsten or titanium-nitride, e.g. TiN.

(13) When biasing (V.sup.+-V.sup.) the top electrode (3) positive with respect to the bottom electrode (4) of such a CBRAM device (1), an electrical field is applied over the electrolyte element (2). A conductive filament then grows (7) from the cation supply metal top electrode (3) towards the bottom layer (4) due to cation reduction, M.sup.+.fwdarw.M, within the electrolyte element (2).

(14) Such a pristine Conductive Bridge Random Access Memory (CBRAM) device (1) is conditioned, i.e. an initial conductive filament is formed, by applying a forming current pulse having a pulse amplitude (I.sub.f) of 10 uA (micro-Ampere) or less, such as 5 uA or less, or 1 uA or less, whereby the pulse amplitude is higher than zero.

(15) If the electrolyte element (2) comprises or consists of silicon-oxide, or tungsten oxide, the amplitude of the forming current (I.sub.f) can be 5 uA or less.

(16) In one example, the forming current pulse has a pulse width (t.sub.f) of 100 ns (nanoseconds) or less, such as 50 ns or less, whereby the pulse width is higher than zero. In case an array of such memory devices (1) is conditioned, the memory devices (1) in the array can be conditioned in parallel instead of sequentially, thereby increasing the throughput of the conditioning step.

(17) A memory device (1), conditioned as discussed in the foregoing paragraphs using a short current forming pulse, can then be programmed. When setting this memory device (1), i.e. bringing it into a Low Resistive State (LRS), a set current pulse is applied. This set current pulse has a pulse width (t.sub.s) of 100 ns or less, but higher than zero, such as 50 ns or less, whereby its current pulse amplitude (I.sub.s) is equal to or higher than the amplitude (I.sub.f) of current pulse applied to form this memory device (1). For instance, this set current pulse amplitude (I.sub.s) is above 10 uA. FIG. 2 illustrates the relative amplitudes of the forming and set current pulse according to this disclosure.

(18) The amplitude (I.sub.s) of this set current pulse now differs from the amplitude (I.sub.f) of the forming current pulse. Hence, one can select the set current pulse amplitude (I.sub.s) in view of or based on the resistance value desired in the Low Resistive State (LRS). As illustrated in FIG. 3, two values for this amplitude were applied (I.sub.s=10 uA or 50 uA). This difference in set current pulse amplitude (I.sub.s) only had limited impact on the resistance value obtained during the subsequent High Resistive State (HRS). The corresponding resistance value of the LRS was noticeably shifted to lower values when increasing the set current pulse amplitude (I.sub.s). The memory window (MW), even at 10 uA, still allows distinguishing the Low Resistive State from the High Resistive State. In one example, the amplitude of the set current pulse is above 10 uA and below 500 uA, such as above 10 uA, and up to and including 50 uA.

(19) As this set current pulse amplitude (I.sub.s) can be selected substantially independently from the resistance value of the FIRS and of the forming state, with the limitations discussed above, one can program the memory device (1) to different low resistance levels in the LRS depending on the set current pulse amplitude (I.sub.s) applied. The current disclosure thus allows multilevel cell programming, whereby the set current pulse amplitude (I.sub.s) is determined in view of a Low Resistance State selected from a set of Low Resistance States.

(20) Although the set current pulse amplitude (I.sub.s) may be selected to be equal to or higher than the amplitude (I.sub.f) of the current pulse applied to form this memory device (1), one can apply a current pulse amplitude lower than this forming current pulse amplitude. Such a lower set current pulse amplitude results in a higher value of the Low Resistive State as illustrated by FIG. 3. This broadens the range of the set current amplitude from which to select in order to reversibly switch between different values of the Low Resistive State.