Field effect transistor having two-dimensionally distributed field effect transistor cells

Abstract

A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.

Claims

1. A Field Effect Transistor (FET), comprising: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells, the plurality of gate electrodes being finger-like electrode extending outwardly from the gate contact; a drain contact connected to the drain pad of each one of the FET cells; a common source contact connected to source pad of each one of the FET cells; wherein the cells are disposed on a surface in a two-dimensional array; wherein a first portion of the FET cells have the gate electrodes thereof control a flow of carriers passing between the drain pads and the source pads of the first portion of the FET cells; wherein a second portion of the FET cells have the gate electrodes thereof control a flow of carriers passing between the drain pads and the source pads of the second portion of the FET cells; and wherein a plurality of the first portion of the gate electrodes being parallel and extending along a first direction and a plurality of the second portion of the gate electrode being parallel and extending along a second direction, the second direction intersecting the first direction.

2. The Field Effect Transistor (FET) recited in claim 1 wherein the FET cells are disposed in a non-linear array.

3. The Field Effect Transistor (FET) recited in claim 1 wherein the FET cells are disposed in U-shaped arrangement.

4. The Field Effect Transistor (FET) recited in claim 1 wherein one portion of the cells is disposed along a line and another portion of the cells is disposed along an intersecting line.

5. A Field Effect Transistor (FET), comprising: a plurality of FET cells having a plurality of finger-like gate electrodes, each one of the FET cells having a corresponding one of the plurality of finger-like gate electrodes disposed between a drain pad and a source pad of such one of the FET cells; a common gate contact disposed in an inner region of the FET; and wherein the finger-like gate electrodes are interconnected to points disposed successively along an edge of the common gate contact, a plurality of a first portion of the plurality of finger-like gate electrodes being parallel and extending outwardly from the common gate contact towards an outer region of the FET along to a vertical direction and a plurality of a second portion of the plurality of finger-like gate electrodes being parallel and extending outwardly from the common gate contact towards an outer region of the FET along a direction intersecting the vertical direction.

6. The Field Effect Transistor (FET) recited in claim 5 wherein the direction intersecting the vertical direction is a horizontal direction.

7. The Field Effect Transistor recited in claim 5 wherein a third portion of a plurality of finger-like gate electrodes extend outwardly from the common gate contact; and wherein the first portion and the second portion are connected to opposite edges of the common gate contact.

8. The Field Effect Transistor recited in claim 5 wherein a third portion of a plurality of finger-like gate electrodes is electrically interconnected to successively points along the common gate contact and extend outwardly from the common gate electrode along the vertical direction; the first portion being connected to points along one portion of the edge of the common gate contact and the third portion being connected to points along an opposite portion of the edge of the common gate contact.

9. A Field Effect Transistor (FET), comprising: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a common gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; a source contact connected to source pad of each one of the FET cells; wherein a plurality of a first portion of the FET cells have the gate electrodes thereof being paralled and control a flow of carriers passing between the drain pads and the source pads of the first portion of the FET cells along a first direction; wherein a plurality of a second portion of the FET cells have the gate electrodes thereof being parallel and control a flow of carriers passing between the drain pads and the source pads of the second portion of the FET cells along a second direction; wherein the first direction intersects the second direction; and wherein the gate electrodes of the first portion of the FET cells and the gate electrodes of the second portion of the FET cells extend outwardly from the common gate contact.

Description

DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a top view of a Field Effect Transistor (FET) according to the PRIOR ART;

(2) FIG. 2A is a top view of a plan view of a linear array of, here eight, FETs of FIG. 1 according to the PRIOR ART:

(3) FIG. 2B shows the heat signature or spatial position of heat generated by each on the eight FETS in the linear array of FIG. 2A according to the PRIOR ART.

(4) FIG. 3A is a plan view of a Field Effect Transistor (FET) according to the disclosure;

(5) FIG. 3B is a cross sectional sketch of a portion of the FET of FIG. 3A, such cross section being taken along line 3B-3B of FIG. 3A according to the disclosure;

(6) FIG. 3C is an prospective view of the FET of FIG. 3A according to the disclosure;

(7) FIG. 4A is a top view of a linear array of, here eight, FETs of FIG. 1 according to the disclosure; and

(8) FIG. 4B shows the heat signature or spatial position of each of heat generated by each on the eight FETS in the linear array of FIG. 4A according to the disclosure.

(9) Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

(10) Referring now to FIGS. 3A-3C, a Field Effect Transistor (FET) 10 is shown to a plurality of, here twelve, FET cells 12.sub.1-12.sub.12, each one of the FET cells 12.sub.1-12.sub.12 having: a source S; a drain D; and a gate G.sub.1-G.sub.12, respectively, each gate G.sub.1-G.sub.12 here an elongated, finger-like gate, being disposed between the source S and the drain D to control a flow of carriers along a channel between the source S and drain D; FET cells 12.sub.1-12.sub.4 being shown on FIG. 3B. Here, the FET 10 is formed using photo-lithographic chemical etching processing. More particularly, each one of the FET cells 12.sub.1-12.sub.12 has, on an upper, planar surface 13 of a semiconductor substrate 15, here for example a substrate having gallium nitride (GaN), a corresponding one of the twelve gate electrodes G.sub.1-G.sub.12, respectively, in Schottky contact with the surface 13 of the semiconductor substrate 15, as shown in FIG. 3A. The FET 10 includes: six drain pads 20.sub.1-20.sub.6 in ohmic contact with the surface 13 of the semiconductor substrate 15; and seven source pads 22.sub.1-22.sub.7 in ohmic contact with the surface 13 of the semiconductor substrate 15, as shown in FIG. 3A. It is noted that each gate finger G.sub.1-G.sub.12 shares a drain (D) provided by one of the drain pads 20.sub.1-20.sub.6 and a source (S) provided by an adjacent one of the source pads 22.sub.1-22.sub.7. Thus, while source pad 22.sub.1 provides the source (S) for FET cell 12.sub.1, source pad 22.sub.2 provides the source (S) for both FET cells 12.sub.2 and 12.sub.3; source pad 22.sub.3 provides the source (S) for both FET cells 12.sub.4 and 12.sub.5; source pad 22.sub.4 provides the source (S) for both FET cells 12.sub.6 and 12.sub.7; source pad 22.sub.5 provides the source (S) both for FET cells 12.sub.8 and 12.sub.9; source pad 22.sub.6provides the source (S) for both FET cells 12.sub.10 and 12.sub.11; source pad 22.sub.7 provides the source (S) for FET cell 12.sub.12. Likewise, drain pad 20.sub.1 provides the drain (D) for both FET cells 12.sub.1 and 12.sub.2; drain pad 20.sub.2 provides the drain (D) for both FET cells 12.sub.3 and 12.sub.4; drain pad 20.sub.3 provides the drain (D) for both FET cells 12.sub.5 and 12.sub.6; drain pad 20.sub.4 provides the drain (D) for both FET cells 12.sub.7 and 12.sub.8; drain pad 20.sub.5 provides the drain (D) for FET cells 12.sub.9 and 12.sub.10; drain pad 20.sub.6 provides the drain (D) for FET cells 12.sub.11 and 12.sub.12. Thus, one of the twelve gates G.sub.1-G.sub.12 is disposed between a source (S) and a drain (D) of each one of the FET cells 12.sub.11 and 12.sub.12. Thus, gate G1 is disposed between source pad 22.sub.1 and drain pad 20.sub.1; gate G2 is disposed between source pad 22.sub.2 and drain pad 20.sub.1; gate G3 is disposed between source pad 22.sub.2 and drain pad 20.sub.2; gate G4 is disposed between source pad 22.sub.3 and drain pad 20.sub.2; gate G5 is disposed between source pad 22.sub.3 and drain pad 20.sub.3; gate G6 is disposed between source pad 22.sub.4 and drain pad 20.sub.3; gate G7 is disposed between source pad 22.sub.4 and drain pad 20.sub.4; gate G8 is disposed between source pad 22.sub.5 and drain pad 20.sub.4; gate G9 is disposed between source pad 22.sub.5 and drain pad 20.sub.5; gate G10 is disposed between source pad 22.sub.6 and drain pad 20.sub.5; gate G11 is disposed between source pad 22.sub.6 and drain pad 20.sub.6; and gate G12 is disposed between source pad 22.sub.7 and drain pad 20.sub.6, as shown in FIG. 3A.

(11) The FET 10 includes: a gate contact 14 connected to the gates G1-G12 of each one of the FET cells 12.sub.1-12.sub.12; a drain contact 16 connected to each one of the drain pads 20.sub.1-20.sub.6, as shown in FIG. 3A. The source pads 22.sub.1-22.sub.7 are electrically interconnected by air bridges 26 shown more clearly in FIG. 3C. A source contact 18 (FIGS. 3A-3C) is disposed on the bottom of the substrate 15 (FIG. 3B) and is connected to source pads 22.sub.1, 22.sub.3, 22.sub.5 and 22.sub.7 by conductive vias 28 passing through the substrate 15, as shown in FIGS. 3A-3C.

(12) More particularly, and referring also to FIG. 3B, the cells 14 are disposed on the upper surface 13 of the substrate 15 in a two-dimensional array in an X-Y plane (FIG. 3A and 3B). The finger-like gate electrodes G1-G12 are electrically interconnected to successively points, P, along an edge of the common gate contact 14. It is noted that a first portion 30 of the finger-like gate electrodes G1-G4 extend along to a vertical direction or Y direction (FIG. 3A) and a second portion 32 of the finger-like gate electrodes G5-G8 extending along a direction intersecting the vertical direction, here for example, a horizontal or X direction. It is noted that a third portion 34 of a plurality of finger-like gate electrodes G9-G12 extend along to a vertical direction or Y direction (FIG. 3A) the first portion 30 and the third portion 34 are connected to opposite edges of the common gate contact 14 and extend in opposite directions. Thus, here in this example, the FET 10 is a U-shaped FET 10.

(13) Referring now to FIGS. 2A and 4A, it is noted that the vertical dimension (along the Y-axis) of an array of the eight FETs 10, each having twelve FET cells, (FIG. 3A) with the FETs of the FIG. 1, the eight FETs 10 occupy less of the vertical (Y axis) dimension. It is also noted in comparing the heat signature of the array of eight FETs 10 of FIG. 3A, with the heat signature of the array of FETs in FIG. 1 (FIG. 2B), with the array of the FETs 10 of FIG. 3A the heat is distributed in two dimensions (the X and Y directions, FIG. 4B) and therefore the heat generated has more unshared surface area over which to spread and thus dissipate.

(14) A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, instead of a U-shaped FET cell, other shapes wherein the FET cells are distributed in two dimensions may be used, such as for example, a V-shaped FET cell, a cup-shaped cell, a concave shaped cell, a parabolic shaped cell. Further, the source and drain may be reversed in any electrical circuit application; with, in either circuit application, the gate controlling the flow of carriers between a source and a drain. Accordingly, other embodiments are within the scope of the following claims.