Method Of Forming A Polysilicon Sidewall Oxide Region In A Memory Cell

Abstract

Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

Claims

1. A method of fabricating a memory cell of a semiconductor device, the method comprising: depositing a conductive layer having a top surface and a side surface; forming an ONO layer over the top surface of the conductive layer; and forming a sidewall oxide layer adjacent the side surface of the conductive layer by a process including: depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer; and performing a rapid thermal oxidation (RTO) anneal.

2. The method of claim 1, wherein the sidewall oxide layer is formed by depositing the thin HTO film on the side surface of the conductive layer and subsequently performing the RTO anneal of the deposited thin HTO film.

3. The method of claim 1, wherein the deposited thin HTO film have a thickness in the range of 50-120 .

4. The method of claim 1, wherein the deposited thin HTO film have a thickness in the range of 60-80 .

5. The method of claim 1, wherein the RTO anneal is performed in a dry O.sub.2 environment, in the temperature range of 1000 C.-1200 C. for a duration in the range of 25-60 sec.

6. The method of claim 1, wherein the RTO anneal is performed in a dry O.sub.2 environment, in the temperature range of 1050 C.-1150 C. for a duration in the range of 30-40 sec.

7. The method of claim 1, wherein the sidewall oxide layer is formed by performing the RTO anneal of the conductive layer and ONO layer, and after the RTO anneal, depositing the thin HTO film over the side surface of the conductive layer.

8. The method of claim 3, wherein: the RTO anneal oxidizes the side surface of the conductive layer, and the thin HTO film is deposited on the oxidized side surface of the conductive layer.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0014] Example aspects and embodiment of the invention are described below with reference to the drawings, in which:

[0015] FIG. 1 shows a partial cross-sectional representation of a conventional EEPROM cell, showing a floating gate, ONO layer, and sidewall oxide covering a side of the floating gate.

[0016] FIG. 2 is an image of an example EEPROM structure exhibiting various undesirable features resulting from a known process for forming a sidewall oxide on the floating gate.

[0017] FIG. 3 is a cross-sectional view of a p-channel split-gate cell of an EEPROM, having a sidewall oxide formed according to the present invention.

[0018] FIG. 4 is a cross-sectional view of a p-channel split-gate cell of an EEPROM having a select transistor channel that is split on either side of the memory transistor, and having a sidewall oxide formed according to the present invention.

[0019] FIGS. 5A-5D illustrate an example process for forming a sidewall oxide on the side of an EEPROM floating gate, and a control gate over the floating gate, according to one embodiment.

[0020] FIGS. 6A-6D illustrate another example process for forming a sidewall oxide on the side of an EEPROM floating gate, and a control gate over the floating gate, according to another embodiment.

[0021] FIG. 7 illustrates example endurance testing results for EEPROM cells having a sidewall oxide produced by (a) a prior art technique of oxide deposition plus furnace annealing, (b) the method shown in FIGS. 5A-5D (HTO followed by RTO), and (c) the method shown in FIGS. 6A-6D (RTO followed by HTO).

[0022] FIG. 8 illustrates example data retention testing results for EEPROM cells having a sidewall oxide produced by (a) a prior art technique of oxide deposition plus furnace annealing, (b) the method shown in FIGS. 5A-5D (HTO followed by RTO), and (c) the method shown in FIGS. 6A-6D (RTO followed by HTO).

[0023] FIG. 9 is a TEM image of an example EEPROM structure including a floating gate and sidewall oxide produced by the method shown in FIGS. 5A-5D (HTO followed by RTO).

[0024] FIG. 10 is a TEM image of an example EEPROM structure including a floating gate and sidewall oxide produced by the method shown in FIGS. 6A-6D (RTO followed by HTO).

DETAILED DESCRIPTION

[0025] Embodiments of the present invention provide methods of forming a polysilicon sidewall oxide on the sidewall of a conductive layer in a memory cell, e.g., a sidewall oxide on the floating gate of an EEPROM cell. The disclosed methods of forming the sidewall oxide formation provides an improved memory cell as compared with known prior art techniques.

[0026] The disclosed methods may be applied to any suitable memory cell, e.g., an EEPROM cell or other memory cell having a conductive layer with a sidewall oxide, e.g., for inhibiting the leakage of voltage from the conductive layer. Two example EEPROM cells incorporating the sidewall oxide formed according to the disclosed methods are shown in FIGS. 3 and 4.

[0027] FIG. 3 illustrates a p-channel split-gate memory cell 10 of an EEPROM device according to one embodiment of the present invention. The memory cell 10 may include a memory transistor 12 and select transistor 14 formed on a silicon substrate 16. The substrate 16 may be defined by p-channels 18 and 20 and N-well 22. Reference numeral 24 may refer to a metal source contact, which may be disposed on p-channel 18, and reference numeral 26 may refer to a metal bitline (drain) contact, disposed on p-channel 20.

[0028] The memory transistor 12 may include a first conductive layer defining a floating gate 28, and a second conductive layer defining a control gate 30, which is shared with the select transistor 14, and a dielectric layer 32 disposed between the floating gate 28 and the control or shared gate 30, as shown in FIG. 3. The dielectric layer 32 may comprise an ONO film 34 and a stacked oxide layer 36 defining oxide layers above and below the ONO film 34. The dielectric layer 32 may thus be referred to as ONO layer 32. The stacked oxide layer 36 may have a vertical portion and a horizontal portion. The floating gate 28 has a top surface 38 and a side surface 40.

[0029] The ONO layer 32 is disposed between the floating gate 28 and shared gate 30, adjacent to the top surface 38 of the floating gate. The vertical portion of the stacked oxide layer 36 is disposed between the floating gate 28 and the shared gate 30, adjacent to a portion of the side surface 40 of the floating gate 28. The vertical portion of the stacked oxide layer, referred to herein as the sidewall oxide inhibits the leakage of charge from the side surface 40 of the floating gate 28. The sidewall oxide on the side surface 40 of the floating gate 28 may be formed by a process as disclosed herein, e.g., by depositing a thin high temperature oxide (HTO) film on the side surface 40 of the floating gate 28, followed by a rapid thermal oxidation (RTO) anneal of the structure, or alternatively, by performing an RTO followed by deposition of an HTO film.

[0030] The horizontal portion of the stacked oxide layer 36 is disposed between the shared gate 30 and the substrate 16, and serves as the thermal gate oxide for the select transistor. Because this layer does not contain silicon nitride, it does not trap electrons, and thus inhibits threshold voltage drift of the select transistor 14.

[0031] The select transistor 14 may include a wordline 30, which, as noted above, is also the gate shared with the memory transistor 12. A gate oxide 42 may also be provided between the floating gate 28 and the silicon substrate 16.

[0032] FIG. 4 illustrates another embodiment, in which the shared gate 30 is split on either side of the floating gate 28, i.e., the shared gate 30 surrounds the entire side surface 40 of the floating gate. In this embodiment, the vertical portion of the stacked oxide layer 36 is disposed adjacent to the entire side surface 40 of the floating gate 28. Also, the horizontal portion of the stacked oxide layer 36 is disposed between the shared gate 30 and the substrate 16 on all sides of the floating gate 28.

[0033] As with the sidewall oxide in the embodiment shown in FIG. 3, the sidewall oxide on the side surface 40 of the floating gate 28 in the embodiment of FIG. 4 may be formed by a process as disclosed herein, e.g., by depositing a thin high temperature oxide (HTO) film on the side surface 40 of the floating gate 28, followed by a rapid thermal oxidation (RTO) anneal of the structure, or alternatively, by performing an RTO followed by deposition of an HTO film.

[0034] The EEPROM cells shown in FIGS. 3 and 4 are only two example implementations of the present invention. The disclosed methods may be incorporated in any other suitable EEPROM cell or other memory cell having a sidewall oxide.

[0035] FIGS. 5A-5D illustrate an example process for forming an EEPROM memory cell 10 having a floating gate, a control gate, and a floating gate sidewall oxide formed according to one embodiment of the present invention.

[0036] After other steps in the process of manufacturing memory cell 10 have been performed, such as well formation, device isolation, threshold adjust implants, etc., the gate oxide 42 of the memory transistor 12 may be formed in any suitable manner, e.g., by growing a SiO.sub.2 layer 42 on substrate 16, which is formed of silicon (Si), as shown in FIG. 5A. Layer 42 may also be a tunnel oxide and may have any suitable thickness, e.g., in the range of 60-120 1. The floating gate 28 of the memory transistor and ONO film may then be formed in any suitable manner. For example, a polysilicon or amorphous polysilicon layer 104 may be deposited on the gate oxide 42, and doped with n- or p-dopants to make it conductive, e.g., by annealing in a furnace using (POCl.sub.3) gas, by doping the polysilicon layer 104 in-situ when deposited, or by ion implantation of the appropriate dopant species into the polysilicon layer 104, for example.

[0037] Next, an SiO.sub.2 layer 106, e.g., with a thickness in the range of 60-120 , may be deposited on the polysilicon layer 104. In some embodiments, the layer 106 may be thermally annealed, e.g., between 800-1000 C. to densify and improve the insulating quality of the oxide. This layer becomes the bottom oxide of the ONO layer 32 disposed on the top surface of the floating gate 28. Next, a silicon nitride (Si.sub.3N.sub.4) layer 108, e.g., with a thickness in the range of 60-200 , is deposited on the SiO.sub.2 layer 106. This layer becomes the silicon nitride layer of the ONO layer 32.

[0038] Next, a protective photoresist layer may be deposited on the stack and patterned with a mask to define the floating gate 28. The stack of films may then be anisotropically etched down to an SiO.sub.2 layer 42 on top of the substrate 16, resulting in the structure shown in FIG. 5A.

[0039] The wafer may then be cleaned using a standard wet chemical process, a dry plasma process, or other suitable process known to those of ordinary skill in the art.

[0040] As shown in FIG. 5B, a thin high temperature oxide (HTO) layer (SiO.sub.2) 114 is deposited over the stack, e.g., with a thickness between 50 and 120 , (e.g., between 60 and 80 , and in one example embodiment, about 70 thick. As shown, the HTO layer may be deposited over the Si.sub.3N.sub.4 layer 108, the vertical side surface 40 of the floating gate 28, and the gate oxide 42.

[0041] A rapid thermal oxidation (RTO) may then be performed to anneal and densify the HTO oxide 114. The RTO may be performed using any suitable parameters or recipe. In some embodiments, the RTO anneal is performed in a dry O.sub.2 environment, in the temperature range of 1000 C.-1200 C. for a duration in the range of 25-60 sec. In certain example embodiments, the RTO anneal is performed in a dry O.sub.2 environment, in the temperature range of 1050 C.-1150 C. for a duration in the range of 30-40 sec.

[0042] The RTO step causes oxidation of the structure, including lateral oxidation of the floating gate 28 and vertical oxidation of the uncovered portion of the substrate 16, to thereby increase the thickness of the oxide layer 114. The resulting (thickened) oxide layer is indicated as 114 in FIG. 5C, which includes (a) a lateral portion over the Si.sub.3N.sub.4 layer 108 which forms the top of the ONO layer 32, (b) a vertical sidewall oxide portion adjacent the side surface 40 of the floating gate 28, and (c) a lateral portion over the portion of the substrate 16 uncovered by the floating gate 28.

[0043] The lateral oxidation of the floating gate 28 due to the RTO step may be more uniform than other conventional techniques, and may cause less lateral oxide encroachment under the floating gate 28 (which undesirably thickens the tunnel oxide 42) and between the floating gate 28 and Si.sub.3N.sub.4 layer 108 (which undesirably thickens the ONO layer 32) as compared with conventional techniques.

[0044] In some embodiments, the total thickness of the SiO.sub.2 layer 114 following the RTO may be between 50 and 120 (e.g., between 60 and 80 ) above the Si3 N4 layer 108, between 100 and 500 (e.g., between 200 and 400 ) on the side surface 40 of the floating gate 28 (i.e., the sidewall oxide), and between 100 and 300 (e.g., between 200 and 250 ) above the substrate 16.

[0045] Next, the control gate (or shared gate) 30 of the EEPROM may be formed in any suitable manner, as illustrated in FIG. 5D. For example, a polysilicon or amorphous polysilicon layer 130 may be deposited on the ONO layer 32 and select transistor gate oxide (the horizontal portion of layer 36), and doped with n- or p-dopants to make the polysilicon layer conductive. Remaining steps to form remaining components of the memory cell, such as formation of source and drain regions and metal interconnect, can then be done to complete the fabrication process.

[0046] FIGS. 6A-6D illustrate another example process for forming an EEPROM memory cell 10 having a floating gate, a control gate, and a floating gate sidewall oxide formed according to another embodiment of the present invention. The embodiment of FIGS. 6A-6D is generally similar to the embodiment of FIGS. 5A-5D, except the rapid thermal oxidation (RTO) step is performed before (rather than after) depositing the thin high temperature oxide (HTO) film.

[0047] The process of forming the structure shown in FIG. 6A is similar to that described above with respect to FIG. 5A, and thus FIG. 6A is identical to FIG. 5A.

[0048] In this embodiment, the rapid thermal oxidation (RTO) may be performed on the structure shown in FIG. 6A, which may result in the structure shown in FIG. 6B. As shown in FIG. 6B, the RTO may cause lateral oxidation of the floating gate 28 and vertical oxidation of the uncovered portion of the substrate 16, to thereby define an oxide layer 114. The RTO anneal may be performed using any suitable parameters or recipe, e.g., any of the parameters or recipes disclosed above with respect to FIG. 5C.

[0049] After the RTO, a thin high temperature oxide (HTO) film (SiO.sub.2) 115 is deposited over the stack, as shown in FIG. 6C. As shown, the HTO layer may be deposited over the Si.sub.3N.sub.4 layer 108 and over the oxide layer 114 formed adjacent the floating gate 28 and substrate 16 by the RTO process. In some embodiments, the HTO film 115 may have a thickness between 50 and 120 (e.g., between 60 and 80 , and in one example embodiment, about 70 thick). The thin HTO film 115 may combine with the oxide layer 114 formed by the RTO to define an oxide layer 114, as shown in FIG. 6C. In some embodiments, the total thickness of the oxide layer 114 may be between 100 and 500 (e.g., between 200 and 400 ) on the side surface 40 of the floating gate 28 (i.e., the sidewall oxide), and between 100 and 300 (e.g., between 200 and 250 ) above the substrate 16.

[0050] As shown in FIG. 6D, a control gate (or shared gate) 30 may then be formed over the structure in any suitable manner, e.g., using techniques discussed above regarding FIG. 5D. Remaining steps to form remaining components of the memory cell, such as formation of source and drain regions and metal interconnect, can then be done to complete the fabrication process.

[0051] FIG. 7 illustrates three graphs arranged side-by-side showing example endurance testing results for EEPROM cells having a sidewall oxide produced by (a) left-side graph: a prior art technique of oxide deposition plus furnace annealing, (b) center graph: the method shown in FIGS. 5A-5D (HTO followed by RTO), and (c) right-side graph: the method shown in FIGS. 6A-6D (RTO followed by HTO).

[0052] As shown, the endurance performance, especially the Vtp high-margin degradation with endurance cycling at both 25 C. and 85 C., are improved in the memory cells produced using the sidewall oxide formation methods discussed above, as compared with memory cells using a prior art sidewall oxide formation process of applying an HTO followed by a furnace anneal.

[0053] FIG. 8 illustrates three graphs arranged side-by-side showing example data retention testing results for EEPROM cells having a sidewall oxide produced by (a) left-side graph: a prior art technique of oxide deposition plus furnace annealing, (b) center graph: the method shown in FIGS. 5A-5D (HTO followed by RTO), and (c) right-side graph: the method shown in FIGS. 6A-6D (RTO followed by HTO).

[0054] As shown, the data retention performance is improved in the memory cells produced using the sidewall oxide formation methods discussed above, as compared with memory cells using a prior art sidewall oxide formation process of applying an HTO followed by a furnace anneal.

[0055] FIG. 9 is a TEM image of an example EEPROM structure including a floating gate and sidewall oxide produced by the method shown in FIGS. 5A-5D (HTO followed by RTO).

[0056] FIG. 10 is a TEM image of an example EEPROM structure including a floating gate and sidewall oxide produced by the method shown in FIGS. 6A-6D (RTO followed by HTO).

[0057] As can be seen by comparing FIG. 9 (HTO followed by RTO) and FIG. 10 (RTO followed by HTO) with prior art FIG. 2 (HTO followed by furnace anneal), the structures resulting from the presently disclosed sidewall oxide formation processes (FIGS. 9 and 10) exhibit less lateral oxide encroachment into the ONO and tunnel oxide channel, a more uniform sidewall oxide thickness adjacent the floating gate sidewall, and less sharp corners at the base of the polysilicon control gate, which differences provide improved memory cell performance over the prior art.

[0058] In summary, a conventional two-step furnace sidewall oxide process causes performance problems on advanced EEPROM cells due to severe lateral encroachment under the ONO and channel. The presently disclosed process solutions replace the furnace oxidation with a RTO anneal process, either before or after the HTO oxide deposition. The presently disclosed may preserve more of the poly 1 (floating gate), provide a more uniform sidewall oxide, cause less lateral oxide encroachment underneath the ONO and tunnel channel, and have less sharp poly corners. Further, the disclosed solutions may be less expensive and simpler to implement than other prior art solutions and have better memory endurance and data retention reliability.

[0059] While the example embodiments discussed above involve the fabrication of p-channel cells, those of ordinary skill in the art will appreciate that the present invention is equally applicable to n-channel cells. It should further be recognized that embodiments of the present invention are independent of the method of programming and erasing the memory cell. Furthermore, the present invention is applicable to other split-gate cells in EEPROM devices and other memory cells in general. In addition, those of ordinary skill in the art should appreciate that other process steps (not forming a part of the present invention) are involved in fabrication of a memory cell than those explicitly described herein. Thus, the example embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention.