PWM signal generator circuit and related integrated circuit

Abstract

A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Claims

1. A Pulse-Width Modulated (PWM) signal generator circuit, comprising: a multiphase clock generator configured to generate phase-shifted clock phases having a same clock period and being phase shifted by a time corresponding to a fraction of the clock period, the PWM signal generator circuit configured to: generate a PWM signal having a given switching duration including a switch-on duration and a switch-off duration, determine for each switch-on duration a number of clock periods of the switch-on duration and a number of the fractions of the clock period of the switch-on duration, and determine for each switch-off duration a number of clock periods of the switch-off duration, and a number of the fractions of the clock period of the switch-off duration.

2. The PWM signal generator circuit of claim 1, further comprising: a clock switching circuit configured to generate a timer clock signal by selecting one of the phase shifted clock phases as the timer clock signal based on a selection signal.

3. The PWM signal generator circuit according to claim 2, further comprising: a timer circuit including one or more counters and one or more comparators, the timer circuit configured to: during the switch-on duration, vary a first count value in response to the timer clock signal and generate a first trigger when the first count value reaches a first integer number, the first integer number indicative of the number of clock periods of the switch-on duration, and during the switch-off duration, vary a second count value in response to the timer clock signal and generate a second trigger when the second count value reaches a second integer number, the second integer number indicative of the number of clock periods of the switch-off duration; a phase accumulator circuit configured to generate the selection signal by: during the switch-on duration, increasing the selection signal by a third integer number, the third integer number indicative of the number of fractions of the clock period of the switch-on duration, and during the switch-off duration, increasing the selection signal by a fourth integer number, the fourth integer number indicative of the number of fractions of the clock period of the switch-off duration; and a toggle circuit configured to: in response to said first trigger, set the PWM signal to low, and in response to said second trigger, set the PWM signal to high.

4. The PWM signal generator circuit according to claim 3, configured to receive at an input the first, second, third, and fourth integer numbers.

5. The PWM signal generator circuit according to claim 3, configured to: during the switch-on duration, determine whether the third integer number is smaller than n/2, where n is equal to a number of the phase-shifted clock phases, and in response to determining the third integer number is smaller than n/2, increase the first count value for a single clock cycle of said timer clock signal by two; and during the switch-off duration, determine whether the fourth integer number is smaller than n/2, and in response to determining the fourth integer number is smaller than n/2, increase the second count value for a single clock cycle of said timer clock signal by two.

6. The PWM signal generator circuit according to claim 3, configured to: during the switch-on duration, determine whether the third integer number is smaller than n/2, where n is equal to a number of the phase-shifted clock phases, and in response to determining the third integer number is smaller than n/2, decrease the first integer number by one; and during the switch-off duration, determine whether the fourth integer number is smaller than n/2, and in response to determining the fourth integer number is smaller than n/2, decrease the second integer number by one.

7. The PWM signal generator circuit according to claim 3, wherein the timer circuit includes a single counter configured to generate the first count value and the second count value, and wherein the single counter is reset at the beginning of each switch-on duration and each switch-off duration.

8. The PWM signal generator circuit according to claim 3, wherein the timer circuit includes a single counter configured to generate the first count value and the second count value, and wherein the single counter is reset only at the beginning of each switch-on duration.

9. The PWM signal generator circuit according to claim 3, wherein the phase accumulator circuit is configured to generate the selection signal by: in response to the first trigger, increasing the selection signal by the second integer number, and in response to the second trigger, increasing the selection signal by the fourth integer number.

10. The PWM signal generator circuit according to claim 3, wherein the clock switching circuit includes: for each of the phase shifted clock phases a respective transmission gate, each transmission gate configured to generate a respective gated clock phase based on the selection signal; and a combinational logic circuit configured to generate the timer clock signal by combining the gated clock phases.

11. An integrated circuit, comprising: a PWM signal generator circuit configured to: receive a number of phase-shifted clock phases having a same clock period and being phase shifted by a time corresponding to a fraction of the clock period; generate a PWM signal having a given switching duration including a switch-on duration and a switch-off duration; determine for each switch-on duration a number of clock periods of the switch-on duration and a number of the fractions of the clock period of the switch-on duration; and determine for each switch-off duration a number of clock periods of the switch-off duration, and a number of the fractions of the clock period of the switch-off duration.

12. The integrated circuit according to claim 11, wherein the PWM signal generator circuit includes: a clock switching circuit configured to select one of the phase shifted clock phases as a timer clock signal based on a selection signal.

13. The integrated circuit according to claim 12, wherein the PWM signal generator circuit includes: a timer circuit including one or more counters and one or more comparators, the timer circuit configured to: during the switch-on duration, vary a first count value in response to the timer clock signal and generate a first trigger when the first count value reaches a first integer number, the first integer number indicative of the number of clock periods of the switch-on duration, and during the switch-off duration, vary a second count value in response to the timer clock signal and generate a second trigger when the second count value reaches a second integer number, the second integer number indicative of the number of clock periods of the switch-off duration; a phase accumulator circuit configured to generate the selection signal by: during the switch-on duration, increasing the selection signal by a third integer number, the third integer number indicative of the number of fractions of the clock period of the switch-on duration, and during the switch-off duration, increasing the selection signal by a fourth integer number, the fourth integer number indicative of the number of fractions of the clock period of the switch-off duration; and a toggle circuit configured to: in response to the first trigger, set the PWM signal to low, and in response to the second trigger, set the PWM signal to high.

14. The integrated circuit according to claim 12, wherein the PWM signal generator circuit is configured to: during the switch-on duration, determine whether the third integer number is smaller than n/2, and in response to determining the third integer number is smaller than n/2, increase the first count value for a single clock cycle of the timer clock signal by two; and during the switch-off duration, determine whether the fourth integer number is smaller than n/2, and in response to determining the fourth integer number is smaller than n/2, increase the second count value for a single clock cycle of the timer clock signal by two.

15. The integrated circuit according to claim 12, wherein the PWM signal generator circuit is configured to: during the switch-on duration, determine whether the third integer number is smaller than n/2, and in response to determining the third integer number is smaller than n/2, decrease the first integer number by one; and during the switch-off duration, determine whether the fourth integer number is smaller than n/2, and in response to determining the fourth integer number is smaller than n/2, decrease the second integer number by one.

16. The integrated circuit according to claim 12, wherein the timer circuit includes a single counter configured to generate the first count value and the second count value, and wherein the single counter is reset at the beginning of each switch-on duration and each switch-off duration.

17. A method, comprising: receiving a number of phase-shifted clock phases having a same clock period and being phase shifted by a time corresponding to a fraction of said clock period; generating a PWM signal having a given switching duration including a switch-on duration and a switch-off duration; determining for each switch-on duration a number of clock periods of the switch-on duration and a number of the fractions of the clock period of the switch-on duration; and determining for each switch-off duration a number of clock periods of the switch-off duration, and a number of the fractions of the clock period of the switch-off duration.

18. The method of claim 17, further comprising: selecting one of the phase shifted clock phases as a timer clock signal based on a selection signal.

19. The method of claim 18, further comprising: during the switch-on duration, varying a first count value in response to the timer clock signal and generating a first trigger when the first count value reaches a first integer number, the first integer number indicative of the number of clock periods of the switch-on duration; and during the switch-off duration, vary a second count value in response to the timer clock signal and generate a second trigger when the second count value reaches a second integer number, the second integer number indicative of the number of clock periods of the switch-off duration.

20. The method of claim 19, further comprising: during the switch-on duration, increasing the selection signal by a third integer number, the third integer number indicative of the number of fractions of the clock period of the switch-on duration; during the switch-off duration, increasing the selection signal by a fourth integer number, the fourth integer number indicative of the number of fractions of the clock period of the switch-off duration; setting the PWM signal to low, in response to the first trigger; and setting the PWM signal to high, in response to the second trigger.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) The embodiments of the present disclosure will now be described with reference to the drawings, which are provided purely to way of non-limiting example and in which:

(2) FIG. 1 shows an example of a PWM signal;

(3) FIG. 2 shows an example of a circuit generating multi-phase clock signals;

(4) FIG. 3 shows an example of the waveforms of clock phases provided by the circuit of FIG. 2;

(5) FIG. 4 shows an example of the fine tuning of the switch-on duration of a PWM signal by means of multi-phase clock signals;

(6) FIG. 5 shows an embodiment of the fine tuning of both the switch-on duration and the switch-off duration of a PWM signal by means of multi-phase clock signals;

(7) FIGS. 6A and 6B show embodiments of a timer circuit in accordance with the present disclosure;

(8) FIG. 7 shows exemplary waveforms generated by the timer circuits of FIGS. 6A and 6B;

(9) FIG. 8 shows an embodiment of a PWM generator circuit; and

(10) FIGS. 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 12C and 12D show various details of the circuits of FIGS. 6A, 6B and 8.

DETAILED DESCRIPTION

(11) In the ensuing description, various specific details are illustrated to enable an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.

(12) Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(13) The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(14) In FIGS. 5 to 12 described below, parts, elements or components that have already been described with reference to FIGS. 1 to 4 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description.

(15) As explained in the foregoing, various embodiments of the present description relate to a PWM signal generator circuit configured to generate a high resolution PWM signal. In particular, in various embodiments, the PWM signal generator circuit is configured to receive a plurality of clock phases ϕ.sub.0 . . . ϕ.sub.n and generate both the rising and the falling edges of the PWM signal as a function of these clock phases ϕ.sub.0 . . . ϕ.sub.n, thereby controlling both the PWM duty cycle and the PWM frequency with a higher resolution.

(16) FIG. 5 shows the general operation of a first embodiment.

(17) In the embodiment considered, the PWM signal generator circuit receives the first clock phases ϕ.sub.0 (and/or the last clock phase ϕ.sub.n=ϕ.sub.0) and the intermediate clock phases ϕ.sub.1 . . . ϕ.sub.n-1. In some embodiments, the PWM signal generator circuit includes a multiphase clock generator that generates the various clock phases, which may include any multiphase clock generator configured to generate the clock phases described herein. Possible solutions for generating such clock phases are already described in the introduction of the present disclosure, and the relevant description applies in its entirety (see in particular the description of FIG. 2). That is, in some embodiments, the multiphase clock generator circuit of various embodiments of the present disclosure may be as described, for example, with respect to FIG. 2.

(18) Moreover, in the embodiment considered, the PWM signal generator circuit is configured to generate a PWM signal, wherein: the switching duration T.sub.SW may be set to T.sub.SW=i.Math.T.sub.CLK+j.Math.T.sub.CLK/n; and the switch-on time T.sub.ON may be set to T.sub.ON=k.Math.T.sub.CLK+l.Math.T.sub.CLK/n.

(19) In various embodiments, the parameters i, j, k and l integer values, wherein the parameters i, j, k and l may be programmable.

(20) Specifically, in the example shown in FIG. 5, it is assumed that n=17, e.g., the PWM signal generator circuit receives the clock phases ϕ.sub.0 . . . ϕ.sub.16, and the PWM signal generator circuit is configured to generate a PWM signal with:
T.sub.SW=i.Math.T.sub.CLK+10.Math.T.sub.CLK/17=T.sub.i+10.Math.T.sub.CLK/17, a duty cycle of 50% (i.e., T.sub.ON=T.sub.OFF=T.sub.SW/2), i.e.,
T.sub.ON=T.sub.OFF=T.sub.i/2+5.Math.T.sub.CLK/17.

(21) In the example considered, it will be assumed for simplicity that i is an even number, and k=p=i/2.

(22) Specifically, in the embodiment considered, the PWM signal generator circuit is configured to use during the first switch-on period T.sub.1 the phase ϕ.sub.0 as clock signal for the digital counter counting the time period T.sub.i/2=k.Math.T.sub.CLK, and (as will be described in greater detail in the following) the PWM signal generator circuit adds at the end a fraction of 5/17 of the period T.sub.CLK by using the phase ϕ.sub.5.

(23) However, instead of then tracking the accumulation of the various fractions, the PWM signal generator circuit uses then during the following switch-off period T.sub.2 the phase ϕ.sub.5 (i.e., the phase used to add the fraction) as clock signal for the timer circuit (i.e., the digital counter counting the time period p.Math.T.sub.CLK). Moreover, the PWM signal generator circuit adds at the end again the respective fraction of 5/17 of the period T.sub.CLK by using in this case the phase ϕ.sub.10, insofar as the phase ϕ.sub.10 is shifted by a delay of 5.Math.T.sub.CLK/17 with respect to the phase ϕ.sub.5.

(24) Next, the PWM signal generator circuit use during the second switch-on period T.sub.3 the phase ϕ.sub.10 as clock signal for the digital counter counting the time period k.Math.T.sub.CLK, and the PWM signal generator circuit adds at the end a fraction of 5/17 of the period T.sub.CLK by using this time the phase ϕ.sub.15, insofar as the phase ϕ.sub.15 is shifted by a delay of 5.Math.T.sub.CLK/17 with respect to the phase ϕ.sub.10.

(25) Similarly, the PWM signal generator circuit use during the following switch-off period T.sub.4 the phase ϕ.sub.15 as clock signal for the digital counter counting the time period p.Math.T.sub.CLK, and the PWM signal generator circuit adds at the end a fraction of 5/17 of the period T.sub.CLK by using this time the phase ϕ.sub.3, insofar as the phase ϕ.sub.3 is shifted by a delay of 5.Math.T.sub.CLK/17 with respect to the phase ϕ.sub.15.

(26) This operation continues also for the following switch-on and switch off periods.

(27) In various embodiments, the PWM generator circuit is thus configured to generate a PWM signal, wherein: the switch-on duration corresponds to T.sub.ON=k.Math.T.sub.CLK+l.Math.T.sub.CLK/12; and the switch-off duration corresponds to T.sub.OFF=p.Math.T.sub.CLK+q.Math.T.sub.CLK/n.

(28) In various embodiments, the parameter n (number of delay stages/phase) is fixed at a hardware level. However, the number n could also be programmable, e.g., by using in FIG. 2 a given fixed number of delay stages (e.g., 32) and selecting the n-th phase (and not necessarily the last one) as feedback signal provided to the phase detector PD. In fact, in this way, the control loop will still be locked to the n-th phase ϕ.sub.n, with T.sub.DU=T.sub.CLK/n.

(29) Thus, in various embodiments, the timer circuit of the PWM signal generator circuit (comprising the counter circuit and the comparator circuit) is configured to: during a switch-on period T.sub.ON, increase a count value from a reset value until the count value reaches the integer value k; and during a switch-off period T.sub.OFF, increase a count value from a reset value until the count value reaches the integer value p.

(30) However, in general, the timer circuit may also monitor the switching duration T.sub.SW, i.e., the timer circuit of the PWM signal generator circuit (comprising the counter circuit and the comparator circuit) may be configured to: during a switch-on period, increase a count value from a reset value until the count value reaches the integer value k; and during a switch-off period, increase the count value used during the switch-on period until the count value reaches the integer value i.

(31) Thus, in various embodiments, the PWM signal generator circuit is configured to determine the parameters k/l, and at least one of p/q, and i/j wherein: in case of a switch-on period T.sub.ON, k corresponds to the integer number of clock cycles of the clock signal CLK and l corresponds to the integer number of the fractions 1/n of a clock cycle of the clock signal CLK; in case of a switch-off period T.sub.OFF, p corresponds to the integer number of clock cycles of the clock signal CLK and q corresponds to the integer number of the fractions 1/n of a clock cycle of the clock signal CLK; and in case of a switching period T.sub.SW, i corresponds to the integer number of clock cycles of the clock signal CLK and j corresponds to the integer number of the fractions 1/n of a clock cycle of the clock signal CLK.

(32) Specifically, in view of the above definitions:
T.sub.ON=k.Math.T.sub.CLK+l.Math.T.sub.CLK/n  (2)
T.sub.OFF=p.Math.T.sub.CLK+q.Math.T.sub.CLK/n  (3)
T.sub.SW=T.sub.ON+T.sub.OFF=i.Math.T.sub.CLK+j.Math.T.sub.CLK/n  (4)
the integer values i and j are related to the integer values k, l, p and q according to the following equations: in case (l+q)<n (without overflow):
i=k+p;j=l+q;  (5) in case (l+q)>n (with overflow):
i=k+p+l;j=l+q−n.  (6)

(33) Thus, in various embodiments, the PWM generator circuit is configured to receive at least two of the parameters i, k and p, and at least two of the parameters j, l and q. For example, the PWM signal generator circuit may directly receive the parameters k/l and/or p/q and/or i/j, such as: data identifying (e.g., corresponding to) the parameters k/l; and data identifying (e.g., corresponding to) the parameters p/q.

(34) Alternatively, the PWM signal generator circuit may receive other data permitting a calculation of these parameters according to equations (5) and (6), such as: data identifying the switching duration T.sub.SW, such as the above-mentioned parameters i and j, and one of: data identifying (e.g., corresponding to) the parameters k/l; data identifying (e.g., corresponding to) the parameters p/q; or data identifying the duty cycle

(35) As shown in FIG. 6A, in various embodiments, the PWM signal generator circuit comprises a timer circuit 102 comprising a digital counter circuit 104 configured to vary (i.e., increase or decrease) an integer count value CNT in response to a clock signal CLK_TMR and a comparator circuit 106 configured to compare the count value CNT with a respective integer comparison threshold.

(36) As shown in FIG. 6A, the same counter 104 and comparator 106 may be used for both the switch-on period and the switch-off period by selecting, e.g., via a multiplexer 108, the parameter k or p as comparison threshold. Accordingly, by resetting the counter 104 via the signal at the output of the comparator 106, the same counter 104 may be used to monitor the switch-on period and the switch-off period. However, the counter 104 may also be used to monitor the switch-on period and the duration T.sub.SW. For example, in this case, the multiplexer 108 may receive the parameters k and i, and the counter 104 may only be reset when the count value CNT reaches the value i.

(37) Alternatively, as shown in FIG. 6B, a respective counter 104a and 104b and comparator 106a and 106b may be used for the switch-on period and the switch-off period, wherein the comparator 106a compares a count value CNTa provided by the counter 104a with the parameter k and the comparator 106b compares a count value CNTb provided by the counter 104ab with the parameter p.

(38) In various embodiments, the timer circuit 102 is configured to generate one or more trigger signal when the output of the comparator indicates that the count value has reached the comparison threshold, e.g., by using a signal EOC_TMR at the output of the comparator 106, or respective signal EOC_TMRa and EOC_TMRb at the outputs of the comparators 106a and 106b.

(39) In the embodiments considered, the signal EOC_TMR (FIG. 6A) or the signals EOC_TMRa and EOC_TMRb (FIG. 6B) are provided to a control circuit 110 with selects the clock signal CLK_TMR for timer circuit 102, in particular the counter 104 (104a/104b), as a function of: during a switch-on period, the parameter 1; and during a switch-off period, the parameter q.

(40) Specifically, even when monitoring the end of the switching duration T.sub.SW, it is preferably to obtain, e.g., calculate according to equations (5) and (6), the parameter q, because this parameter indicates the additional fractions which have to be added with respect to the previous switch-on period.

(41) For example, the control circuit 110 may select the clock signal CLK_TMR by driving via a selection signal SEL1 a multiplexer 100 receiving at input the clock phases ϕ.sub.0 . . . ϕ.sub.n-1. Similarly, the control signal may drive via a selection signal SEL2 a multiplexer 112 in order to select either the parameter 1 or the parameter q, i.e., the selection signal indicates whether the current period is a switch-on period or a switch-off period, and may thus also be used to drive the multiplexer 108.

(42) Specifically, in various embodiments, in response to a trigger in the signal EOC_TMR (FIG. 6A) or the signals EOC_TMRa and EOC_TMRb (FIG. 6B), the control circuit 110 is configured to change the logic value of the selection signal SEL1: during a switch-on period, as a function of the parameter l; and during a switch-off period, as a function of the parameter q.

(43) Specifically, in various embodiments, the control circuit also performs a modulo operation in order to maintain the selection signal SEL1 between 0 and n−1. Accordingly, in response to a trigger in the signal EOC_TMR (FIG. 6A) or the signals EOC_TMRa and EOC_TMRb (FIG. 6B), the control circuit 110 varies the selection signal SEL1: during a switch-on period, SEL1=(SEL1+l) mod n; and during a switch-off period, SEL1=(SEL1+q) mod n.

(44) Thus, essentially, the control circuit 110 implements a phase accumulator circuit, which adds to the currently selected phase either 1 or q, wherein the parameters q may be calculated, e.g., as shown in equations (5) and (6) as a function of the parameters j and n.

(45) Finally, in various embodiments, the respective period (either a switch-on or switch-off period) is terminated and the following period is started with the next clock pulse (i.e., with the next rising or falling edge based on which type of edge is used by the timer circuit 102) of the selected clock phase.

(46) Thus essentially, during a switch-on period T.sub.ON the trigger signal EOC_TMR (or EOC_TMRa) is generated after a time k.Math.T.sub.CLK, and by changing the clock signal CLK_TMR the switch-on period is terminated, thereby starting the following switch-off period, after an additional time l/n.Math.T.sub.CLK. Similarly, during a switch-off period T.sub.OFF the trigger signal EOC_TMR (or EOC_TMRb) is generated after a time p.Math.T.sub.CLK (which may be obtained, e.g., by resetting the counter 104 and waiting for p cycles or by waiting until the count value reaches i), and by changing the clock signal CLK_TMR the switch-off period is terminated, thereby starting the following switch-on period, after an additional time q/n.Math.T.sub.CLK.

(47) For example, this is shown in FIG. 7, wherein during a switch-on period, the timer circuit uses a clock phase CLK_TMR=ϕ.sub.x, and the trigger signal EOC_TMR is set after, e.g., k=9 periods of the phase ϕ.sub.x, e.g., with the 10.sup.th rising edge. In response to the trigger signal EOC_TMR (EOC_TMRa) the control circuit selects a new phase CLK_TMR=ϕ.sub.y (with y=(x+l) mod n). Moreover, in response to the immediately following (e.g., rising) edge in the signal ϕ.sub.y, the PWM signal generator circuit terminates the switch-on period and starts the following switch-off period, thereby introducing an additional time corresponding a fraction l/n of the clock period.

(48) In the embodiment considered, during the following switch-off period, the timer circuit uses then the clock phase CLK_TMR=ϕ.sub.y, and the trigger signal EOC_TMR is set after, e.g., p=8 periods of the phase ϕ.sub.y, e.g., with the 9.sup.th rising edge. In response to the trigger signal EOC_TMR (EOC_TMRb) the control circuit selects a new phase CLK_TMR=ϕ.sub.z (with z=(y+q) mod n). In response to the immediately following (e.g., rising) edge in the signal ϕ.sub.z, the PWM signal generator circuit terminates the switch-off period and starts the following switch-on period, thereby introducing an additional time corresponding a fraction q/n of the clock period.

(49) In the previous embodiments, the control circuit 110 is configured to drive the selection circuit 100 in order to changes the phase ϕ assigned to the clock signal CLK_TMR from the current phase ϕ(t) (e.g., ϕ.sub.0) to the next phase ϕ(t+1) (e.g., ϕ.sub.5) in response to the signal EOC_TMR, thereby adding the fractions (l or q) at the end of the respective switch-on or switch-off period.

(50) However, in various embodiments, the switching from the current phase (kW to the next phase ϕ(t+1) may occur at any instant during the respective period. In this case, the control unit 110 may also be configured to either increase/decrease sequentially, e.g., in response to the clock signal CLK_TMR, the selection signal SEL1 from the old phase ϕ(t) to the new phase ϕ(t+1) (e.g., ϕ.sub.0, ϕ.sub.1, ϕ.sub.2, ϕ.sub.3, ϕ.sub.4, ϕ.sub.5) or by switching directly to the new phase.

(51) Generally, while reference has been made to periods of the clock signal CLK, indeed the phases ϕ.sub.0 . . . ϕ.sub.n-1 may also have a different clock period T.sub.PLL, e.g., the frequency f.sub.PLL=1/T.sub.PLL may be a multiple of the clock frequency f.sub.CLK, e.g., by using a frequency divider in the feedback loop of the phase ϕ.sub.n-1. Accordingly, in general: the switch-on duration corresponds to T.sub.ON=k.Math.T.sub.PLL+l.Math.T.sub.PLL/n; and the switch-off duration corresponds to T.sub.OFF=p.Math.T.sub.PLL+q.Math.T.sub.PLL/n.

(52) FIG. 8 shows a second embodiment of a PWM signal generator circuit.

(53) Specifically, in the embodiment considered, the PWM signal generator circuit comprises again a timer circuit 102, a clock switching circuit 100′ and a control circuit/phase accumulator 110′.

(54) Specifically, with respect to FIGS. 6A and 6B, the clock switching circuit 100′ is not implemented with a mere multiplexer, but with a circuit which directly generates, in response to the trigger signal EOC_TMR provided by the timer circuit 102, the clock signal CLK_TMR for the timer circuit as a function of the selection signal SEL1 provided by the control circuit 110′. Generally, as described in the foregoing, also any other trigger signal may be used to assign to the clock signal CLK_TMR a new clock phase as a function of the selection signal SEL1.

(55) For example, a possible embodiment of the clock switching circuit 100′ is shown in FIGS. 9A and 9B.

(56) In the embodiment considered, the selection signal SEL1 (indicative of the next clock phase), is provided to a series of optional latches 1000 configured to store the value of the signal SEL1 in response to the trigger signal EOC_TMR. Substantially, these latches 1000 ensure that the circuit samples the value of the signal SEL1 only when a trigger in the signal EOC_TMR is generated.

(57) In the embodiment considered, each clock phase ϕ.sub.0 . . . ϕ.sub.n-1 is provided to a respective transmission gate (gated clock cells) 1002.sub.0 . . . 1002.sub.n being enabled as a function of the selections signal SEL1 or optionally the latched selections signal SEL1, thereby generating respective (gated) signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd. For example, in various embodiments, the selection signal comprises (n) bits SEL.sub.0 . . . SEL.sub.n-1 and uses a one-hot encoding, wherein a given bit is associated univocally with a given clock phase ϕ.sub.0 . . . ϕ.sub.n-1, i.e., only one of the bits SEL.sub.0 . . . SEL.sub.n-1 is set and indicates that the respective clock phase ϕ.sub.0 . . . ϕ.sub.n-1 may pass through the respective transmission gate 1002.sub.0 . . . 1002.sub.n-1, while the other clock phases ϕ.sub.0 . . . ϕ.sub.n-1 cannot pass through the respective transmission gates 1002.sub.0 . . . 1002.sub.n-1. In general, also other encoding schemes may be used for the selection signal (such as a binary encoding), and the transmission gates may be driven via a decoder circuit configured to generate the one-hot encoded drive signals for the transmission gates 1002.sub.0 . . . 1002.sub.n-1 as a function of the selection signal SELL

(58) As shown in FIG. 9B, the signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd are then provided to a combinational logic circuit 1004 configured to generate at output the clock signal CLK_TMR for the timer circuit 102 by combining the signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd. For example, in various embodiments the signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd are combined via a logic OR operation, e.g., implemented with a cascaded structure of a plurality of OR gates OR1, OR2, OR3, etc.

(59) FIG. 10A shows the operation of the clock switching circuit 100′ at the example of a selection signal SEL1 having in sequence the value k, x and y, thereby activating (in response to the trigger signal EOC_TMR) in sequence the clock phases ϕ.sub.k_gtd, ϕ.sub.x_gtd and ϕ.sub.y_gtd.

(60) Thus, in case the selection signal SEL1 changes, the clock signal CLK_TMR switches from a first clock phase to a second clock phase in response to the selection signal.

(61) Specifically, as shown in FIG. 10B, when the second clock phase (ϕ.sub.x_gtd) goes to high (rising edge), while the first clock phase (ϕ.sub.k_gtd) is still high, the resulting clock signal CLK_TMR will have a single clock pulse with a duration being greater than the clock period T.sub.PLL of the clock phases ϕ.sub.0 . . . ϕ.sub.n-1, thereby essentially losing a clock cycle.

(62) Usually this occurs when the respective fraction l or q is smaller than n/2.

(63) Conversely, as shown in FIG. 10C, when the second clock phase (ϕ.sub.y_gtd) goes to high (rising edge), while the first clock phase (d).sub.td) is low, the resulting clock signal CLK_TMR will have a single clock pulse, with a duration being smaller than the clock period T.sub.PLL of the clock phases ϕ.sub.0 . . . ϕ.sub.n-1. Usually this occurs when the respective fraction l or q is greater than n/2.

(64) Thus, the lost clock edge (FIG. 10B) should be taken into account in order to correctly determine the duration of the respective time interval. Specifically, in various embodiments, in case a clock cycle is lost, i.e., the respective fraction l or q is smaller than n/2, the PWM signal generator circuit is configured to increase the timer circuit 102 by an additional clock cycle, i.e., the timer 102 is increase by 2 and not only 1 for a single clock cycle.

(65) FIG. 11A shows a possible embodiment of the timer circuit 102.

(66) Specifically, in the embodiment considered, the counter 104 is implemented with an accumulator comprising: a register 1040 providing at an output the count value CNT, wherein the register 1040 is configured to store a signal REG_IN at a respective input in response to the clock signal CLK_TMR; and a digital adder 1042, configured to generate the signal REG_IN at the input of the register 1040 by adding an increment value INC to the count value CNT.

(67) In the embodiment considered, the increment value INC may be set either to “1” or “2”, e.g., via a multiplexer 1044. Specifically, the selection is driven via a selection signal SEL3 provided by the control circuit 110 (or similarly by the control circuit 110′).

(68) Specifically, in the embodiment considered, the control circuit 110 comprises: a digital comparator 1100 configured to determine whether the fraction value l or q of the current switch-on or switch-off period is greater than n/2; and a circuit 1102 configured to generate a selection signal SEL3 as a function of the comparison signal generated by the comparator 1100 and a trigger signal indicating the start of a new switch-on or switch-off period, such as the signal EOC_TMR or, in the general case, as a function of the comparison signal generated by the comparator 1100 and a generic trigger signal whose length is one CLK_TMR cycle and generated in any appropriate instant during the switch-on or switch-off period.

(69) Specifically, in the embodiment considered, the multiplexer 112 already provide the fraction value for the current period, wherein the selection signal SEL2 indicates whether the current period is a switch-on or switch-off period. Accordingly, the comparator 1100 may receive at input the signal provided by the multiplexer 112 and thus generates a comparison signal indicating whether the fraction value l or q is greater than n/2. Specifically, the circuits 110 and 112 are configured: when the signal at the output of the comparator indicates that the fraction l or q (based on the current period) is greater than n/2 or the trigger signal (e.g., EOC_TMR) is not set, drive the multiplexer 1044 via the signal SEL3 in order to selected the value “1”, whereby the accumulator 1040/1042 is increased in response to the clock signal CLK_TMR by “1”; and when the signal at the output of the comparator indicates that the fraction l or q (based on the current period) is smaller than n/2 and the trigger signal (e.g., EOC_TMR) is set, drive the multiplexer 1044 via the signal SEL3 in order to selected the value “2”, whereby the accumulator 1040/1042 is increased in response to the clock signal CLK_TMR by “2”.

(70) Accordingly, substantially, the timer circuit 104 is configured to increase for one clock cycle of the signal CLK_TMR (i.e., a single cycle for each switch-on or switch-off period) the count value by two (“2”) when the fraction l or q (based on the current period) is smaller than n/2.

(71) Conversely, FIG. 11B shows that a similar result may be obtained by adapting directly the threshold value used by the comparator 106.

(72) Specifically, in the embodiment considered, the increment value INC is always set to “1”, and an additional digital subtractor is provided which is configured, e.g., via a multiplexer 1048, to: subtract the value “1” from the current threshold selected by the multiplexer 108 (k or p); or maintain the threshold value, e.g., by subtracting the value “0” from the current threshold selected by the multiplexer 108 (k or p).

(73) In general, the embodiments may also be combined, i.e., during a switch-on duration may be implemented either the “plus-two” mechanism (FIG. 11A) or the adaption of the threshold k (FIG. 11B), and during a switch-off duration may be implemented either the “plus-two” mechanism or the adaption of the threshold p.

(74) Accordingly, in the embodiments considered, the circuits 1100/1102 inform the timer circuit 102 that a counting edge has been missed or will be missed due to clock combination shown in FIG. 9B. This missing edge information (i.e., the signal SEL3) can be computed by the control circuit/phase accumulator machine 110/110′ that controls the fine delay selection and generates the phase selection change SEL1 (indicative of the next clock phase to be used for fine tuning of PWM signal). In fact, if the new phase selection selects a clock having its rising edge appearing during the on-time of the running clock, the combined CLK_TMR will have a longer on-time and the edge of the next selected clock phase, used in the clock combination circuitry of FIG. 9B, will be missed. This happens if the phase selection change is smaller than the half of number of available phases i.e., this occurs when the respective fraction l or q is smaller than n/2 (e.g., └17/2┘=8).

(75) Using this clock change property, the timer may be incremented by “1” or “2”, or the threshold of the comparator 106 may be adapted with respect to this internal flag generated as shown in FIG. 11A or 11B.

(76) In various embodiments, the PWM signal is switched in response to the next rising edge of the new clock phase, i.e., the selected clock phase ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd of the following switch-on or switch-off period. However, the PWM signal may also be changed in response to the rising edge of the trigger signal EOC_TMR in the case of a SELL signal generated in any appropriate instant during the given time slot/period.

(77) For example, as shown in FIG. 8, the PWM signal generator circuit may comprise a toggle circuit 114 configured to generate the PWM signal as a function of the signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd and the trigger signal EOC_TMR.

(78) Generally, any suitable circuit may be used to toggle the level of the PWM signal in response to the signal EOC_TMR (or EOC_TMRa and EOC_TMRb) and the new clock phase.

(79) For example, FIG. 12A shows an embodiment of the toggle circuit 114. Specifically, the toggle circuit 114 comprise a rising edged detector circuit. Specifically, in the embodiment considered, the toggle circuit comprises for each of the signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd a respective rising edge detector 1140.sub.0 . . . 1140.sub.n-1, which is enabled as a function of the signal EOC_TMR.

(80) Specifically, as shown in FIGS. 12B, 12C and 12D, in response to the rising edge of the current clock phase (e.g., ϕ.sub.k_gtd in FIG. 12C), the signal EOC_TMR will be set after a brief delay. In response to the trigger in the signal EOC_TMR, the circuit 100′ will switch to the new clock phase (e.g., ϕ.sub.x_gtd in FIG. 12C). Thus, no additional rising edge of the old clock signal (e.g., ϕ.sub.k_gtd in FIG. 12C) occurs. Thus, in response to the following rising edge in the new clock phase (e.g., ϕ.sub.x_gtd in FIG. 12C) the respective edge detector 1140 will set its output (e.g., to high), because also the signal EOC_TMR is still set.

(81) Accordingly, in the embodiment considered, the output of the various rising edge detector 1140.sub.0 . . . 1140.sub.n-1 may be connected to a combinational logic circuit, e.g., implementing a logic OR function (FIG. 12A shows schematically a logic OR gate OR4, that may correspond to the last OR gate of a chain of OR gates, e.g., comprising in cascade 6 OR gates having three inputs, 2 OR gates having 2 inputs and the OR gate OR4) for this purpose but, generally speaking, it can be implemented with a different number and topology of gates as a result of a different balancing process with respect to speed and to the number of clock phases), which generates at output a trigger signal TRIG indicating that the logic level of the PWM signal has to change.

(82) Accordingly, in the embodiment considered, the signal TRIG may be used to drive a flip-flop FF1 in order to invert the output of the flip-flop FF1, wherein the PWM signal is generated as a function (and preferably corresponds to) the signal at the output of the flip-flop FF1.

(83) For example, in the embodiment considered, the flip-flop FF1 is implemented with a D-type flip-flop, receiving at the data terminal D via an inverter INV1 the inverted output signal of the flip-flop FF1, thereby inverting the output of the flip-flop FF1 in response to the trigger signal TRIG.

(84) Of course, without prejudice to the principle of the disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure, as defined by the ensuing claims.

(85) The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.