Transimpedance gain circuit for temporally differentiating photo-sensing systems in dynamic vision sensors

Abstract

The invention relates to a transimpedance gain circuit for temporally differentiating photo-sensing systems in dynamic vision sensors, which uses at least one photodiode and at least two in-series transistors, each of the transistors being connected in diode configuration and being positioned at the output of the photodiode. The output current from the photodiode flows through the drain-source channels of the transistors and the source of the last transistor in series is connected to a voltage selected from ground voltage, a constant voltage or a controlled voltage.

Claims

1. A transimpedance gain circuit for temporally differentiating photo-sensing systems in dynamic vision sensors, which employs at least one photodiode, wherein the transimpedance gain circuit comprises: at least two in-series transistors, each one of the at least two in-series transistors being connected in diode configuration and being positioned at an output of the at least one photodiode; and a current mirror configured to control polarity of a current generated by the at least one photodiode, wherein the current mirror comprises electric current copying and inversion means and electric current amplification means, and wherein the current mirror is positioned between the at least one photodiode and the at least two in-series transistors, wherein the at least two in-series transistors are configured to be fed by an output current of the current mirror, which is a copy of the current generated by the at least one photodiode, such that the output current of the current mirror flows through drain-source channels of the at least two in-series transistors, and wherein the last in-series transistor of the at least two in-series transistors has a source connected to a voltage selected between a ground voltage, a constant voltage and a controlled voltage.

2. The transimpedance gain circuit according to claim 1, wherein the at least two in-series transistors have an exponential type current-voltage characteristic.

3. The transimpedance gain circuit according to claim 1, wherein the at least two in-series transistors are FET transistors biased in weak inversion.

4. The transimpedance gain circuit according to claim 1, wherein the transimpedance gain circuit comprises a biasing circuit for automatically controlling a gain of the current mirror, said biasing circuit being positioned between the current mirror and the at least two in-series transistors.

5. The transimpedance gain circuit according to claim 1, wherein a logarithmic dependence exists between an output voltage versus the current generated by the at least one photodiode.

6. A current amplification stage comprising the transimpedance gain circuit according to claim 1, and a transconductance circuit connected at an output of the transimpedance gain circuit.

7. A voltage amplification stage comprising the transimpedance gain circuit according to claim 1, and a transconductance circuit, the transimpedance gain circuit being connected at an output of the transconductance circuit.

8. A method of reducing mismatch among pixels, the method comprising providing a transimpedance gain circuit, and connecting the transimpedance gain circuit to a derivative circuit; introducing an input signal; and eliminating a continuous voltage of the input signal at an output of the transimpedance gain circuit, wherein the transimpedance gain circuit employs at least one photodiode, wherein the transimpedance gain circuit comprises: at least two in-series transistors, each one of the at least two in-series transistors being connected in diode configuration and being positioned at an output of the at least one photodiode; and a current mirror configured to control polarity of a current generated by the at least one photodiode, wherein the current mirror comprises electric current copying and inversion means and electric current amplification means, and wherein the current mirror is positioned between the at least one photodiode and the at least two in-series transistors, wherein the at least two in-series transistors are configured to be fed by an output current of the current mirror which is a copy of the current generated by the at least one photodiode, such that the output current of the current mirror flows through drain-source channels of the at least two in-series transistors, and wherein the last in-series transistor of the at least two in-series transistors has a source connected to a voltage selected between a ground voltage, a constant voltage and a controlled voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is an example of an embodiment of the present invention, comprising one single stage.

(2) FIG. 2 is an example of an embodiment of the invention, wherein the circuit is composed of two stages.

(3) FIG. 3 is an example of an embodiment in the circuit, wherein the circuit comprises having two stages, each one of which has a gain equal to 3.

DESCRIPTION OF VARIOUS EXAMPLE EMBODIMENTS OF THE INVENTION

(4) Below is an illustrative and non-limiting description of various particular embodiments of the invention, making reference to the numbering adopted in the figures.

(5) In the present invention, the circuit that transforms the photocurrent to a voltage, by means of a logarithmic conversion, carries out, implicitly, a voltage amplification with low mismatch of the gain between the various pixels within the same microchip.

(6) Therefore, FIG. 1 shows the most basic embodiment of the circuit, object of the invention. The particular embodiment comprises a photodiode (1), which generates a photocurrent I.sub.ph, which is amplified by means of a current mirror (2) having a gain A. The amplified current leads to a chain of N transistors (3, 4 and 5), N being a natural number, all of which have connected their gate to their drain, which is known by connection in diode configuration. Please note that FIG. 1 shows 3 transistors, which may in reality be any number N of transistors.

(7) In the event of an embodiment with NMOS FET transistors, the voltage difference formed in each transistor (3, 4 and 5), biased in weak inversion, is approximately the same and equals

(8) $V={\mathrm{nU}}_T\ln \left(\frac{{\mathrm{AI}}_{\mathrm{ph}}}{I_g}\right)$

(9) In this way, the voltage obtained in the highest transistor is approximately

(10) $V_N={\mathrm{NnU}}_T\ln \left(\frac{{\mathrm{AI}}_{\mathrm{ph}}}{I_g}\right)$

(11) In an embodiment of the integrated circuit, the parameters A, corresponding to the gain of the current mirror and I.sub.g corresponding to a parameter characteristic of the FET transistor, usually referred to as specific current, undergo great variation from pixel to pixel, whilst U.sub.T is an equal physical constant for all the pixels. The parameter n, corresponding to a further parameter characteristic of the FET transistor usually known as slope factor undergoes a relatively low variation from pixel to pixel. When the output voltage V.sub.N is taken to the derivative circuit, it provides the output

(12) $\frac{V_N}{t}={\mathrm{NnU}}_T\frac{I_{\mathrm{ph}}^{}}{I_{\mathrm{ph}}}$

(13) In such a way that this circuit adds the N factor (N being the number of transistors in each stage) to the gain obtained by means of previous techniques and the parameters which undergo great mismatch from pixel to pixel A and I.sub.g do not intervene.

(14) In practice it is not possible to use very high N values, being limited to 3 or 4. However, it is possible to connect different stages in cascade, like those shown in FIG. 1. This is shown in FIG. 2, where the first stage has N.sub.1 in-series transistors and the second stage has N.sub.2.

(15) The voltage formed in the first block V.sub.N1 (3) is carried to the gate of a transistor (11) with the source connected to V.sub.Q, generating a current

(16) $I_2=I_{s2}{}^{\frac{V_{N2}-{\mathrm{nV}}_Q}{{\mathrm{nU}}_T}}$
Upon deriving the output from the circuit V.sub.N1, the following approximate result is obtained:

(17) $\frac{V_{N2}}{t}=N_1{N}_2{\mathrm{nU}}_T\frac{I_{\mathrm{ph}}^{}}{I_{\mathrm{ph}}}$

(18) Once again, the parameters of high mismatch index between pixels do not appear in the final equation. This method makes it possible to expand to more successive stages.

(19) FIG. 3 shows an exemplary embodiment with two stages, each one contributing an additional gain 3. It shows a possible embodiment of the current mirrors. In order to achieve the additional gain, 3 FET transistors (3, 4 and 5) have been employed in cascade in each one of the steps. A FET transistor (11) is positioned at the input of the second stage with the source connected to a voltage V.sub.Q in order to generate the current I.sub.2.

(20) The current mirrors are basic circuits well known in literature on analog integrated circuit design. These copy the current in its input branch to the output branch, giving to the output branch an optional amplification or attenuation. In FIG. 3, the current mirror of the first stage is formed by three elements, two PMOS FET transistors (6, 7) being with their gate connected to respective constant voltage V.sub.a and V.sub.b and a voltage amplifier (8) with a gain which is high enough to generate the virtual ground conditions in the node that joins the photodiode (1) to the first PMOS transistor (6), thus improving the velocity of the circuit noticeably. The current mirror of the second stage (8, 9 and 10) is identical to that of the first stage, although it may be biased with different voltages V.sub.c and V.sub.d, which would give rise to a different gain.

(21) These circuits, which are repeated for each pixel, should be complemented by a number of biasing circuits, shared between all the pixels, in order to fix the voltages V.sub.a, V.sub.b, V.sub.c, V.sub.d and V.sub.Q.

(22) In the specific case of using DVS cameras, at least one photodiode is required to capture light in each pixel. Therefore, in each pixel of the DVS camera, there would be a transimpedance stage (or stages in cascade).

(23) If the stage is used in a context other than that of the DVS cameras, the input current may come from another circuit which is not a photodiode. In fact, for example, when several of these stages are used in cascade, only the first receives the current from the diode. The rest receive it from a transistor.