Insulation detection circuit and detection method thereof for two-way on-board charger

Abstract

The present invention discloses an insulation detection circuit and a detection method thereof for a two-way on-board charger. The detection circuit comprises an inverter circuit, a first Y capacitor connected between an output live line and a ground line of the inverter circuit, a second Y capacitor connected between an output neutral line and the ground line of the inverter circuit, a live line sampling circuit and a neutral line sampling circuit which are connected with the output live line and the output neutral line of the inverter circuit, and a controller. The controller determines an insulation state of the two-way on-board charger according to two sampling voltages.

Claims

1. An insulation detection circuit for a two-way on-board charger, comprising: an inverter circuit, a first Y capacitor connected between an output live line and a ground line of the inverter circuit, and a second Y capacitor connected between an output neutral line and the ground line of the inverter circuit, a live line sampling circuit and a neutral line sampling circuit correspondingly connected with the output live line and the output neutral line of the inverter circuit, and a controller connected with the live line sampling circuit and the neutral line sampling circuit, wherein the controller determines an insulation state of the two-way on-board charger according to sampling voltages respectively output by the two sampling circuits, wherein a summing circuit is provided among the controller, the live line sampling circuit and the neutral line sampling circuit and configured to perform summing processing on the two sampling voltages and output a summed voltage; and the controller determines an insulation state of the two-way on-board charger according to the summed voltage, wherein the live line sampling circuit and the neutral line sampling circuit have the same circuit structure, and each of the live line sampling circuit and the neutral line sampling circuit comprises: a voltage dividing circuit, a bias power source, a bias circuit, and an impedance matching circuit, wherein: the voltage dividing circuit is connected with the output live line or the output neutral line, and configured to proportionally reduce voltages to output a divided voltage; the bias circuit is connected between an output terminal of the voltage dividing circuit and the bias power source and configured to bias the divided voltage; and the impedance matching circuit is connected with the output terminal of the voltage dividing circuit, and configured to perform impedance matching and output one of the sampling voltages.

2. The insulation detection circuit according to claim 1, wherein the voltage dividing circuit in the live line sampling circuit comprises a first resistor R1 and a sixth resistor R6 which are connected in series between the output live line and the ground line, and a connection end of the first resistor and the sixth resistor serves as the output terminal of the voltage dividing circuit; the voltage dividing circuit in the neutral line sampling circuit comprises a second resistor R2 and a fifth resistor R5 which are connected in series between the output neutral line and the ground line, and a connection end of the second resistor and the fifth resistor serves as the output terminal of the voltage dividing circuit.

3. The insulation detection circuit according to claim 1, wherein the bias circuit in the live line sampling circuit comprises a fourth resistor R4, wherein one end of the fourth resistor is connected with the bias power source, and the other end of the fourth resistor is connected with the connection end of the first resistor and the sixth resistor; the bias circuit in the neutral line sampling circuit comprises a third resistor R3, wherein one end of the third resistor is connected with the bias power source, and the other end of the third resistor is connected with the connection end of the second resistor and the fifth resistor.

4. The insulation detection circuit according to claim 1, wherein the impedance matching circuit uses an emitter follower or a voltage follower.

5. The insulation detection circuit according to claim 4, wherein the impedance matching circuit in the live line sampling circuit comprises a first operational amplifier, wherein a non-inverting input terminal of the first operational amplifier is connected with the connection end of the first resistor and the sixth resistor, and an output terminal of the first operational amplifier is connected with its inverting input terminal and outputs the sampling voltage; the impedance matching circuit in the neutral line sampling circuit comprises a second operational amplifier, wherein a non-inverting input terminal of the second operational amplifier is connected with the connection end of the second resistor and the fifth resistor, and an output terminal of the second operational amplifier is connected with its inverting input terminal and outputs the sampling voltage.

6. The insulation detection circuit according to claim 5, wherein the summing circuit comprises a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and an output terminal A; the seventh resistor is connected in series between the output terminal A and an output terminal of the first operational amplifier; an eighth resistor is connected in series between the output terminal A and an output terminal of the second operational amplifier; the ninth resistor is connected in series between the output terminal A and the ground line; and the output terminal A outputs the summed voltage.

7. A detection method for determining an insulation state of a two-way on-board charger using the insulation detection circuit according to claim 1, the detection method comprising: sampling voltages on the output live line and the output neutral line of the inverter circuit, respectively; and determining the insulation state of the two-way on-board charger by the controller according to the sampling voltages output by the two sampling circuits.

8. The detection method according to claim 7, wherein the detection method specifically comprises the following steps: reducing voltages on the output live line and on the output neutral line of the inverter circuit proportionally by using the voltage dividing circuit respectively to generate the divided voltage; performing bias processing on the divided voltage by using the bias circuit, performing impedance matching on the divided voltage subjected to bias processing, and outputting the sampling voltages; performing summing processing on the sampling voltage of the output live line and the sampling voltage of the output neutral line by using the summing circuit, and outputting the summed voltage; and determining the insulation state of the two-way on-board charger according to the summed voltage.

9. An insulation detection circuit for a two-way on-board charger, comprising: an inverter circuit; a first Y capacitor connected between an output live line and a ground line of the inverter circuit; a second Y capacitor connected between an output neutral line and the ground line of the inverter circuit; a live line sampling circuit and a neutral line sampling circuit correspondingly connected with the output live line and the output neutral line of the inverter circuit; and a controller connected with the live line sampling circuit and the neutral line sampling circuit, wherein the controller determines an insulation state of the two-way on-board charger according to sampling voltages respectively output by the two sampling circuits, wherein the live line sampling circuit and the neutral line sampling circuit have the same circuit structure, and each of the live line sampling circuit and the neutral line sampling circuit comprises: a voltage dividing circuit, a bias power source, a bias circuit, and an impedance matching circuit, wherein: the voltage dividing circuit is connected with the output live line or the output neutral line, and configured to proportionally reduce voltages to output a divided voltage; the bias circuit is connected between an output terminal of the voltage dividing circuit and the bias power source and configured to bias the divided voltage; and the impedance matching circuit is connected with the output terminal of the voltage dividing circuit, and configured to perform impedance matching and output one of the sampling voltages.

10. The insulation detection circuit according to claim 9, wherein the voltage dividing circuit in the live line sampling circuit comprises a first resistor R1 and a sixth resistor R6 which are connected in series between the output live line and the ground line, and a connection end of the first resistor and the sixth resistor serves as the output terminal of the voltage dividing circuit; the voltage dividing circuit in the neutral line sampling circuit comprises a second resistor R2 and a fifth resistor R5 which are connected in series between the output neutral line and the ground line, and a connection end of the second resistor and the fifth resistor serves as the output terminal of the voltage dividing circuit.

11. The insulation detection circuit according to claim 9, wherein the bias circuit in the live line sampling circuit comprises a fourth resistor R4, wherein one end of the fourth resistor is connected with the bias power source, and the other end of the fourth resistor is connected with the connection end of the first resistor and the sixth resistor; the bias circuit in the neutral line sampling circuit comprises a third resistor R3, wherein one end of the third resistor is connected with the bias power source, and the other end of the third resistor is connected with the connection end of the second resistor and the fifth resistor.

12. The insulation detection circuit according to claim 9, wherein the impedance matching circuit uses an emitter follower or a voltage follower.

13. The insulation detection circuit according to claim 12, wherein the impedance matching circuit in the live line sampling circuit comprises a first operational amplifier, wherein a non-inverting input terminal of the first operational amplifier is connected with the connection end of the first resistor and the sixth resistor, and an output terminal of the first operational amplifier is connected with its inverting input terminal and outputs the sampling voltage; the impedance matching circuit in the neutral line sampling circuit comprises a second operational amplifier, wherein a non-inverting input terminal of the second operational amplifier is connected with the connection end of the second resistor and the fifth resistor, and an output terminal of the second operational amplifier is connected with its inverting input terminal and outputs the sampling voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a principle block diagram of a preferred embodiment of the present invention;

(2) FIG. 2 is a circuit diagram without a summing circuit;

(3) FIG. 3 is a circuit diagram with a summing circuit;

(4) FIG. 4 is a waveform diagram of a summed voltage when the insulation is normal;

(5) FIG. 5 is a waveform diagram of a summed voltage when the insulation fails;

(6) FIG. 6 is a waveform diagram of a voltage at each point when the insulation is normal; and

(7) FIG. 7 is a waveform diagram of a voltage at each point when the insulation fails.

DETAILED DESCRIPTION

(8) In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

(9) When the on-board charger operates in an inverting state, due to the requirements of a forward on-board charger (OBC) on the electromagnetic interference (EMI), there is a Y capacitor on each of the output line line L and the output neutral line N on an AC output port to the ground line during the inversion, and Y capacitance values of the output live line and the output neutral line to the ground are equal. In the presence of the Y capacitors, the output live line L and the output neutral line N generate a voltage to the ground, respectively, and the phases of the two voltages are staggered by 180 degrees. The amplitudes of the voltages are related to a ratio of the capacitance values of the output live line L and the output neutral line N of the capacitor. When the insulation of the output live line L or the output neutral line N to the ground fails, the voltage of the output live line L or the output neutral line N to the ground will lose balance.

(10) The present invention discloses an insulation detection circuit and a detection method thereof for a two-way on-board charger. According to this method, in an inversion mode, the insulation impedances of the output live line L and the output neutral line N to the ground are obtained by detecting the voltages of the output live line L and the output neutral line N to the ground. Whether there is an insulation failure between AC output and the vehicle body when the on-board charger operates in a pure inversion mode is detected by using the insulation impedance, thereby eliminating the hidden danger of electric shock to personnel.

(11) The insulation detection circuit for the two-way on-board charger disclosed by the present invention comprises an inverter circuit, a first Y capacitor C1 connected between an output live line and a ground line of the inverter circuit, a second Y capacitor C2 connected between an output neutral line and the ground line of the inverter circuit, a live line sampling circuit and a neutral line sampling circuit which are correspondingly connected with the output live line and the output neutral line of the inverter circuit, and a controller connected with the live line sampling circuit and the neutral line sampling circuit. The live line sampling circuit and the neutral line sampling circuit output a sampling voltage, respectively. The controller determines an insulation state of the two-way on-board charger according to the two sampling voltages.

(12) FIG. 1 is a principle block diagram of a preferred embodiment. A summing circuit is provided among the controller, the live line sampling circuit and the neutral line sampling circuit. The summing circuit is configured to perform summing processing on the two sampling voltages to obtain the summed voltage, and transmit the summed voltage to the controller. The controller determines an insulation state of the two-way on-board charger according to the summed voltage. It should be noted that the summing processing can be calculated inside the controller, and a circuit diagram of its embodiment is shown in FIG. 2. The summing processing may also be performed outside the controller. After the processing is completed, the summed voltage is transmitted to the controller, and a circuit diagram of its embodiment is shown in FIG. 3.

(13) In the above embodiments, the live line sampling circuit and the neutral line sampling circuit have the same circuit structure, and each comprises a voltage dividing circuit, a bias power source, a negative bias circuit, and an impedance matching circuit. The voltage dividing circuit is connected with the output live line or the output neutral line, and configured to proportionally reduce voltages and output a divided voltage; The negative bias circuit is connected between an output terminal of the voltage dividing circuit and the bias power source and configured to bias the divided voltage. The impedance matching circuit is connected with the output terminal of the voltage dividing circuit, and configured to perform impedance matching and output a sampling voltage. It should be noted that the impedance matching circuit can match the impedances of an input terminal and an output terminal, so that the input impedance is high and the output impedance is low, thereby enhancing the load capacity.

(14) Referring to the embodiments shown in FIG. 2 and FIG. 3, the voltage dividing circuit in the live line sampling circuit comprises a first resistor R1 and a sixth resistor R6 which are connected in series between the output live line and the ground line, and a connecting end G of the first resistor and the sixth resistor serves as the output terminal of the voltage dividing circuit. The voltage dividing circuit in the neutral line sampling circuit comprises a second resistor R2 and a fifth resistor R5 which are connected in series between the output neutral line and the ground line, and a connection end B of the second resistor and the fifth resistor serves as the output terminal of the voltage dividing circuit. A voltage division ratio is determined by a ratio of values of the first resistor R1 to the sixth resistor R6, and a ratio of values of the second resistor R2 to the fifth resistor R5. In this embodiment, R1=R2, R5=R6.

(15) The negative bias circuit in the live line sampling circuit comprises a fourth resistor R4, wherein one end of the fourth resistor is connected with the bias power source, and the other end of the fourth resistor is connected with the connection end C of the first resistor and the sixth resistor. The negative bias circuit in the neutral line sampling circuit comprises a third resistor R3, wherein one end of the third resistor is connected with the bias power source, and the other end of the third resistor is connected with the connection end B of the second resistor and the fifth resistor. In this embodiment, R3=R4.

(16) In this embodiment, the impedance matching circuit uses an emitter follower or a voltage follower.

(17) The impedance matching circuit in the live line sampling circuit comprises a first operational amplifier oab1. A non-inverting input terminal of the first operational amplifier is connected with the connection end C of the first resistor and the sixth resistor. An output terminal of the first operational amplifier is connected with its inverting input terminal and outputs the sampling voltage. The impedance matching circuit in the neutral line sampling circuit comprises a second operational amplifier oab2. A non-inverting input terminal of the second operational amplifier is connected with the connection end B of the second resistor and the fifth resistor. An output terminal of the second operational amplifier is connected with its inverting input terminal and outputs the sampling voltage.

(18) In this embodiment as shown in FIG. 3, the summing circuit comprises a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and an output terminal A. The seventh resistor R7 is connected in series between the output terminal A and the output terminal of the first operational amplifier. The eighth resistor R8 is connected in series between the output terminal A and the output terminal of the second operational amplifier. The ninth resistor R9 is connected in series between the output terminal A and the ground line. The output terminal A outputs the summed voltage to the controller.

(19) The working principle of the present invention is described in detail below with reference to FIG. 3. There are Y capacitors for the output live line L and the output neutral line N of the converter circuit of the charger, that is, the first Y capacitor C1 and the second Y capacitor C2, where C1=C2. The Y capacitors causes the output live line L and the output neutral line N to generate voltages VL and VN to the ground, respectively. In addition, phases of these two voltages differ by 180 degrees. The amplitudes of these two voltages are related to the ratio of the Y capacitors, in which:

(20) $\begin{array}{cc}\mathrm{VL}=\mathrm{Vac}.Math.\sqrt{2}.Math.\sin \left(2.Math.\pi .Math.f.Math.t+\pi \right].Math.\frac{C1}{C1+C2}& \left(\mathrm{Formula}1\right)\\ \mathrm{VN}=\mathrm{Vac}.Math.\sqrt{2}.Math.\sin \left(2.Math.\pi .Math.f.Math.t\right).Math.\frac{C2}{C1+C2}& \left(\mathrm{Formula}2\right)\end{array}$

(21) In the formulas, f is the frequency of an AC voltage, and t is a time.

(22) The resistors R2 and R5 are connected between the output neutral line N and the ground line. The voltage on the output neutral line N is proportionally reduced. A voltage VB1 is formed at a point B of the connection end of R2 and R5. A resistor R3 is added between the bias power source v_pwl1 and the point B, and v_pwl1 and R3 and R5 form a DC bias voltage VB2 to a point C. The voltage VB at the point B is a sum of VB1 and VB2.

(23) In which,
VB1=VN*R5/(R2+R5)  (Formula 3)
VB2=v_pwl1*R5/(R3+R5)  (Formula 4)
VB=VB1+VB2  (Formula 5)

(24) The resistors R1 and R6 are connected between the output live line L and the ground line. The voltage on the output live line L is proportionally reduced. A voltage VC1 is formed at the point C of the connection end of R1 and R6. A resistor R4 is added between the bias power source v_pwl1 and the point C, and v_pwl1 and R5 and R6 form a DC bias voltage VC2 to the point C. The voltage VC at the point C is a sum of VC1 and VC2.
VC1=VL*R6/(R1+R6)  (Formula 6)
VC2=v_pwl1*R6/(R4+R6)  (Formula 7)
VC=VC1+VC2  (Formula 8)
After the voltage at the point C passes through the impedance matching circuit, the voltage VD at a point D of an output terminal D of the first operational amplifier is equal to VC. In the same way, after the voltage at the point B passes through the impedance matching circuit, the voltage VE at a point E of an output terminal E of the second operational amplifier is equal to VB. The voltages at the points D and E are added to the point A via the resistors R7 and R8. The voltage at the point A is:

(25) $\begin{array}{cc}VA=\mathrm{VD}+\mathrm{VE}VA\mathrm{is}\mathrm{obtained}\mathrm{in}\mathrm{combination}\mathrm{with}\mathrm{Formulas}1\mathrm{to}9.& \left(\mathrm{Formula}9\right)\\ VA=\frac{\begin{array}{c}\left(\mathrm{Vac}.Math.\sqrt{2}.Math.\sin \left(2.Math.\pi f.Math.t\right)\right).Math.\\ \left[\frac{-C1}{C1+C2}.Math.R5.Math.\left(R1+R6\right)+\frac{C2}{C1+C2}.Math.R6.Math.\left(R2+R5\right)\right]\end{array}}{\left(R2+R5\right).Math.\left(R1+R6\right)}+\mathrm{V\_PWL1}.Math.\frac{R6}{R4+R6}+\mathrm{V\_PWL1}.Math.\left(\frac{R5}{R3+R5}\right)& \left(\mathrm{Formula}10\right)\end{array}$

(26) The voltage at the point Ain FIG. 3 is sent to an AD sampling port of the controller MCU. In a normal state, the impedances of the output live line L and the output neutral line N to the ground are infinite, that is, pwlr1 is infinite in FIG. 3. In addition, the value of the Y capacitor C1 of the output live line L to the ground is equal to the value of the Y capacitor C2 of the output neutral line N to the ground. In a normal insulation state, a divided voltage VB1 of the output live line L to the ground line and a divided voltage VC1 of the output neutral line N to the ground line add up to zero, which is as shown in the following formula;

(27) $\mathrm{VB}1+\mathrm{VC}1=\frac{\begin{array}{c}\left(\mathrm{Vac}.Math.\sqrt{2}.Math.\sin \left(2.Math.\pi f.Math.t\right)\right).Math.\\ \left[\frac{-C1}{C1+C2}.Math.R5.Math.\left(R1+R6\right)+\frac{C2}{C1+C2}.Math.R6.Math.\left(R2+R5\right)\right]\end{array}}{\left(R2+R5\right).Math.\left(R1+R6\right)}$

(28) A sum of the voltages at the point A is equal to a sum of negative bias voltages. That is, in the normal insulation state,

(29) $VA=\mathrm{V\_PWL1}.Math.\frac{R6}{R4+R6}+\mathrm{V\_PWL1}.Math.\left(\frac{R5}{R3+R5}\right)$

(30) The controller MCU reads a voltage value at the point A through AD sampling. The voltage value at the point A is equal to a sum of negative bias voltage values of the output live line L and the output neutral line N (the voltage at the point A is shown in FIG. 4). The summed voltage remains constant in amplitude, and the graph shows a straight line. In this case, the controller MCU determines whether the output live line L and the output neutral line N are normally insulated. In the normal state, the insulation resistance pwlr1 is considered to be infinite, and the insulation resistance pwlr1 is ignored in the above formula. FIG. 6 shows voltage waveforms at various points when the insulation is normal. VL is a voltage of the output live line L to the ground, VN is a voltage of the output neutral line N to the ground, VA0 is a voltage at an output terminal of R7, and VA1 is a voltage at an output terminal of R8.

(31) When the output live line L or the output neutral line N has an insulation failure to the ground line, the impedance of the output live line L or the output neutral line N to the ground line is decreasing. That is, PWLr1 in FIG. 2 or FIG. 3 decreases from infinity, and the impedance of the output live line L to the ground will decrease. In this case, the voltage of VL to the ground line and the voltage of VN to the ground line will lose balance, and the sum of VN and VL is no longer equal to zero. According to the actual measurement shown in FIG. 5, the amplitude of the summed voltage shows a sine wave waveform. The controller MCU will determine that the insulation fails according to the voltage value obtained by AD sampling, and meanwhile determine the amplitude of the value of the insulation resistance. FIG. 7 shows voltage waveforms at various points when the insulation fails. VL is a voltage of the output live line L to the ground, VN is a voltage of the output neutral line N to the ground, VA0 is a voltage at the output terminal of R7, and VA1 is a voltage at the output terminal of R8.

(32) In an embodiment as shown in FIG. 2, the controller MCU uses two different AD sampling ports to input samplings of VL and VN to the MCU, and performs summing processing.

(33) The present invention further discloses a detection method for an insulation detection circuit for a two-way on-board charger. The detection circuit comprises an inverter circuit, a first Y capacitor C1 connected between an output live line and a ground line of the inverter circuit, and a second Y capacitor C2 connected between an output neutral line and the ground line of the inverter circuit. The detection method comprises the following steps: sampling voltages on the output live line and the output neutral line of the inverter circuit, respectively; and determining an insulation state of the two-way on-board charger according to the two sampling voltages.

(34) In a preferred embodiment, the detection method comprises the following steps: reducing voltages on the output live line and on the output neutral line of the inverter circuit proportionally by using a voltage dividing circuit respectively to generate a divided voltage; performing bias processing on the divided voltage by using a negative bias circuit, performing impedance matching on the divided voltage subjected to bias processing, and outputting a sampling voltage; performing summing processing on the sampling voltage of the output live line and the sampling voltage of the output neutral line by using a summing circuit to obtain a summed voltage; and determining an insulation state of the two-way on-board charger according to the summed voltage.

(35) The above embodiments are merely examples, and are not limitative. Any equivalent modifications or changes made without departing from the spirit and scope of the present application shall be included in the scope of claims of the present application.