Inroute burst header in a VSAT system

Abstract

A satellite terminal and a machine-implemented method are provided for encoding a burst header of a burst for transmission on an inroute. One component of a group of satellite terminal components consisting of an ASIC, a FPGA, and a DSP, generates a burst header having five information bits encoded therein. The five information bits may be encoded using a Reed-Muller code, a (32, 5) block code or a convolutional code having a code rate of either 1/5 or 1/10. The five information bits may represent one or more of a modulation type for a payload of the burst, a code rate for encoding the payload, a code type, and a spreading factor for spreading the payload during transmission. A satellite gateway and a machine-implemented method are also provided for decoding a burst header of a burst received on an inroute as described above.

Claims

1. A machine-implemented method for encoding a burst header of a burst to be transmitted on an inroute from a satellite terminal, the machine-implemented method comprising: generating, by an application specific integrated circuit of a satellite terminal, a burst header, the burst header having encoded therein, via a convolutional code having a code rate of either 1/5 or 1/10, a plurality of information bits representing a modulation type for modulating a payload of the burst and a code rate for the payload, a number of the plurality of information bits being five; providing the burst, including the burst header and the payload to a modulator; modulating the burst header via a binary phase shift keying modulation; modulating the payload data via a modulation matching the modulation type encoded within the burst header; and transmitting the modulated burst header and the modulated payload data, the modulated payload data having a first code rate matching the code rate encoded within the burst header, wherein either: the generating the burst header comprises: encoding the plurality of information bits of the burst header using the convolution code to produce a 50 bit codeword, wherein a plurality of generator polynomials for producing the 50 bit codeword comprise: g0=(1 1 1 1 1), g1=(1 0 1 1 1), g2=(1 1 0 0 1), g3=(1 1 0 1 1), g4=(1 1 1 0 1), g5=(1 1 0 1 1), g6=(1 0 1 1 1), g7=(1 0 1 0 1), g8=(1 0 0 1 1), and g9=(1 0 0 0 1), wherein: gi=(g.sub.i,0 g.sub.i,1 g.sub.i,2 g.sub.i,3 g.sub.i,4 g.sub.i,5), and i is an integer, and 0<i<9; or the generating the burst header comprises: encoding the plurality of information bits of the burst header using the convolutional code having the code rate of 1/5 to produce a 25 bit codeword which is repeated once, thereby producing 50 bits included in the encoded burst header, wherein a plurality of generator polynomials for producing the 25 bit codeword comprises: g0=(1 0 1 0 1), g1=(1 0 1 1 1), g2=(1 1 0 1 1), g3=(1 1 1 1 1), and g4=(1 1 0 0 1), wherein: gi=(g.sub.i,0 g.sub.i,1 g.sub.i,2 g.sub.i,3 g.sub.i,4), and i is an integer, and 0<i<4.

2. The machine-implemented method of claim 1, wherein: the plurality of information bits further represent a spreading factor for the payload, and the modulated payload data is transmitted using a first spreading factor matching the spreading factor represented by the plurality of information bits.

3. The machine-implemented method of claim 1, wherein: the plurality of information bits further represent a code type for encoding the payload, and the machine-implemented method further comprises encoding the payload data via a first code type matching the code type represented by the plurality of information bits.

4. The machine-implemented method of claim 1, wherein the modulating the burst header via a binary phase shift keying modulation comprises: modulating the burst header via a $\frac{}{2}$ shifted binary phase shift keying modulation.

5. The machine-implemented method of claim 1, wherein: the convolutional code and the plurality of generator polynomials for producing the 50 bit codeword are used to encode the plurality of information bits to produce the 50 bit codeword, and tail bits are not transmitted.

6. The machine-implemented method of claim 5, wherein: the 50 bit codeword includes 50 coded bits, p.sub.0 through p.sub.49, the p.sub.0=((((u.sub.0 xor u.sub.4) xor u.sub.3) xor u.sub.2) xor u.sub.1), p.sub.1=(((u.sub.0 xor u.sub.3) xor u.sub.2) xor u.sub.1), p.sub.2=((u.sub.0 xor u.sub.4) xor u.sub.1), p.sub.3=(((u.sub.0 xor u.sub.4) xor u.sub.2) xor u.sub.1), p.sub.4=(((u.sub.0 xor u.sub.4) xor u.sub.3) xor u.sub.1), p.sub.5=(((u.sub.0 xor u.sub.4) xor u.sub.2) xor u.sub.1), p.sub.6=(((u.sub.0 xor u.sub.3) xor u.sub.2) xor u.sub.1), p.sub.7=((u.sub.0 xor u.sub.2) xor u.sub.1), p.sub.8=((u.sub.0 xor u.sub.2) xor u.sub.1), p.sub.9=(u.sub.0 xor u.sub.1), p.sub.10=((((u.sub.1 xor u.sub.0) xor u.sub.4) xor u.sub.3) xor u.sub.2), p.sub.11=(((u.sub.1 xor u.sub.4) xor u.sub.3) xor u.sub.2), p.sub.12=((u.sub.1 xor u.sub.0) xor u.sub.2), p.sub.13=(((u.sub.1 xor u.sub.0) xor u.sub.3) xor u.sub.2), p.sub.14=(((u.sub.1 xor u.sub.0) xor u.sub.4) xor u.sub.2), p.sub.15=(((u.sub.1 xor u.sub.0) xor u.sub.3) xor u.sub.2), p.sub.16=(((u.sub.1 xor u.sub.4) xor u.sub.3) xor u.sub.2), p.sub.17=((u.sub.1 xor u.sub.4) xor u.sub.2), p.sub.18=((u.sub.1 xor u.sub.3) xor u.sub.2), p.sub.19=(u.sub.1 xor u.sub.2), p.sub.20=((((u.sub.2 xor u.sub.1) xor u.sub.0) xor u.sub.4) xor u.sub.3), p.sub.21=(((u.sub.2 xor u.sub.0) xor u.sub.4) xor u.sub.3), p.sub.22=((u.sub.2 xor u.sub.1) xor u.sub.3), p.sub.23=(((u.sub.2 xor u.sub.1) xor u.sub.4) xor u.sub.3), p.sub.24=(((u.sub.2 xor u.sub.1) xor u.sub.0) xor u.sub.3), p.sub.25=(((u.sub.2 xor u.sub.1) xor u.sub.4) xor u.sub.3), p.sub.26=(((u.sub.2 xor u.sub.0) xor u.sub.4) xor u.sub.3), p.sub.27=((u.sub.2 xor u.sub.0) xor u.sub.3), p.sub.28=((u.sub.2 xor u.sub.4) xor u.sub.3), p.sub.29=(u.sub.2 xor u.sub.3), p.sub.30=((((u.sub.3 xor u.sub.2) xor u.sub.1) xor u.sub.0) xor u.sub.4), p.sub.31=(((u.sub.3 xor u.sub.1) xor u.sub.0) xor u.sub.4), p.sub.32=((u.sub.3 xor u.sub.2) xor u.sub.4), p.sub.33=(((u.sub.3 xor u.sub.2) xor u.sub.0) xor u.sub.4), p.sub.34=(((u.sub.3 xor u.sub.2) xor u.sub.1) xor u.sub.4), p.sub.35=(((u.sub.3 xor u.sub.2) xor u.sub.0) xor u.sub.4), p.sub.36=(((u.sub.3 xor u.sub.1) xor u.sub.0) xor u.sub.4), p.sub.37=((u.sub.3 xor u.sub.1) xor u.sub.4), p.sub.38=((u.sub.3 xor u.sub.1) xor u.sub.4), p.sub.39=(u.sub.3 xor u.sub.4), p.sub.40=((((u.sub.4 xor u.sub.3) xor u.sub.2) xor u.sub.1) xor u.sub.0), p.sub.41=(((u.sub.4 xor u.sub.2) xor u.sub.1) xor u.sub.0), p.sub.42=((u.sub.4 xor u.sub.3) xor u.sub.0), p.sub.43=(((u.sub.4 xor u.sub.3) xor u.sub.1) xor u.sub.0), p.sub.44=(((u.sub.4 xor u.sub.3) xor u.sub.2) xor u.sub.0), p.sub.45=(((u.sub.4 xor u.sub.3) xor u.sub.1) xor u.sub.0), p.sub.46=(((u.sub.4 xor u.sub.2) xor u.sub.1) xor u.sub.0), p.sub.47=((u.sub.4 xor u.sub.2) xor u.sub.0), p.sub.48=((u.sub.4 xor u.sub.1) xor u.sub.0), and the p.sub.49=(u.sub.4 xor u.sub.0), wherein: the u.sub.0, the u.sub.1, the u.sub.2, the u.sub.3, and the u.sub.4 are the plurality of information bits.

7. The machine-implemented method of claim 1, further comprising: mapping bits of the encoded plurality of information bits of the burst header to respective symbols according to a desired modulation type for the payload, the desired modulation type being a modulation type selected from a group consisting of an offset quadrature phase shift keying modulation type, an 8 phase shift keying modulation type, and a 16 amplitude and phase shift keying modulation type, wherein as a result of the mapping bits, an effective modulation type for the burst header is a $\frac{}{2}$ shifted binary phase shift keying modulation type.

8. The machine-implemented method of claim 1, wherein: the plurality of information bits are encoded, using the plurality of generator polynomials for producing the 25 bit codeword, to produce the 25 bit codeword, and the 25 bit codeword includes 25 coded bits, p.sub.0 through p.sub.24, the p.sub.0=((u.sub.0 xor u.sub.3) xor u.sub.1), p.sub.1=(((u.sub.0 xor u.sub.3) xor u.sub.2) xor u.sub.1), p.sub.2=(((u.sub.0 xor u.sub.4) xor u.sub.2) xor u.sub.1), p.sub.3=((((u.sub.0 xor u.sub.4) xor u.sub.3) xor u.sub.2) xor u.sub.1), p.sub.4=((u.sub.0 xor u.sub.4) xor u.sub.1), p.sub.5=((u.sub.1 xor u.sub.4) xor u.sub.2), p.sub.6=(((u.sub.1 xor u.sub.4) xor u.sub.3) xor u.sub.2), p.sub.7=(((u.sub.1 xor u.sub.0) xor u.sub.3) xor u.sub.2), p.sub.8=((((u.sub.1 xor u.sub.0) xor u.sub.4) xor u.sub.3) xor u.sub.2), p.sub.9=((u.sub.1 xor u.sub.0) xor u.sub.2), p.sub.10=((u.sub.2 xor u.sub.0) xor u.sub.3), p.sub.11=(((u.sub.2 xor u.sub.0) xor u.sub.4) xor u.sub.1), p.sub.12=(((u.sub.2 xor u.sub.1) xor u.sub.4) xor u.sub.3), p.sub.13=((((u.sub.2 xor u.sub.1) xor u.sub.0) xor u.sub.4) xor u.sub.3), p.sub.14=((u.sub.2 xor u.sub.1) xor u.sub.3), p.sub.15=((u.sub.3 xor u.sub.1) xor u.sub.4), p.sub.16=(((u.sub.3 xor u.sub.1) xor u.sub.0) xor u.sub.2), p.sub.17=(((u.sub.3 xor u.sub.2) xor u.sub.0) xor u.sub.4), p.sub.18=((((u.sub.3 xor u.sub.2) xor u.sub.1) xor u.sub.0) xor u.sub.4), p.sub.19=((u.sub.3 xor u.sub.2) xor u.sub.4), p.sub.20=((u.sub.4 xor u.sub.2) xor u.sub.0), p.sub.21=(((u.sub.4 xor u.sub.2) xor u.sub.1) xor u.sub.3), p.sub.22=(((u.sub.4 xor u.sub.3) xor u.sub.1) xor u.sub.0), p.sub.23=((((u.sub.4 xor u.sub.1) xor u.sub.2) xor u.sub.1) xor u.sub.0), and the p.sub.24=((u.sub.4 xor u.sub.3) xor u.sub.0)), wherein: the u.sub.0, the u.sub.1, the u.sub.2, the u.sub.3, and the u.sub.4 are the plurality of information bits.

9. A machine-implemented method for decoding a burst header of a burst, the machine-implemented method comprising: receiving, by a satellite gateway, the burst including the burst header and encoded payload data; demodulating, by the satellite gateway, the burst header having been modulated using a predefined phase shift keying modulation type; decoding the burst header by the satellite gateway, the burst header having a plurality of information bits encoded therein via a convolutional code having a code rate of either 1/5 or 1/10, the plurality of information bits being 5 bits representing, with respect to the payload data, a modulation type and a first code rate, the decoding the burst header further comprising: combining two sets of 25 bits of the burst header into one set of 25 bits, and decoding the one set of 25 bits of the burst header, encoded using the convolutional code, to produce the plurality of information bits; and demodulating the encoded payload data modulated using the modulation type, the encoded payload data having been encoded at the first code rate.

10. The machine-implemented method of claim 9, wherein the plurality of information bits further represents a spreading factor by which the payload is transmitted.

11. The machine-implemented method of claim 9, wherein the plurality of information bits further represent a code type used to encode the payload data.

12. The machine-implemented method of claim 9, further comprising: decoding the encoded payload data according to an encoding method having the first code rate represented by the plurality of information bits encoded in the burst header.

Description

DRAWINGS

(1) In order to describe the manner in which the above-recited and other advantages and features can be obtained, a more particular description is provided below and will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments and are not therefore to be considered to be limiting of its scope, implementations will be described and explained with additional specificity and detail through the use of the accompanying drawings.

(2) FIG. 1 illustrates an exemplary operating environment for various embodiments.

(3) FIG. 2 illustrates a layout of an exemplary burst.

(4) FIG. 3 illustrates functional block diagram of a portion of an exemplary satellite terminal.

(5) FIG. 4 shows an exemplary table which maps a value of information bits encoded within a burst header to a modulation type, a code rate and a spreading factor.

(6) FIG. 5 shows an exemplary structure of an encoder for encoding five information bits according to a (50, 5) convolutional code.

(7) FIG. 6 illustrates a table for mapping coded bits to symbols for a desired modulation type such that a modulation effectively becomes a binary phase shift keying modulation.

(8) FIGS. 7-9 illustrate bit to symbol mapping for OQPSK, 8PSK and 16APSK burst header modulation types, respectively.

(9) FIG. 10 shows a functional block diagram of a portion of an exemplary satellite gateway.

DETAILED DESCRIPTION

(10) Embodiments are discussed in detail below. While specific implementations are discussed, it should be understood that this is done for illustration purposes only. A person skilled in the relevant art will recognize that other components and configurations may be used without parting from the spirit and scope of the subject matter of this disclosure.

Overview

(11) A satellite terminal and a machine-implemented method are provided for encoding a burst header of a burst for transmission on an inroute from a satellite terminal to a satellite gateway. In various embodiments, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a digital signal processor (DSP) of a satellite terminal generates a burst header for a burst. Five information bits may be encoded within the burst header using a (16, 5) Reed-Muller code, a (32, 5) block code or a convolutional code having a code rate of either 1/5 or 1/10. The five information bits may represent a modulation type for a payload of the burst and a code rate for encoding the payload. In some embodiments, the five information bits may further represent a spreading factor for spreading the payload during transmission and a code type for encoding the payload. In some embodiments, the burst header may be modulated via a binary phase shift keying modulation.

(12) In various embodiments, when the five information bits are encoded using the (16, 5) Reed-Muller code, the resulting 16 bit codeword may be repeated to produce 32 bits for the burst header. In other embodiments, when the five information bits are encoded using a convolutional code, the code rate may be either 1/5 or 1/10. Thus, when the code rate is 1/10, encoding the five information bits produces a 50 bit codeword for the burst header. When the code rate is 1/5, encoding the five information bits produces a 25 bit codeword, which may be repeated to produce 50 bits for the burst header.

(13) Embodiments may include a satellite gateway and a machine-implemented method for decoding a burst header of a burst to produce five information bits representing a modulation type and a code rate for a payload of the burst. In some embodiments, the five information bits may further represent one or more of a spreading factor for spreading the payload during transmission and a code type used for encoding the payload.

Exemplary Operating Environment

(14) FIG. 1 illustrates an exemplary operating environment 100, in which various embodiments may operate. Exemplary operating environment 100 may include a satellite 104 in an orbit, a satellite gateway 106, and a satellite terminal 102. Satellite terminal 102 may be a very small aperture terminal (VSAT), which may transmit a burst on an inroute 108, 110 to satellite gateway 106 via satellite 104.

Exemplary Burst

(15) FIG. 2 illustrates an exemplary burst 200 consistent with various embodiments of the invention. Transmission of the burst 200 may begin with a radio portion of a transmitter turning on 202, transmission of a UW 204 for at least synchronization purposes, transmission of a burst header 206 that signals various physical attributes of a payload 208, transmission of payload 208, which includes a number of symbols, and turning off 210 of the radio portion of the transmitter.

Satellite Terminal

(16) FIG. 3 is a functional block diagram illustrating a portion of satellite terminal 102. Satellite terminal 102 may include an application specific integrated circuit (ASIC) 302, a modulator 304 and a transmitter 306. ASIC 302 may encode bits representing information according to a particular encoding scheme, which may include a Reed Muller code, a convolutional code, a (32, 5) block code or another type of encoding scheme. Modulator 304 may receive the encoded bits and may modulate the encoded bits via a type of modulation such as, for example, a binary phase shift keying (BPSK) modulation type, an offset quadrature phase shift keying (OQPSK) modulation type, an 8 phase shift keying (8PSK) modulation type, or a 16 amplitude and phase shift keying (16APSK) modulation type. Transmitter 306 transmits the modulated encoded bits as symbols according to the modulation type. In an alternate embodiment, ASIC 302 may be replaced with a FPGA or a DSP.

Burst Header Encoding

(17) In one embodiment, a (16, 5) Reed-Muller code may be used to encode five information bits u=[u.sub.4 u.sub.3 u.sub.2 u.sub.1 u.sub.0]. The following generator matrix, G, may be used to Reed-Muller encode the five information bits for a burst header.

(18) $G=\left[\begin{array}{cccccccccccccccc}0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1\\ 0& 0& 1& 1& 0& 0& 1& 1& 0& 0& 1& 1& 0& 0& 1& 1\\ 0& 0& 0& 0& 1& 1& 1& 1& 0& 0& 0& 0& 1& 1& 1& 1\\ 0& 0& 0& 0& 0& 0& 0& 0& 1& 1& 1& 1& 1& 1& 1& 1\\ 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1\end{array}\right]$

(19) Any 5 bit information vector u=[u.sub.4 u.sub.3 u.sub.2 u.sub.1 u.sub.0] may be encoded onto a 16 bit codeword, c, using c=u.Math.G. The 16 bit codeword may then be repeated once to produce 32 bits for the burst header. The burst header may be transmitted using a BPSK modulation. The BPSK modulation is very robust and works well at a low Es/No, where Es is symbol energy of the signal and No is noise. For example, when Es/No1 db, and a (16, 5) Reed-Muller code is used to encode five information bits onto a 16 bit codeword, which is repeated once and included as 32 bits of the burst header, the BPSK modulation is robust enough to work under these conditions. When only 16 bits of the codeword, with no repetition, is included in the burst header, the BPSK modulation is robust enough to work when Es2 db. In some embodiments, the BPSK modulation may be a

(20) $\frac{}{2}$
shifted BPSK modulation.

(21) In another embodiment a (32, 5) block code may be used to encode the five information bits onto a 32 bit codeword. Any 5 bit information vector u=[u.sub.4 u.sub.3 u.sub.2 u.sub.1 u.sub.0] may be encoded onto a 32 bit codeword, c, using c=u.Math.G, where G is given by the block code

(22) $\mathrm{generator}\mathrm{matrix}\mathrm{as}G=[\begin{array}{cccccccccccccccccccccccccccccccc}0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1& 0& 1\\ 0& 0& 1& 1& 0& 0& 1& 1& 0& 0& 1& 1& 0& 0& 1& 1& 0& 0& 1& 1& 0& 0& 1& 1& 0& 0& 1& 1& 0& 0& 1& 1\\ 0& 0& 0& 0& 1& 1& 1& 1& 0& 0& 0& 0& 1& 1& 1& 1& 0& 0& 0& 0& 1& 1& 1& 1& 0& 0& 0& 0& 1& 1& 1& 1\\ 0& 0& 0& 0& 0& 0& 0& 0& 1& 1& 1& 1& 1& 1& 1& 1& 0& 0& 0& 0& 0& 0& 0& 0& 1& 1& 1& 1& 1& 1& 1& 1\\ 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 0& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1\end{array}]$

(23) In a third embodiment, a convolutional code may be used to encode the five information bits onto a 50 bit codeword. In some implementations, a convolutional encoder may perform tail biting. In other words, tail bits are not transmitted. Alternatively, instead of encoding the five information bits onto a 50 bit codeword, a convolutional code may encode the five information bits onto a 25 bit codeword, which may be repeated and included as 50 bits of the burst header.

(24) FIG. 4 illustrates an exemplary table which maps a value of the information bits of a burst header to a modulation type, code rate, and spreading factor for a payload of a burst including the burst header. As shown in the table, the information bits having a value of 0 indicates that the payload is transmitted using OQPSK modulation, a code rate of 1/3, and a spreading factor of 0. The information bits having a value of 1 indicates that the payload is transmitted using the OQPSK modulation, a code rate of 1/2, and a spreading factor of 0. The information bits having a value of 2 indicates that the payload is transmitted using OQPSK modulation, a code rate of 2/3, and a spreading factor of 0. The information bits having a value of 3 indicates that the payload is transmitted using OQPSK modulation, a code rate of 4/5, and a spreading factor of 0. The information bits having a value of 4 indicates that the payload is transmitted using OQPSK modulation, a code rate of 9/10, and a spreading factor of 0. The information bits having a value of 5 indicates that the payload is transmitted using 8PSK modulation, a code rate of 1/2, and a spreading factor of 0. The information bits having a value of 6 indicates that the payload is transmitted using 8PSK modulation, a code rate of 2/3, and a spreading factor of 0. The information bits having a value of 7 indicates that the payload is transmitted using 8PSK modulation, a code rate of 4/5, and a spreading factor of 0. The information bits have a value of 8 indicates that the payload is transmitted using 8PSK modulation, a code rate of 8/9, and a spreading factor of 0. The information bits having a value of 9 indicates that the payload is transmitted using 16APSK modulation, a code rate of 1/2, and a spreading factor of 0. The information bits having a value of 10, the payload is transmitted using 16APSK modulation, a code rate of 2/3, and a spreading factor of 0. The information bits having a value of 11 indicates that the payload is transmitted using 16APSK modulation, a code rate of 4/5, and a spreading factor of 0. The information bits having a value of 12 indicates that the payload is transmitted using 16APSK modulation, a code rate of 8/9, and a spreading factor of 0. The information bits have a value of 13, the payload is transmitted using OQPSK modulation indicates that a code rate of 1/3, and a spreading factor of 8. The information bits having a value of 14 indicates that the payload is transmitted using OQPSK modulation, a code rate of 1/2, and a spreading factor of 8. The information bits having a value of 15 indicates that the payload is transmitted using OQPSK modulation, a code rate of 2/3, and a spreading factor of 8. The information bits having a value of 16 indicates that the payload is transmitted using OQPSK modulation, a code rate of 4/5, and a spreading factor of 8. The information bits having a value of 17 indicates that the payload is transmitted using OQPSK modulation, a code rate of 9/10, and a spreading factor of 8. The information bits having a value of 18 indicates that the payload is transmitted using 8PSK modulation, a code rate of 1/2, and a spreading factor of 8. The information bits having a value of 19 indicates that the payload is transmitted using 8PSK modulation, a code rate of 2/3, and a spreading factor of 8. The information bits having a value of 20 indicates that the payload is transmitted using 8PSK modulation, a code rate of 4/5, and a spreading factor of 8. The information bits having a value of 21 indicates that the payload is transmitted using 8PSK modulation, a code rate of 8/9, and a spreading factor of 8. The information bits have a value of 22 indicates that the payload is transmitted using 16APSK modulation, a code rate of 1/2, and a spreading factor of 8. The information bits having a value of 23 indicates that the payload is transmitted using 16APSK modulation, a code rate of 2/3, and a spreading factor of 8. The information bits have a value of 24 indicates that the payload is transmitted using 16APSK modulation, a code rate of 4/5, and a spreading factor of 8. The information bits having a value of 25 indicates that the payload is transmitted using 16APSK modulation, a code rate of 8/9, and a spreading factor of 8. The information bits have a value of 26 indicates that the payload is transmitted using OQPSK modulation, a code rate of 1/2, and a spreading factor of 16. The information bits having a value of 27 indicates that the payload is transmitted using OQPSK modulation, a code rate of 2/3, and a spreading factor of 16. The information bits having a value of 28 indicates that the payload is transmitted using OQPSK modulation, a code rate of 4/5, and a spreading factor of 16. The information bits having a value of 29 indicates that the payload is transmitted using OQPSK modulation, a code rate of 9/10, and a spreading factor of 16. Values of 30 and 31 for the information bits may be reserved for future use.

(25) Additional information may also be represented by the five information bits. For example, the five information bits may further represent a code type for encoding the payload, including, but not limited to, Turbo Coding and LDPC (low density parity check) coding. For example, with reference to FIG. 4, the information bits having a value of 1 indicates that the payload is transmitted using the OQPSK modulation, a code rate of 1/2, using Turbo Coding and spreading factor of 0. Whereas the information bits having a value of 2 indicates that the payload is transmitted using the OQPSK modulation, a code rate of 2/3, using LDPC coding and spreading factor of 0.

(26) FIG. 5 illustrates an exemplary convolutional encoder 500 having a code rate of 1/10 (each information bit is encoded into 10 encoded bits). Convolutional encoder 500 may include shift registers 502, 504, 506, 508 and a delay register 510. Each of shift registers 502, 504, 506, 508 and delay register 510 has a respective input and output. Assuming that the five information bits are u=[u.sub.4 u.sub.3 u.sub.2 u.sub.1 u.sub.0], an initial state of a convolutional encoder 500 may be as shown in FIG. 5. In the initial state, delay register 510 has bit u.sub.1 as an input and no output, shift register 508 has bit u.sub.1 as an output and bit u.sub.2 as an input, shift register 506 has bit u.sub.2 as an output and bit u.sub.3 as an input, shift register 504 has bit u.sub.3 as an output and bit u.sub.4 as an input, and shift register 502 has bit u.sub.4 as an output and bit u.sub.0 as an input. Each of g.sub.i,0, g.sub.i,1, g.sub.i,3, and g.sub.i,4 may have a value of 0 or 1. Each of (hereinafter, referred to as xor) 510, 512, 514, 516 indicates an exclusive-or operation with two inputs, such that each input is either a 0 or a 1.

(27) If a generator polynomial gi=(g.sub.i,0 g.sub.i,1 g.sub.i,2 g.sub.i,3 g.sub.i,4) and a generator polynomial g0=(1 1 1 1 1), then g.sub.0,0=1, g.sub.0,1=1, g.sub.0,2=1, g.sub.0,3=1 and g.sub.0,4=1. When a respective gi=1, then a respective u bit is input to a respective xor. Otherwise, a 0 is input to the respective xor. Therefore, initially, a first bit produced, p.sub.0, is ((((u.sub.0 xor u.sub.4) xor u.sub.3) xor u.sub.2) xor u.sub.1). When g.sub.1,0=1, g.sub.1,1=0, g.sub.1,2=1, g.sub.1,3=1, g.sub.1,4=1, then a second bit produced, p.sub.1, is (((u.sub.0 xor u.sub.3) xor u.sub.2) xor u.sub.1). When g.sub.2,0=1, g.sub.2,1=1, g.sub.2,2=0, g.sub.2,3=0 and g.sub.2,4=1, then a third produced bit, p.sub.2, is ((u.sub.0 xor u.sub.4) xor u.sub.1). When g.sub.3,0=1, g.sub.3,1=1, g.sub.3,2=0, g.sub.3,3=1 and g.sub.3,4=1, then a fourth bit, p.sub.3, is (((u.sub.0 xor u.sub.4) xor u.sub.2) xor u.sub.1). When g.sub.4,0=1, g.sub.1,1=1, g.sub.1,2=1, g.sub.1,3=1, g.sub.1,4=1, then a fifth bit produced, p.sub.4, is (((u.sub.0 xor u.sub.4) xor u.sub.3) xor u.sub.1). When g.sub.5,0=1, g.sub.5,1=1, g.sub.5,2=1, g.sub.5,3=1, g.sub.5,4=1, then a sixth bit produced, p.sub.5, is (((u.sub.0 xor u.sub.4) xor u.sub.2) xor u.sub.1). When g.sub.6,0=1, g.sub.6,1=1, g.sub.6,2=1, g.sub.6,3=1, g.sub.6,4=1, then a seventh bit produced, p.sub.6, is (((u.sub.0 xor u.sub.3) xor u.sub.2) xor u.sub.1). When g.sub.7,0=1, g.sub.7,1=0, g.sub.7,2=1, g.sub.7,3=0, g.sub.7,4=1, then an eighth bit produced, p.sub.7, is ((u.sub.0 xor u.sub.2) xor u.sub.1). When g.sub.8,0=1, g.sub.8,1=0, g.sub.8,2=0, g.sub.8,3=1, g.sub.8,4=1, then a ninth bit produced, p.sub.8, is ((u.sub.0 xor u.sub.2) xor u.sub.1). When g.sub.9,0=1, g.sub.9,1=0, g.sub.9,2=0, g.sub.9,3=0, g.sub.9,4=1, then a tenth bit produced, p.sub.9, is (u.sub.0 xor u.sub.1).

(28) After generating bits p.sub.0 through p.sub.9, the u bits are shifted to the right and delay register 510 has an output of u.sub.1 and an input of u.sub.2, shift register 508 has an output of u.sub.2 and an input of u.sub.3, shift register 506 has an output of u.sub.3 and an input of u.sub.4, shift register 504 has an output of u.sub.4 and an input of u.sub.0, and shift register 502 has an output of u.sub.0 and an input of u.sub.1. Using the values of g0 through g9, to produce the next 10 bits, one can see that p.sub.10 is ((((u.sub.1 xor u.sub.0) xor u.sub.4) xor u.sub.3) xor u.sub.2), p.sub.11, is (((u.sub.1 xor u.sub.4) xor u.sub.3) xor u.sub.2), p.sub.12 is ((u.sub.1 xor u.sub.0) xor u.sub.2), p.sub.13 is (((u.sub.1 xor u.sub.0) xor u.sub.3) xor u.sub.2), p.sub.14 is (((u.sub.1 xor u.sub.0) xor u.sub.4) xor u.sub.2), p.sub.15 is (((u.sub.1 xor u.sub.0) xor u.sub.3) xor u.sub.2), p.sub.16 is (((u.sub.1 xor u.sub.4) xor u.sub.3) xor u.sub.2), p.sub.17 is ((u.sub.1 xor u.sub.4) xor u.sub.2), p.sub.18 is ((u.sub.1 xor u.sub.3) xor u.sub.2), and p.sub.19 is (u.sub.1 xor u.sub.2).

(29) After generating bits p.sub.10 through p.sub.19, the u bits are shifted to the right and delay register 510 has an output of u.sub.2 and an input of u.sub.3, shift register 508 has an output of u.sub.3 and an input of u.sub.4, shift register 506 has an output of u.sub.4 and an input of u.sub.0, shift register 504 has an output of u.sub.0 and an input of u.sub.1, and shift register 502 has an output of u.sub.1 and an input of u.sub.2. Using the values of g0 through g9, to produce the next 10 bits, one can see that p.sub.20 is ((((u.sub.2 xor u.sub.1) xor u.sub.0) xor u.sub.4) xor u.sub.3), p.sub.21, is (((u.sub.2 xor u.sub.0) xor u.sub.4) xor u.sub.3), p.sub.22 is ((u.sub.2 xor u.sub.1) xor u.sub.3), p.sub.23 is (((u.sub.2 xor u.sub.1) xor u.sub.4) xor u.sub.3), p.sub.24 is (((u.sub.2 xor u.sub.1) xor u.sub.0) xor u.sub.3), p.sub.25 is (((u.sub.2 xor u.sub.1) xor u.sub.4) xor u.sub.3), p.sub.26 is (((u.sub.2 xor u.sub.0) xor u.sub.4) xor u.sub.3), p.sub.27 is ((u.sub.2 xor u.sub.0) xor u.sub.3), p.sub.28 is ((u.sub.2 xor u.sub.4) xor u.sub.3), and p.sub.29 is (u.sub.2 xor u.sub.3).

(30) After generating bits p.sub.20 through p.sub.29, the u bits are shifted to the right and delay register 510 has an output of u.sub.3 and an input of u.sub.4, shift register 508 has an output of u.sub.4 and an input of u.sub.0, shift register 506 has an output of u.sub.0 and an input of u.sub.1, shift register 504 has an output of u.sub.1 and an input of u.sub.2, and shift register 502 has an output of u.sub.2 and an input of u.sub.3. Using the values of g.sub.0 through g.sub.9, to produce the next 10 bits, one can see that p.sub.30 is ((((u.sub.3 xor u.sub.2) xor u.sub.1) xor u.sub.0) xor u.sub.4), p.sub.31, is (((u.sub.3 xor u.sub.1) xor u.sub.0) xor u.sub.4), p.sub.32 is ((u.sub.3 xor u.sub.2) xor u.sub.4), p.sub.33 is (((u.sub.3 xor u.sub.2) xor u.sub.0) xor u.sub.4), p.sub.34 is (((u.sub.3 xor u.sub.2) xor u.sub.1) xor u.sub.4), p.sub.35 is (((u.sub.3 xor u.sub.2) xor u.sub.0) xor u.sub.4), p.sub.36 is (((u.sub.3 xor u.sub.1) xor u.sub.0) xor u.sub.4), p.sub.37 is ((u.sub.3 xor u.sub.1) xor u.sub.4), p.sub.38 is ((u.sub.3 xor u.sub.0) xor u.sub.4), and p.sub.39 is (u.sub.3 xor u.sub.4).

(31) After generating bits p.sub.30 through p.sub.39, the u bits are shifted to the right and delay register 510 has an output of u.sub.4 and an input of u.sub.0, shift register 508 has an output of u.sub.0 and an input of u.sub.1, shift register 506 has an output of u.sub.1 and an input of u.sub.2, shift register 504 has an output of u.sub.2 and an input of u.sub.3, and shift register 502 has an output of u.sub.3 and an input of u.sub.4. Using the values of g0 through g9, to produce the next 10 bits, one can see that p.sub.40 is ((((u.sub.4 xor u.sub.3) xor u.sub.2) xor u.sub.1) xor u.sub.0), p.sub.41, is (((u.sub.4 xor u.sub.2) xor u.sub.1) xor u.sub.0), p.sub.42 is ((u.sub.4 xor u.sub.3) xor u.sub.0), p.sub.43 is (((u.sub.4 xor u.sub.3) xor u.sub.1) xor u.sub.0), p.sub.44 is (((u.sub.4 xor u.sub.3) xor u.sub.2) xor u.sub.0), p.sub.45 is (((u.sub.4 xor u.sub.3) xor u.sub.1) xor u.sub.0), p.sub.46 is (((u.sub.4 xor u.sub.2) xor u.sub.1) xor u.sub.0), p.sub.47 is ((u.sub.4 xor u.sub.2) xor u.sub.0), p.sub.48 is ((u.sub.4 xor u.sub.1) xor u.sub.0), and p.sub.49 is (u.sub.4 xor u.sub.0).

(32) After generating bits p.sub.40 through p.sub.49, the u bits are shifted to the right and delay register 510 has an output of u.sub.0 and an input of u.sub.1, shift register 508 has an output of u.sub.1 and an input of u.sub.2, shift register 506 has an output of u.sub.2 and an input of u.sub.3, shift register 504 has an output of u.sub.3 and an input of u.sub.4, and shift register 502 has an output of u.sub.4 and an input of u.sub.0. However, because this embodiment employs tail biting, the inputs and outputs of shift registers 502, 504, 506, 508 are exactly the same as those of the initial state. When the inputs and outputs of shift registers 502, 504, 506, 508 are identical to those of the initial state, the process is completed.

(33) As one can see from the above example, when using convolutional coding with a code rate of 1/10, each of the five information bits, produces 10 coded bits. Therefore, exemplary convolutional encoder 500 produces a 50-bit codeword from the five information bits.

(34) By altering the generator polynomials of FIG. 5 such that gi=(g.sub.i,0, g.sub.i,1, g.sub.i,2, g.sub.i,3, g.sub.i,4), g0=(1 0 1 0 1), g1=(1 0 1 1 1), g2=(1 1 0 1 1), g3=(1 1 1 1 1), and g4=(1 1 0 0 1) (with no g.sub.5 through g.sub.9, and continuing to use tail biting, altered exemplary convolutional encoder 500 may have a code rate of 1/5 (each information bit is encoded into 5 coded bits). By using the newly presented generator polynomials and performing the operations previously discussed with respect to the convolutional encoder having a code rate of 1/10 (a (50, 5) convolutional code), one can see that the information bits u.sub.4 u.sub.3 u.sub.2 u.sub.1 u.sub.0 generate produced bits p.sub.0 through p.sub.24 as p.sub.0=((u.sub.0 xor u.sub.3) xor u.sub.1), p.sub.1=(((u.sub.0 xor u.sub.3) xor u.sub.2) xor u.sub.1), p.sub.2=(((u.sub.0 xor u.sub.4) xor u.sub.2) xor u.sub.1), p.sub.3=((((u.sub.0 xor u.sub.4) xor u.sub.3) xor u.sub.2) xor u.sub.1), p.sub.4=((u.sub.0 xor u.sub.4) xor u.sub.1), p.sub.5=((u.sub.1 xor u.sub.4) xor u.sub.2), p.sub.6=(((u.sub.1 xor u.sub.4) xor u.sub.3) xor u.sub.2), p.sub.7=(((u.sub.1 xor u.sub.0) xor u.sub.3) xor u.sub.2), p.sub.8=((((u.sub.1 xor u.sub.0) xor u.sub.4) xor u.sub.3) xor u.sub.2), p.sub.9=((u.sub.1 xor u.sub.0) xor u.sub.2), p.sub.10=((u.sub.2 xor u.sub.0) xor u.sub.3), p.sub.11=(((u.sub.2 xor u.sub.0) xor u.sub.4) xor u.sub.1), p.sub.12=(((u.sub.2 xor u.sub.1) xor u.sub.4) xor u.sub.3), p.sub.13=((((u.sub.2 xor u.sub.1) xor u.sub.0) xor u.sub.4) xor u.sub.3), p.sub.14=((u.sub.2 xor u.sub.1) xor u.sub.3), p.sub.15=((u.sub.3 xor u.sub.1) xor u.sub.4), p.sub.16=(((u.sub.3 xor u.sub.1) xor u.sub.0) xor u.sub.2), p.sub.17=(((u.sub.3 xor u.sub.2) xor u.sub.0) xor u.sub.4), p.sub.18=((((u.sub.3 xor u.sub.2) xor u.sub.1) xor u.sub.0) xor u.sub.4), p.sub.19=xor u.sub.2) xor u.sub.4), p.sub.20=((u.sub.4 xor u.sub.2) xor u.sub.0), p.sub.21=(((u.sub.4 xor u.sub.2) xor u.sub.1) xor u.sub.3), p.sub.22=(((u.sub.4 xor u.sub.3) xor u.sub.1) xor u.sub.0), p.sub.23=((((u.sub.4 xor u.sub.1) xor u.sub.2) xor u.sub.1) xor u.sub.0), and p.sub.24=xor u.sub.3) xor u.sub.0). When using convolutional coding, a BPSK modulation or a

(35) $\frac{}{2}$
shifted BPSK modulation is very robust, as previously mentioned, and may be used to modulate the burst header. Other types of modulation may be used in other embodiments, including, but not limited to, offset quadrature phase shift keying (OQPSK), 8 phase shift keying (8PSK), and 16 amplitude and phase shift keying (16APSK).

(36) In some embodiments, a burst header may be modulated according to a predefined modulation, which may include the OQPSK modulation, the 8PSK modulation, or the 16APSK modulation. However, by mapping each coded bit of the code header, the effective modulation type for the modulated burst header may be

(37) $\frac{}{2}$
shifted BPSK. For example, with reference to FIG. 6, when OQPSK modulation is to be used for modulating the burst header, an even coded bit of the burst header having a value of 0 is mapped to a symbol of 00, an even coded bit of the burst header having a value of 1 is mapped to a symbol of 11, an odd coded bit of the burst header having a value of 0 is mapped to a symbol of 10, and an odd coded bit of the burst header having a value of 1 is mapped to a symbol of 01. When 8PSK modulation is to be used for modulating the burst header, an even coded bit of the burst header having a value of 0 is mapped to a symbol of 000, an even coded bit of the burst header having a value of 1 is mapped to a symbol having a value of 011, an odd coded bit of the burst header having a value of 0 is mapped to a symbol having a value of 110, and an odd coded bit having a value of 1 is mapped to a symbol having a value of 101. When 16APSK modulation is to be used for modulating the burst header an even coded bit of the burst header having a value of 0 is mapped to a symbol having a value of 1100, an even coded bit of the burst header having a value of 1 is mapped to a symbol having a value of 1111, an odd coded bit having a value of 0 is mapped to a symbol of 1110, and an odd coded bit having a value of 1 is mapped to a symbol of 1101. This assumes that the bit to symbol mapping for OQPSK, 8PSk and 16APSK is as given in FIGS. 7-9, respectively.

(38) By performing the mappings as described above, an effective modulation of the burst header is

(39) $\frac{}{2}$
shifted BPSK.

Satellite Gateway

(40) FIG. 10 is a functional block diagram illustrating a portion 1000 of satellite gateway 106. Satellite gateway 106 may include a receiver 1002, a demodulator 1004, and an application specific integrated circuit (ASIC) 1006. Receiver 1002 may receive modulated encoded bits as symbols according to a predefined modulation type for a burst header of a burst. Demodulator 1004 may receive the modulated encoded bits from receiver 1002 and may demodulate the modulated encoded bits to provide the encoded bits. ASIC 1006 may decode the encoded bits representing information bits based on a particular encoding scheme, which may include a Reed-Muller (16,5) code, a block code (32,5), a convolutional code, or another type of encoding scheme. In at least some embodiments, the information bits include five information bits, which may represent one or more of a modulation type, a code rate, a code type and a spreading factor for a payload of a burst. In an alternate embodiment, ASIC 1006 may be replaced by either a FPGA or a DSP.

CONCLUSION

(41) The disclosed embodiments provide a number of advantages over existing systems such as: a. provides for flexible expansion of supported code rates per inroute without changing a length of the UW; b. eliminates the task of finding a good set of UWs each time additional code rates are added; c. allows modulation and code rate changes for payloads from burst to burst on an inroute; d. allows for more efficient use of bandwidth; and e. provides other information such as a spreading factor for a payload of a burst.

(42) Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms for implementing the claims.

(43) Although the above descriptions may contain specific details, they should not be construed as limiting the claims in any way. Other configurations of the described embodiments are part of the scope of this disclosure. Accordingly, the appended claims and their legal equivalents should only define the invention, rather than any specific examples given.