DEVICE WITH TRANSISTORS DISTRIBUTED OVER SEVERAL SUPERIMPOSED LEVELS INTEGRATING A RESISTIVE MEMORY

Abstract

Method for producing a device with transistors distributed over several levels and provided with a resistive memory cell having an electrode formed of a conductor portion belonging to a connection element connected to a transistor of a given level.

Claims

1. A method for producing a device with transistors distributed over several levels and provided with at least one resistive memory cell comprising a first electrode, a second electrode and a dielectric region arranged between the first electrode and the second electrode, the method including: forming a structure provided with one or more connection elements in at least one first insulator layer surmounting a first transistor of a given level of components, a first electrode of a resistive memory cell being formed of at least one conductor portion of a first connection element among said one or more connection elements, forming a dielectric region of the memory cell on an upper face of the structure, the dielectric region lying on the conductor portion of the first connection element (6.sub.1), assembling on the upper face of the structure a support including a semiconductor layer in which at least one second transistor is intended to be formed, forming at least one second insulator layer, the second insulator layer surmounting the second transistor at least partially produced and the first electrode of the resistive memory cell, forming one or more openings through the second insulator layer, at least one first opening among the one or more openings revealing the dielectric region of the resistive memory cell, forming in the first opening at least one second electrode of the resistive memory cell on the dielectric region.

2. The method according to claim 1, wherein the dielectric region is a region of a dielectric layer covering the upper face of the structure.

3. The method according to claim 1, wherein the support is assembled by bonding on the dielectric layer or on a layer formed on the dielectric layer.

4. The method according to claim 1, wherein the dielectric region is a region of a dielectric layer covering said structure, the assembly of said structure on said support being produced without prior etching of said dielectric layer

5. The method according to claim 1, wherein the first electrode of a resistive memory cell is formed of the conductor portion coated with at least one metal layer, the production of the metal layer including the steps of: forming a mask on the first insulator layer, the mask being provided with at least one opening facing the conductor portion, etching the first insulator layer through the opening of the mask such as to reveal the conductor portion, depositing the metal layer.

6. The method according to claim 1, wherein at least one second opening among said openings formed in the second insulator layer reveals a region of the second transistor.

7. The method according to claim 6, further including the formation of a conductor element in the second opening, the conductor element being connected to the second electrode of the resistive memory cell.

8. The method according to claim 6, further including after formation of the second insulator layer: forming a hole traversing the second insulator layer and the layer of dielectric material, the hole revealing at least one other connection element among said one or more connection elements, then filling the hole with a conductor material.

9. The method according to claim 8, wherein the hole is formed after said openings through a masking layer blocking said openings, the masking being removed prior to filling the openings and the hole with conductor material.

10. The method according to claim 1, the first connection element being connected to the first transistor.

11. The method according to claim 1, further including: forming another opening traversing the second insulator layer and revealing a conductor part connected to said first connection element, forming in this opening at least one contact pad with said conductor part.

12. A device with transistors distributed over several levels and provided with at least one resistive memory cell provided with a first electrode, a second electrode and a dielectric region arranged between the first electrode and the second electrode, the device including: a structure provided with one or more connection elements in at least one first insulator layer surmounting a first transistor of a given level of components, a resistive memory cell comprising a first electrode formed of at least one conductor portion of a first connection element among said one or more connection elements, the memory cell being moreover provided with a dielectric region lying on the conductor portion of the first connection element, a second electrode of the resistive memory cell being laid out on the dielectric region, at least one second transistor of a level above the given level.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The present invention will be better understood on reading the description of examples of embodiments given for purely indicative purposes and in no way limiting, while referring to the appended drawings in which:

[0046] FIGS. 1A-1K serve to illustrate an example of method for producing a device with superimposed transistor levels and provided with a resistive memory cell;

[0047] FIG. 2 illustrates a variant of embodiment in which an upper level transistor is connected to an upper electrode of the resistive memory cell;

[0048] FIG. 3 illustrates an embodiment of a connection pad on a lower electrode of the resistive memory cell;

[0049] FIG. 4 illustrates a non-volatile memory stage of a circuit in which a device with superimposed transistor levels and with resistive memory cell is integrated.

[0050] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to make it easier to go from one figure to the next.

[0051] The different parts represented in the figures are not necessarily according to a uniform scale in order to make the figures more legible.

[0052] Moreover, in the description hereafter, terms that depend on the orientation of the structure such as vertical, horizontal, upper, lower, lateral, apply in considering that the structure is oriented in the manner illustrated in the figures.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0053] An example of method for producing a device provided with transistors distributed over several levels and at least one resistive memory cell will now be given with reference to FIGS. 1A-1K.

[0054] In this example, the memory cell that is produced may be of OxRAM type, that is to say a memory based on the formation and the reversible rupture of conductor filament(s) in a metal oxide based dielectric material.

[0055] Reference is firstly made to FIG. 1A illustrating a stage or level of the device, in particular the first level N.sub.1, among a plurality of stages or levels N.sub.1, . . . , N.sub.k (with k>1) of electronic components distributed over three dimensions and formed on a substrate 1.

[0056] The substrate 1 may be a bulk substrate or a semiconductor on insulator substrate for example of SOI (Silicon On Insulator) type. Such a substrate is typically provided with a superficial semiconductor layer lying on an insulator layer.

[0057] The level N.sub.1 comprises one or more transistors T.sub.11, T.sub.12 for example of MOS type, of which at least the channel region is formed in a semiconductor layer 2. The transistors T.sub.11, T.sub.12 are covered with at least one insulator layer 5. This insulator layer 5 may be formed of a stack of several sub-layers of insulator material such as for example SiO.sub.2 and SiN.

[0058] One or more connection elements 6.sub.1, 6.sub.2, 6.sub.3, 6.sub.4, are produced in the insulator layer 5. In this example, the connection elements 6.sub.1, 6.sub.2, 6.sub.3, 6.sub.4, each enable a contact to be made on a region of a transistor T.sub.11, T.sub.12 or the semiconductor layer 2 of the first level N.sub.1 or even of the substrate 1 on which this semiconductor layer 2 is formed. The connection elements 6.sub.1, 6.sub.2, 6.sub.3, 6.sub.4 may be formed of portions for example based on copper or tungsten.

[0059] Among the connection elements 6.sub.1, 6.sub.2, 6.sub.3, 6.sub.4, at least one first connection element 6.sub.1 is intended to form an electrode, in particular the lower electrode of the resistive memory cell C.sub.1.

[0060] The first connection element 6.sub.1 comprises a horizontal portion 6a (that is to say which extends in a direction parallel to the semiconductor layer 2) connected to at least one vertical portion 6b (that is to say which extends in a direction orthogonal to the semiconductor layer 2). In FIG. 1A, the vertical direction corresponds to that of a vector z of an orthogonal reference point [O; x; y; z] whereas the horizontal direction is a direction parallel to the plane [O; x; y]. In this example of embodiment, the lower electrode of the cell C.sub.1 is connected to a transistor T.sub.11 of the level N.sub.1.

[0061] FIG. 1A shows a step of producing a mask 11, for example based on photosensitive resin that is laid out on the insulator layer 5. This mask 11 comprises at least one opening 12 arranged facing the horizontal portion 6a of the connection element 6.sub.1.

[0062] Then (FIG. 1B), etching of the insulator layer 5 through the opening 12 of the mask 11 is carried out, such as to remove a thickness of the insulator layer 5 that is located on the horizontal portion 6a and which is not protected by the mask 11. The opening 12 in the insulator layer 5 is thus extended such as to reveal the horizontal portion 6a. The etching of the insulator layer 5 may be carried out for example by means of dry etching.

[0063] The mask 11 is then removed, for example using a stripping method.

[0064] Then (FIG. 1C), it is possible to produce a metal layer 13 on the first connection element 6.sub.1, and in particular on a horizontal portion 6a of this first connection element 6.sub.1. This metal layer 13 may in particular be formed when the etching described previously with reference to FIG. 1B Is carried out so as to remove a thickness of the horizontal portion 6a of the connection element 6.sub.1. In this case, the metal layer 13 forms part of the lower electrode of the memory cell C.sub.1. The metal layer 13 may be formed for example of a stack of Ti and TiN or TaN, Ir, or Pt. The metal layer 13 is preferably based on an inert material vis--vis oxygen. For example a metal layer 13 based on TiN is not very susceptible to oxidisation, which makes it possible to improve the reliability of the memory cell.

[0065] In order to smooth the surface of the insulator layer 5 and the metal layer 13 formed on the horizontal portion 6a, a chemical mechanical polishing (CMP) step may then be carried out. Then, a deposition of a layer of dielectric material 15 is carried out, for example based on a high-k material such as HfO.sub.2 or Ta.sub.2O.sub.5 or Al.sub.2O.sub.3. High-k material is taken to mean a material with a dielectric constant k higher than that of silicon dioxide. The choke of the dielectric material used may be made as a function of that of the metal layer 13. A metal layer based on TiN is particularly suited when the dielectric layer 15 is based on HfO.sub.2.

[0066] More generally, the layer of dielectric material 15 of the cell may be based on a transition metal oxide, such as TiO.sub.2 or even an alloy of HfAlO type. It is also possible to provide the dielectric layer 15 formed of several sub-layers based on similar materials but of different stoichiometries, for example a stack of sub-layers of Ta.sub.2O.sub.5 and TaO.sub.x with x<2.5, HfO.sub.2/HfO.sub.x(with x<2). The dielectric layer 15 may also be formed of sub-layers of different materials, for example a stack of Al.sub.2O.sub.3 and HfO.sub.2, or HfO.sub.2 and Ta.sub.2O.sub.5. The dielectric layer 15 is advantageously deposited over the full wafer as in the example of embodiment of FIG. 1D.

[0067] Full wafer deposition is taken to mean that the dielectric layer 15 is formed such as to cover the entire upper face of the device in the course of being produced.

[0068] The dielectric layer 15 is thus produced on the insulator layer 5 as well as on one or more portions of connection elements, and in particular on the horizontal portion 6a of the first connection element 6.sub.1.

[0069] A region 15a of the dielectric layer 15 arranged on the horizontal portion 6a of the first connection element 6.sub.1 is intended to form a dielectric zone of the resistive memory cell C.sub.1 provided to be intercalated between the lower electrode and an upper electrode.

[0070] Advantageously, the dielectric layer 15 is not etched and may serve as support to a so-called bonding layer 17, for example made of silicon oxide (SiO.sub.2).

[0071] A support including a semiconductor layer 22 is then transferred, for example by molecular bonding. This support may also be provided with an insulator layer 23, for example based on SiO.sub.2, which forms another bonding layer and which is placed in contact with the bonding layer 17 covering the level N.sub.1 of components in order to carry out the molecular bonding. A bonding of oxide on oxide type may in particular be carried out (FIG. 1E). The support including the semiconductor layer 22 may be a substrate of semiconductor on insulator type, such as for example a SOI substrate.

[0072] Then, from the semiconductor layer 22, a transistor T.sub.21 of an upper level N.sub.2, in particular a second level N.sub.2 of the 3D stack is formed at least partially. Typically, the transistor T.sub.21 implemented at this stage comprises a channel region that extends into the semiconductor layer 22, source and drain regions which may be at least partially formed in the semiconductor layer 22, as well as a gate dielectric and gate produced on the semiconductor layer 22 (FIG. 1F). It is then possible to form another insulator layer 35, for example based on SiO.sub.2, such as to cover the second level N.sub.2 of components and in particular the transistor T.sub.21.

[0073] At least one opening 42 is then made in this insulator layer 35 (FIG. 1G).

[0074] This opening 42 also traverses the insulator layers 23 and 17 and emerges on the dielectric region 15a of the memory cell C.sub.1. The opening 42 is thus produced facing the horizontal portion 6a of the first connection element 6.sub.1 forming the lower electrode of the memory cell C.sub.1.

[0075] One or more other openings 44a, 44b, 44c revealing respectively one or more zones of the transistor T.sub.21 of the level N.sub.2 may also be made (FIG. 1H). An opening 44a is for example formed revealing the source region, an opening 44b revealing the gate, and an opening 44c revealing the drain region of the transistor T.sub.1.

[0076] A masking 46 on the insulator layer 35 is then carried out. This masking 46 is provided such as to block the opening 42 in order to protect the region 15a of the dielectric layer 15 (FIG. 1I). In this example of embodiment, the masking 46 is also provided so as to block other openings already produced in the insulator layer 35, in particular the openings 44a, 44b, 44c. The masking 46 comprises a hole 47 situated facing at least one second connection element 6.sub.2 of the first level N.sub.1 among the plurality of connection elements 6.sub.1, 6.sub.2, 6.sub.3.

[0077] Through the hole 47 of the masking 46, etching of the insulator layers 35, 23 is carried out. This etching is extended into the dielectric layer 15, such as to reveal the second connection element 6.sub.2. During this etching, the region 15a of the dielectric layer 15 is protected by the masking 46, in the same way as the transistor T.sub.21 of level N.sub.2.

[0078] The masking 46 is then removed, for example using a stripping method.

[0079] The opening 42 at the bottom of which is located the region 15a of the dielectric layer 15 is thus once again revealed.

[0080] Then, a deposition of at least one conductor layer 51 is carried out in this opening 42. The conductor layer 51 is thus formed on the dielectric region 15a of the memory cell. The conductor layer 51 is preferably metal and for example formed of a stack of Ti and TiN. The deposition of this conductor layer 51 may also be carried out in the openings 44a, 44b, 44c. The conductor layer 51 may thus also be laid out on the source, gate, drain regions of the transistor T.sub.21 of the second level N.sub.2 and on a portion 6a of the second connection element 6.sub.2. In the example of embodiment of FIG. 1J, the conductor layer 51 is also deposited in the hole 47 so as to make contact on the connection element 6.sub.2 of the first level N.sub.1.

[0081] Then, a filling of the openings and the hole in which the metal layer 51 has been formed may be carried out using a conductor material 53, in particular a metal such as tungsten (W).

[0082] In the example of embodiment of FIG. 1K, the stack of the conductor layer 51 and other metal material 53 in the opening 42 makes it possible to produce a conductor element 76.sub.1. This conductor element 76.sub.1 forms an upper electrode of the memory cell C.sub.1 arranged on the dielectric region 15a of the dielectric layer 15.

[0083] In this example of embodiment, the stack of the conductor layer 51 and the metal material 53 in the hole 47 makes it possible to produce another conductor element 762 on the second connection element 6.sub.2. This other conductor element 762 makes it possible to establish a contact on the transistor T.sub.11 of the first level N.sub.1. Other conductor elements 77a, 77b, 77c, are also formed respectively on the source region, gate and drain region of the transistor T.sub.2l of the second level N.sub.2.

[0084] A variant of embodiment illustrated in FIG. 2 provides to form a connection zone 80 between the resistive memory cell C.sub.1 and the transistor T.sub.21 of the second level N.sub.2. The connection zone 80 is established in particular between the conductor element 76.sub.1 forming an upper electrode of the cell C.sub.1 and an electrode of the transistor T.sub.21 of the second level N.sub.2, for example its drain electrode. The fabrication of the connection zone 80 may be carried out during filling such as described previously with reference to FIG. 1K so as to form a superficial metal layer lying on the upper face of the insulator layer 35. Then, this superficial metal layer is etched. To produce the connection zone 80, it is also possible to carry out a method including the formation of an insulator layer (not represented in FIG. 2), carrying out steps of photolithography and etching to form a hole revealing the elements 76.sub.1 and 77c, then filling the hole with a metal material, then planarization by CMP.

[0085] An implementation of the device with superimposed transistors given in FIG. 3 provides for the formation of a connection pad 90 in contact with the first connection element 6.sub.1 serving as lower electrode of the resistive memory cell C.sub.1. This connection pad 90 may be formed by producing an opening through the insulator layers 35, 23, 17, 5, this opening revealing a conductor portion 6b connected to the first connection element 6.sub.1. Then, filling of the opening with conductor material is carried out.

[0086] Advantageously, the filling is carried out during the step described previously with reference to FIG. 1K during which a stack of a conductor layer 51 and the metal material 53 is deposited.

[0087] One or the other of the examples that have just been given corresponds to an embodiment in which the memory cell is formed between a first level and a second level of components. When there are more than two levels or stages it is also possible to produce this cell between two other stages, above the second level.

[0088] One or the other of the methods that have just been described may apply to other types of resistive memories in which the layer 15 is based on a material exhibiting a resistive switching effect.

[0089] A transistor device provided with a resistive memory cell C.sub.1 as described in one or the other of the examples of embodiment described previously may be integrated in a non-volatile memory stage 100 of a circuit, for example a circuit forming a flip-flop and of the type of that described in the document of Jovanovic et al., Design insights for reliable energy efficient non-volatile flip-flop in 28 nm FDSOI, IEEE Conference S3S 2015 (FIG. 4).