RANDOM TELEGRAPH NOISE NATIVE DEVICE FOR TRUE RANDOM NUMBER GENERATOR AND NOISE INJECTION

Abstract

A method (and system) for generating random numbers includes setting a drain voltage Vd on an MOSFET device to maximize a transconductance of the MOSFET device and setting a gate voltage Vg of the MOSFET device to tune as desired a random number statistical distribution of an output of the MOSFET device> The MOSFET device includes a gate structure with an oxide layer including at least one artificial trapping layer in which carrier traps are designed to occupy a predetermined distance from conduction and valance bands of material of the artificial trapping layer.

Claims

1. A semiconductor device, comprising: a substrate; a source region and a drain region embedded in said substrate; and a gate structure formed between said source and drain regions, wherein said gate structure comprises an oxide layer comprising at least one artificial trapping layer in which carrier traps are designed to occupy a predetermined distance from conduction and valance bands of material of said artificial trapping layer.

2. The semiconductor device of claim 1, wherein each of said at least one trapping layer is fabricated using one of nanocrystal deposition, scanning tunnel microscopy, E-beam, and quantum dots formation.

3. The semiconductor device of claim 1, wherein said source and drain regions and said gate structure thereby form a MOS (metal oxide semiconductor) device, said semiconductor device further comprising: an operational amplifier formed on said substrate; and a resistance R interconnected between a first input terminal and an output terminal of said operational amplifier, said operational amplifier and resistor thereby forming a low noise amplifier for said MOS device.

4. The semiconductor device of claim 3, as configured so that an amount of a gate current Ig of said MOS device passes through said resistance R, so that an output voltage of said low noise amplifier V=Ig*R, and wherein a voltage at a second input terminal of said operational amplifier sets a voltage Vg for said gate of said MOS structure.

5. The semiconductor device of claim 4, wherein a voltage at said drain of said MOS is set at a voltage value predetermined to maximize a transconductance gm of said MOS device and wherein Vg is selectively set to tune a random number statistical distribution of voltage values of said output voltage of said operational amplifier.

6. The semiconductor device of claim 3, as configured so that an amount of a drain current Id of said MOS device passes through said resistance R, so that an output voltage of said low noise amplifier V=Id*R, and wherein a voltage at a second input terminal of said operational amplifier sets a voltage Vd for said drain of said MOS structure.

7. The semiconductor device of claim 6, wherein said voltage Vd at said drain of said MOS is set at a voltage value predetermined to maximize a transconductance gm of said MOS device and wherein Vg is selectively set to tune a random number statistical distribution of voltage values of said output voltage of said operational amplifier.

8. A random number generator, comprising: a random telegraph noise native device; a low noise amplifier connected to an output of said random telegraph noise native device; a filter; and a comparator, wherein said low noise amplifier, said filter, and said comparator are configured to form an analog-to-digital (A/D) converter for an output signal from said random telegraph noise native device.

9. The random number generator of claim 8, wherein said random telegraph noise native device comprises one of an MOSFET (metal oxide semiconductor field effect transistor) structure and an RRAM (resistive random access memory) structure.

10. The random number generator of claim 8, wherein said random telegraph noise native device comprises a semiconductor device comprising: a substrate; a source region and a drain region embedded in said substrate; and a gate structure formed between said source and drain regions, wherein said gate structure comprises an oxide layer comprising at least one artificial trapping layer in which carrier traps are designed to occupy a predetermined distance from conduction and valance bands of material of said artificial trapping layer.

11. The random number generator of claim 10, wherein each of said at least one trapping layer is fabricated using one of nanocrystal deposition, scanning tunnel microscopy, E-beam, and quantum dots formation.

12. The random number generator of claim 10, wherein said source and drain regions and said gate structure thereby form a MOS (metal oxide semiconductor) device, said semiconductor device further comprising: an operational amplifier formed on said substrate; and a resistance R interconnected between a first input terminal and an output terminal of said operational amplifier, said operational amplifier and resistor thereby forming a low noise amplifier for said MOS device.

13. The random number generator of claim 12, as configured so that an amount of a gate current Ig of said MOS device passes through said resistance R, so that an output voltage of said low noise amplifier V=Ig*R, and wherein a voltage at a second input terminal of said operational amplifier sets a voltage Vg for said gate of said MOS structure.

14. The random number generator of claim 13, wherein a voltage at said drain of said MOS is set at a voltage value predetermined to maximize a transconductance gm of said MOS device and wherein Vg is selectively set to tune a random number statistical distribution of voltage values of said output voltage of said operational amplifier.

15. The random number generator of claim 12, as configured so that an amount of a drain current Id of said MOS device passes through said resistance R, so that an output voltage of said low noise amplifier V=Id*R, and wherein a voltage at a second input terminal of said operational amplifier sets a voltage Vd for said drain of said MOS structure.

16. The random number generator of claim 15, wherein said voltage Vd at said drain of said MOS is set at a voltage value predetermined to maximize a transconductance gm of said MOS device and wherein Vg is selectively set to tune a random number statistical distribution of voltage values of said output voltage of said operational amplifier.

17. A method of generating random numbers, said method comprising: setting a drain voltage Vd on an MOSFET (metal oxide semiconductor field effect transistor) device to maximize a transconductance of said MOSFET device; and setting a gate voltage Vg of said MOSFET device to tune as desired a random number statistical distribution of an output of said MOSFET device, wherein said MOSFET device comprises a gate structure comprising an oxide layer including at least one artificial trapping layer in which carrier traps are designed to occupy a predetermined distance from conduction and valance bands of material of said artificial trapping layer.

18. The method of claim 17, wherein each of said at least one trapping layer is fabricated using one of nanocrystal deposition, scanning tunnel microscopy, E-beam, and quantum dots formation.

19. The method of claim 17, wherein an output voltage of said MOSFET is provided as an input signal into a low noise amplifier.

20. The method of claim 19, wherein said low noise amplifier comprises a component of an analog-to-digital (A/D) converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The foregoing and other exemplary purposes, aspects and advantages will be better understood from the following detailed description of an exemplary embodiment of the invention with reference to the drawings, in which:

[0011] FIG. 1A illustrates an exemplary conventional random number generator that uses a small noise source that requires a relatively large amplifier and filter circuits;

[0012] FIG. 1B illustrates a comparable circuit of an exemplary embodiment of the present invention, using a relatively smaller amplifier and filter circuits;

[0013] FIG. 2 shows exemplarily the concept of controlling tunneling time 200;

[0014] FIG. 3 shows exemplarily the concept of artificial traps 300 for noise engineering;

[0015] FIG. 4 shows exemplarily a MOS-type device 200 having at least one trapping layer 206 in the gate oxide structure 204;

[0016] FIG. 5A illustrates an exemplary embodiment 500 of a noise generator circuit of the present invention using Ig-RTN;

[0017] FIG. 5B illustrates an exemplary embodiment 550 of a noise generator circuit of the present invention using Id-RTN; and

[0018] FIG. 6 illustrates how the random noise generator circuits of the present invention can be selectively biased and tuned.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION

[0019] Referring now to the drawings, and more particularly to FIGS. 1B -6, exemplary embodiments of the method and structures of the present invention will now be described.

[0020] As shown exemplarily in FIG. 1B, an exemplary embodiment of the present invention uses a large noise source device 152, which generates large noise at high frequency, which, in turn, permits a smaller amplifier and filter for the A/D converter 154. These smaller dimensions for the A/D converter downsize the circuit area of the present invention to 1200 mm.sup.2, which provides a savings in circuit area of the conventional circuit 100 shown in FIG. 1A.

[0021] The large noise source 152 of the present invention uses native device trapping, which will be explained shortly.

[0022] FIG. 2 shows exemplarily the concept of controlling of tunneling time. On the left side is shown how different trap depths change tunneling times, which aspect provides different noise signals shown on the right side of FIG. 2. There are several different parameters known in the art the control tunneling time, including temperature, voltage, and oxide layer composition (e.g., high K or other material). Prior art methods relied upon temperature for changing tunnel times. In contrast, the present invention uses voltage to change tunneling time and engineer the random variable shown on the right side of FIG. 2.

[0023] FIG. 3 shows exemplarily how artificial traps can be engineered to control tunneling time by change location of the traps relative to the conduction and valence bands; the closer the traps are located to the conduction and valence bands, the more often emissions occur.

[0024] FIG. 4 shows exemplarily an MOS-type RTN native device 400 having source/drain 402, 404 and gate structure 406 with at least one artificial trapping layer 408 in the gate oxide.

[0025] Such MOS-type structure 400 permits small capacitance for trapping, Q=C V. In most implementations of the present invention, the traps will be intentionally created close to Ef. There can be multiple artificial trapping layers 408, or only a single artificial trapping layer, in the gate oxide. With single trap layer, the output can only have two different states. With multiple layers, the output can have more than two states, which feature enhances the information (data) delivered from the same amount of devices. The MOS structure permits small width and short channel, which is ideal for high density circuit integration.

[0026] The artificial trapping layer(s) 408 can exemplarily be fabricated by such any method that permits traps to be selectively located relative to the conduction and valence bands. For example, high density Ru nanocrystals can be deposited, much as currently done for non-volatile memory applications. Other methods such as STM (scanning tunnel microscopy), quantum dots, other nanocrystal deposition can be used for generating the artificial trapping layer(s).

[0027] FIG. 5A shows exemplarily how the MOS RTN native device 502 is connected to provide Ig as an output signal for low noise amplifier (LNA) 504 to provide output signal Ig*R, where R is the feedback resistance of the LNA. The control parameters 506 are voltages Vd and Vg.

[0028] FIG. 5B shows how the RTN native device 552 is connected to provide Id as input into LNA 554, and control parameters 556 are again Vd and Vg. The output signal in this configuration is Id*R.

[0029] FIG. 6 shows details related to the control parameters Vd and Vg shown in FIGS. 5A and 5B. Thus, as shown in FIG. 6, the circuit of FIG. 5A can be controlled by biasing the noise-source transistor to be in the maximum gm regime, meaning that Vd is chosen to maximize gm. To modify the random number behavior, the statistical distribution, Vg is chosen to tune the tunneling time and thereby control the random variable's probability function.

[0030] While the invention has been described in terms of several exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modification.

[0031] Further, it is noted that, Applicants' intent is to encompass equivalents of all claim elements, even if amended later during prosecution.