Integrated capacitor comprising an electrically insulating layer made of an amorphous perovskite-type material and manufacturing process

Abstract

An integrated capacitor comprises a layer of dielectric material known as functional dielectric material based on crystallized material of perovskite type, between at least one first electrode known as a bottom electrode at the surface of a substrate and at least one second electrode known as a top electrode, said electrodes being electrically insulated by a layer of electrically insulating material in order to allow at least one contact on the top electrode. The electrically insulating material is made of an amorphous dielectric material of perovskite type having a dielectric constant lower than that of the crystallized material of perovskite type. The contact is formed from an etched contacting layer in contact with the electrically insulating dielectric layer level with its surface parallel to the plane of the layers. A process for manufacturing such an integrated capacitor is also provided.

Claims

1. An integrated capacitor, comprising: a layer of dielectric material known as a functional dielectric material based on a crystallized material of perovskite type, between at least one first electrode known as a bottom electrode above a surface of a substrate and at least one second electrode known as a top electrode above the bottom electrode; an etched contacting layer having a first region over a surface of the top electrode, a second region that extends horizontally beyond a first edge of the top electrode, a third region over a surface of the bottom electrode, and a fourth region that extends horizontally beyond a second, opposing edge of the top electrode; a layer of electrically insulating material over the top electrode, the layer of electrically insulating material defining a first contact between the first region of the etched contacting layer and the surface of the top electrode and a third contact between the third region of the etched contacting layer and the surface of the bottom electrode; and a protective insulating layer over the etched contacting layer, the protective insulating layer being etched to define a second contact in the second region of the etched contacting layer entirely horizontally beyond the first edge of the top electrode and a fourth contact in the fourth region of the etched contacting later entirely horizontally beyond the second, opposing edge of the top electrode, wherein: the electrically insulating material comprises an amorphous dielectric material of perovskite type having a dielectric constant lower than that of the crystallized material of perovskite type, a surface of the first contact is parallel to a plane of the layer of dielectric material, and the amorphous dielectric material comprises an oxide selected from the group consisting of PZT, SrTiO.sub.3, (Pb,La)(Zr,Ti)O.sub.3, Pb(Mg,Nb,Ti)O.sub.3, Pb(Zn,Nb,Ti)O.sub.3, and BiFeO.sub.3.

2. The integrated capacitor according to claim 1, wherein the crystallized functional dielectric material is an oxide selected from the group consisting of Pb(Sr,Ti)O.sub.3, SrTiO.sub.3, (Ba,Sr)TiO.sub.3, (Pb,La)(Zr,Ti)O.sub.3, Pb(Mg,Nb,Ti)O.sub.3, Pb(Zn,Nb,Ti)O.sub.3, BiFeO.sub.3, and BaTiO.sub.3.

3. The integrated capacitor according to claim 1, wherein a chemical composition of the functional dielectric material is the same as a chemical composition of the electrically insulating dielectric material.

4. The integrated capacitor according to claim 1, wherein the electrodes are made of platinum, ruthenium, ruthenium oxide, iridium, iridium oxide, or gold.

5. The integrated capacitor according to claim 1, wherein the substrate is made of silicon and comprises an upper oxide layer.

6. The integrated capacitor according to claim 1, further comprising an adhesion layer disposed between the substrate and the bottom electrode.

7. A process for manufacturing an integrated capacitor according to claim 1, comprising at least one step of producing the layer of electrically insulating material, on top of or underneath the top electrode, via a sol-gel process comprising: spreading a sol-gel solution; drying said solution at a temperature between around 100 C. and 150 C.; and pyrolysis of said dried solution at a temperature between around 300 C. and 500 C. resulting in the amorphous dielectric material.

8. The process for manufacturing the integrated capacitor according to claim 7, further comprising at least one step of producing the layer of dielectric material via a sol-gel process comprising: spreading a sol-gel solution on the surface of a substrate comprising a bottom electrode; drying said solution at a temperature between around 100 C. and 150 C.; pyrolysis of said dried solution at a temperature between around 300 C. and 500 C. resulting in the functional dielectric material; and crystallization of said functional dielectric material brought to a temperature greater than or equal to the crystallization temperature of said material to obtain the crystallized functional dielectric material.

9. The process for manufacturing an integrated capacitor according to claim 8, wherein the crystallization is carried out by rapid thermal annealing.

10. The integrated capacitor according to claim 1, wherein the first contact overlaps with the bottom electrode.

11. The integrated capacitor according to claim 10, wherein the second contact overlaps with the bottom electrode.

12. The integrated capacitor according to claim 1, wherein a surface of the second contact is parallel to the plane of the layer of dielectric material.

13. The integrated capacitor according to claim 1, wherein at least part of the protective insulating layer is directly over and in contact with the layer of electrically insulating material.

14. The integrated capacitor according to claim 1, wherein an entirety of the first contact does not overlap with an entirety of the second contact.

15. The integrated capacitor according to claim 14, wherein an entirety of the third contact does not overlap with an entirety of the fourth contact.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be better understood and other advantages will appear on reading the following description given non-limitingly and owing to the appended figures, among which:

(2) FIG. 1 illustrates an example of an MIM capacitor structure according to the known art;

(3) FIG. 2 illustrates an example of the use of an insulating dielectric to make the contacts on the MIM capacitor according to the known art;

(4) FIG. 3 illustrates the appearance of defects in the PZT, due to the presence of hydrogen in an undoped silicon glass;

(5) FIGS. 4a and 4b illustrate two examples of processes for sol-gel-type spreading onto a substrate by spin-coating and by dip-coating;

(6) FIGS. 5a and 5b illustrate an example of a multilayer for a high permittivity capacitor according to the invention with an unetched or etched bottom electrode; and

(7) steps 6a to 6k illustrate the various steps of a process for manufacturing an integrated capacitor according to the invention.

DETAILED DESCRIPTION

(8) According to the invention, it is proposed to use a sol-gel process that makes it possible to produce components having a high permittivity dielectric layer and a layer of material having a lower permittivity providing an electrically insulating role between the two types of electrodes known as bottom and top electrodes.

(9) In the case of very high permittivity materials, a well-known technique is the sol-gel process and notably of sol-gel polymerization type. The sol-gel deposition of PbTiO.sub.3 (PT) was reported for the first time in 1984 by GURKOVICH S. R., Blum J. B., Preparation of monolithic lead-titanate by sol-gel process, in Ultrastructure Processing of Ceramics, Glasses and Composites, L. L. Ha. D. R. Ulrich, Editor, Wiley-Interscience: New-York, 152-160, 1984.

(10) The following year, Budd et al., BUDD K. D., Dey S. K., PAYNE D. A., Sol-gel processing of PT, PZ, PZT and PLZT thin films. Br. Ceram. Proc. 107-121, 1985, described the synthesis of perovskite thin films based on lead (PT, PZ, PZT, PLZT). This process uses a solution containing reactive precursors such as metal salts or alkoxides, and a solvent. The deposition of thin films may take place by spin-coating or else by dip-coating as illustrated in FIGS. 4a and 4b.

(11) The principle of the sol-gel process is based on a succession of hydrolysis-condensation reactions, at a temperature close to ambient temperature, which results in the formation of an inorganic polymer, which may then be heat treated. The step of hydrolysing metal alkoxides is shown schematically by the following reaction:
M-OR+H.sub.2O.fwdarw.M-OH+ROH

(12) where M is a metal cation, and R an alkyl organic group. This reaction allows the conversion of the alkoxy functions to hydroxyl functions. The solution obtained is called a sol; that is to say a solid phase, constituted of small entities, dispersed in a liquid (the solvent). The hydroxyl functions are then converted to M-O-M species corresponding to the formation of an inorganic macromolecular network constituting the gel. This takes place following several condensation reactions (formation of oxo, O, bridges by oxolation) reactions, with removal of alcohol and of water.
M-OH+M-OR.fwdarw.M-O-M+ROH
M-OH+M-OH.fwdarw.M-O-M+H.sub.2O

(13) The production of piezoelectric films via the sol-gel technique consists of a succession of steps of spreading the sol-gel solution and of heat treatments. For example, a succession of steps of spreading of sol-gel, drying (at 100 C.-150 C.), pyrolosis (at 300 C.-500 C.), and crystallization (at 600 C.-800 C.).

(14) The solution is customarily spread over a substrate by spin-coating. The film thickness deposited depends mainly on the speed of rotation of the spin coater and on the physicochemical parameters of the solution (viscosity, concentration, evaporation rate). A drying step makes it possible to evaporate a portion of the solvents and to obtain a solid deposit. The layer then undergoes a pyrolysis (or calcination) in order to remove the organic residue.

(15) This step, generally carried out on a hotplate, is crucial since it considerably conditions the structural quality of the piezoelectric film. The calcination temperature must be high enough in order to remove all of the organic residue (typically between 300 C. and 450 C.). Otherwise, the trapping of organic matter may lead to the presence of porosities. However, too high a temperature risks promoting the appearance of a parasitic phase, such as pyrochlore in the case of PZ, described in the publication: GONG W., L J. F., CHu X., LI L., J. Eur. Ceram. Soc. 24, 2977-2982, 2004.

(16) After pyrolysis, the amorphous layer obtained is crystallized and densified at a temperature between 600 C. and 800 C. This crystallization step is usually carried out by rapid thermal annealing (RTA), rather than by conventional annealing, in order, notably, to limit the thermal budget. The rapid thermal annealing (RTA) process is today among the most-used processes for the crystallization of thin films. Its main asset is a transmission of thermal energy via radiation and not by convection. This results in extremely rapid temperature rises which may reach up to 300 C./s owing to the use of halogen lamps. The annealing operations last a few tens of seconds. The thickness of a layer after crystallization is generally around 50 nm. Depending on the final material thickness desired, it is necessary to repeat all of the steps described previously several times. However, the crystallization step is very often carried out every two or three layers pyrolysed. The advantage of using the RTA process in order to reduce both the thermal budget and the manufacturing time of the films is then understood.

(17) The sol-gel process has the advantage of being inexpensive and relatively simple to implement, requiring only a spreading area, hotplates and an RTA furnace. Furthermore, it does not require significant maintenance, which is a considerable asset compared to vacuum deposition techniques. It is furthermore very flexible for the development of complex materials. It is thus possible to easily vary the compositions by means of metering the organometallic precursors, or else to incorporate dopants in order to optimize the properties of the films.

(18) Generally, the material deposited by the sol-gel process undergoes several steps. After pyrolysis, the material has been stripped of all its organic compounds (therefore H and C). The resulting material is therefore exclusively composed of non-organic materials after this pyrolysis (sometimes called calcination). As the material is not crystallized, it does not have a very high dielectric constant.

(19) The present invention proposes to exploit this property of lower dielectric constant in order to use this layer referred to as a calcined or pyrolysed layer, as an insulating dielectric DI as illustrated in FIG. 2. This has the advantage of making it possible to use a single material as insulating dielectric DI and functional dielectric DF, the insulating dielectric DI does not have hydrogenated compounds capable of weakening the properties of the functional dielectric DF, the dielectric constant of the insulating dielectric DI remains low compared to that of the functional dielectric DF (typically, for PZT, the dielectric constant of the non-crystallized calcined PZT lies between 20 and 30, whereas the dielectric constant of the crystallized PZT lies between 400 and 1500).

Example of an Implementation Process According to the Invention

(20) The integrated capacitor according to the invention comprises, in this example, a functional dielectric material of perovskite type having a high dielectric constant, which may notably be PZT, and an electrical insulator of dielectric type of amorphous perovskite type, which has not undergone a final crystallization annealing phase, between the bottom electrode and the top electrode, as illustrated in FIG. 5, which shows one possible multilayer for a very high value integrated capacitor using PZT as insulating dielectric DI.sub.am (calcined) and functional dielectric DF.sub.cris (crystallized), starting from a substrate S.sub.0 covered with an oxide layer S.sub.1 and an adhesion layer C.sub.ac and comprising a bottom electrode Ei and a top electrode Es.

(21) The various steps of the process are described below with the aid of FIGS. 6a to 6k.

(22) In order to produce such a multilayer, it is possible to use a silicon substrate S.sub.0, typically 200 mm in diameter. An oxidation step is carried out that defines a surface layer S.sub.1 of SiO.sub.2 having a thickness of 500 nm, as illustrated in FIG. 6a. This makes it possible to prevent diffusions towards the substrate.

(23) An adhesion layer C.sub.ac is then deposited by sputtering of 5 nm of titanium Ti followed by an oxidation, by rapid thermal annealing, of 2 minutes at 750 C. under oxygen O.sub.2. This adhesion layer may also be made of tantalum Ta.

(24) The bottom electrode Ei as illustrated in FIG. 6b, made of Pt (100 nm) is deposited by sputtering. This electrode may also be made of iridium. The bottom electrode may or may not be etched, for example by ion milling in accordance with a suitable pattern.

(25) The functional dielectric made of PZT is then prepared via the sol-gel process as mentioned in the reaction scheme described previously, which is referenced DF.sub.cris and is illustrated in FIG. 6c. Typically, 200 nm of PZT can be deposited by carrying out at least one spin-coating deposition, followed by a drying operation at 110 C. for 5 minutes on a hotplate, and a pyrolysis step at 350 C. for 5 minutes on a hotplate. In the case of the use of successive depositions in order to obtain the desired thickness of PZT, each deposition is followed by a drying and pyrolysis operation before the next deposition.

(26) A final crystallization annealing operation is then carried out at 700 C. in air for 30 seconds. Generally, this annealing should be carried out every 3 PZT deposition/drying/pyrolysis operations.

(27) It is possible to use materials other than PZT, having a very high permittivity, which may notably be one of the following oxides: SrTiO.sub.3, (Ba,Sr)TiO.sub.3, (Pb,La)(Zr,Ti)O.sub.3, Pb(Mg,Nb,Ti)O.sub.3, Pb(Zn,Nb,Ti)O.sub.3, BiFeO.sub.3, BaTiO.sub.3.

(28) The PZT is then etched by a wet etching process based on the following preparation: HF at 1%, HCl at 37% in water and in the following relative proportions: 5/9/50. This etching may also be carried out by dry etching using RIE (Reactive Ion Etching) equipment with gases of chlorinated type with addition of argon as illustrated in FIG. 6d. This etching is defined using, prior to the etching, a photoresist defined by a photolithography step using a dedicated mask.

(29) The top electrode Es made of Pt and having a thickness typically of 100 nm, as illustrated in FIG. 6e, is then deposited by sputtering. This electrode may equally well be made of ruthenium, or ruthenium oxide, made of iridium, or made of iridium oxide, or else made of gold. This electrode is etched by ion milling. This etching is defined using, prior to the etching, a photoresist defined by a photolithography step using a dedicated mask.

(30) The insulating dielectric, referenced DI.sub.am, and illustrated in FIG. 6f is then deposited by the sol-gel process but not carrying out the final crystallization step. In this case, use is made of PZT or of other materials which may notably be SrTiO.sub.3, (Ba,Sr)TiO.sub.3, (Pb,La)(Zr,Ti)O.sub.3, Pb(Mg,Nb,Ti)O.sub.3, Pb(Zn,Nb,Ti)O.sub.3, BiFeO.sub.3, BaTiO.sub.3. Typically, the insulating dielectric layer may have a thickness of the order of 400 nm approximately, obtained by six calcined depositions carried out by spin-coating, followed by a drying operation at 110 C. for 5 minutes on a hotplate, followed by a pyrolysis operation at 350 C. for 5 minutes on a hotplate, repeated six times. It is possible to reduce or increase the thickness by reducing or increasing the number of depositions (spin-coating+drying at 110 C. for 5 minutes on hotplate+pyrolysis at 350 C. for 5 minutes on hotplate) or the viscosity of the sol-gel liquid.

(31) This insulating dielectric is then etched by a wet etching process based on the preparation: 1% HF-37% HClH.sub.2O in the proportions 5/9/200. This etching is defined using, prior to the etching, a photoresist defined by a photolithography step using a dedicated mask as illustrated in FIG. 6g.

(32) A metal is then deposited to make the contact Rc as illustrated in FIG. 6h. This metal may, non-limitingly, be Al, Al/Cu, Al/Si, Cu, Pt, etc. Notably it is possible to use an Al/1% Cu alloy having a thickness of 1 m, deposited by sputtering.

(33) This layer is then etched by a wet or dry etching process as illustrated in FIG. 6i. This etching is defined using, prior to the etching, a photoresist defined by a photolithography step using a dedicated mask.

(34) Finally, a protective insulating layer I as illustrated in FIG. 6j is deposited, which is etched in order to access the contact layer Rc as illustrated in FIG. 6k.