Devices comprising high-K dielectric layer and methods of forming same

Abstract

Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO.sub.2) and zirconium dioxide (ZrO.sub.2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO.sub.2 and/or tetragonal phase ZrO.sub.2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.

Claims

1. A method of forming a semiconductor device, said method comprising: forming, on a semiconductor substrate, a 10 to 40 thick dielectric layer comprising at least one of hafnium dioxide (HfO.sub.2) and zirconium dioxide (ZrO.sub.2), said dielectric layer having a continuous planar surface; after forming the dielectric layer, performing plasma deposition of an inert gas, such that the inert gas penetrates the continuous planar surface of the dielectric layer, thereby forming an inert gas impregnated dielectric layer; and after performing the plasma deposition, applying a high voltage bias at 7kV-15kV to the inert gas impregnated dielectric layer, thereby forming a high-k dielectric layer comprising at least some tetragonal phase HfO.sub.2 or tetragonal phase ZrO.sub.2.

2. The method according to claim 1, wherein the dielectric layer comprises ZrO.sub.2.

3. The method according to claim 1, wherein the dielectric layer comprises HfO.sub.2.

4. The method according to claim 1, wherein the dielectric layer consists essentially of HfO.sub.2.

5. The method according to claim 1, wherein the inert gas is selected from argon and helium.

6. The method according to claim 5, wherein the inert gas is helium.

7. The method according to claim 6, wherein the dielectric layer comprises HfO.sub.2.

8. The method according to claim 7, wherein, after applying the high voltage bias, at least 50% of the HfO.sub.2 present in the high-k dielectric, is in the tetragonal phase.

9. The method according to claim 1, wherein, after applying the high voltage bias, at least 50% of the total HfO.sub.2 and ZrO.sub.2 present in the high-k dielectric, is in the tetragonal phase.

10. The method according to claim 1, wherein the high-k dielectric layer is 10 to 20 thick.

11. The method according to claim 1, wherein the semiconductor substrate comprises a silicon dioxide interlayer and the dielectric layer is formed directly on the silicon dioxide interlayer.

12. The method according to claim 1, wherein the high-k dielectric layer comprises at least one of: hafnium dioxide (HfO.sub.2), wherein at least 50% of said HfO.sub.2 is in the tetragonal phase; or zirconium dioxide (ZrO.sub.2), wherein at least 50% of said ZrO.sub.2 is in the tetragonal phase.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A and 1B depict simple schematics showing the plasma deposition and high voltage bias steps performed in accordance with an embodiment of the invention.

(2) FIG. 2 depicts a flow chart showing an embodiment of the inventive method of forming a semiconductor device.

(3) FIGS. 3A-H depict charts showing properties relating to embodiments of the invention and comparative examples.

DETAILED DESCRIPTION OF THE INVENTION

(4) The present invention is generally directed to semiconductor devices having a high-k dielectric, to methods of forming the same, and to electronic devices that contain the same.

(5) Although this invention is susceptible to embodiment in many different forms, certain embodiments of the invention are shown and described. It should be understood, however, that the present disclosure is to be considered as an exemplification of the principles of this invention and is not intended to limit the invention to the embodiments illustrated.

(6) In a first aspect, the invention provides a semiconductor device that includes: a semiconductor substrate; and a 10 to 40 thick high-k dielectric layer containing at least one of hafnium dioxide (HfO.sub.2) and zirconium dioxide (ZrO.sub.2), said high-k dielectric layer being disposed on the semiconductor substrate, and containing at least some tetragonal phase HfO.sub.2 or tetragonal phase ZrO.sub.2.

(7) The semiconductor substrate includes one or more layers, and may optionally include one or more of a channel region, electrode(s), and an interfacial layer (e.g., SiO.sub.2 or SiOH). The semiconductor substrate may be doped or undoped, and may optionally contain doped and undoped regions therein. The semiconductor substrate may optionally be pre-treated with any desirable pre-treatment (e.g., OH-terminated).

(8) In some embodiments, the semiconductor substrate contains silicon. In some embodiments, the semiconductor substrate contains a silicon dioxide interlayer. In some such embodiments, the high-k dielectric layer is formed directly on the silicon dioxide interlayer.

(9) The term high-k dielectric layer is a layer that contains a high-k dielectric material, i.e., a material with a high dielectric constant (k), as compared to silicon dioxide (for which k=3.9). A high-k dielectric layer (which may also be referred to as a film) is typically used in place of a silicon dioxide gate dielectric or another dielectric layer of a device in semiconductor manufacturing processes. Replacement of SiO.sub.2 and/or other dielectric layers with high-k layers allows the semiconductor industry to further drive down pattern dimensions in order to reduce transistor size and enhance processor speed in accordance with Moore's Law.

(10) The high-k dielectric layer is disposed on the semiconductor substrate, and contains one or more of hafnium dioxide (HfO.sub.2) and zirconium dioxide (ZrO.sub.2). Known crystalline phases of HfO.sub.2 and ZrO.sub.2 include cubic, tetragonal, and monoclinic. In the high-k dielectric layer of the present invention, at least some of the HfO.sub.2 or ZrO.sub.2 present exists in the tetragonal phase. This tetragonal phase HfO.sub.2 or ZrO.sub.2 remains stable at room temperature.

(11) In some embodiments, the high-k dielectric layer contains tetragonal phase HfO.sub.2. In some embodiments, the high-k dielectric layer contains HfO.sub.2 and at least 50% (e.g., 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, or 100%, including any and all ranges and subranges therein) of the HfO.sub.2 in the high-k dielectric layer is in the tetragonal phase.

(12) In some embodiments, the high-k dielectric layer contains tetragonal phase ZrO.sub.2. In some embodiments, the high-k dielectric layer contains ZrO.sub.2 and at least 50% (e.g., 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, or 100%, any and all ranges and subranges therein) of the ZrO.sub.2 in the high-k dielectric layer is in the tetragonal phase.

(13) In some embodiments, the high-k dielectric layer contains both HfO.sub.2 and ZrO.sub.2 (e.g., Hf.sub.1-xZr.sub.xO.sub.2).

(14) In some embodiments, the high-k dielectric layer contains monoclinic phase HfO.sub.2 and tetragonal phase HfO.sub.2. In some embodiments, the high-k dielectric layer contains monoclinic phase ZrO.sub.2 and tetragonal phase ZrO.sub.2. In some embodiments, the high-k dielectric layer contains both tetragonal phase HfO.sub.2 and tetragonal phase ZrO.sub.2. In some embodiments, the high-k dielectric layer contains both tetragonal phase HfO.sub.2 and tetragonal phase ZrO.sub.2 and monoclinic phase HfO.sub.2 and monoclinic phase ZrO.sub.2.

(15) In some embodiments, the high-k dielectric layer consists essentially of HfO.sub.2, ZrO.sub.2, or a combination thereof. In some embodiments, the high-k dielectric layer consists of HfO.sub.2, ZrO.sub.2, or a combination thereof.

(16) In some embodiments, the high-k dielectric layer is not lanthanum-doped.

(17) The high-k dielectric layer is 10 to 40 thick (e.g., 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, or 40 thick), including any and all ranges and subranges therein. For example, in some embodiments, the high-k dielectric layer is 10 to 20 thick.

(18) In a second aspect, the invention provides a device (e.g., an electronic device) that contains the semiconductor device according to the first aspect of the invention.

(19) In a third aspect, the invention provides a method of forming a semiconductor device, said method including: forming, on a semiconductor substrate, a 10 to 40 thick dielectric layer that includes at least one of hafnium dioxide (HfO.sub.2) and zirconium dioxide (ZrO.sub.2), said dielectric layer having a continuous planar surface; after forming the dielectric layer, performing plasma deposition of an inert gas, such that the inert gas penetrates the continuous planar surface of the dielectric layer, thereby forming an inert gas impregnated dielectric layer; and after performing the plasma deposition, applying a high voltage bias to the inert gas impregnated dielectric layer, thereby forming a high-k dielectric layer that contains at least some tetragonal phase HfO.sub.2 or tetragonal phase ZrO.sub.2.

(20) The high-k dielectric layer corresponds to that described supra in accordance with the first aspect of the invention. In some embodiments, the dielectric layer is formed directly on a silicon dioxide interlayer of the semiconductor substrate. The dielectric layer may be formed using any art-acceptable techniques, which are well known to persons having ordinary skill in the art. For example, in some embodiments, the dielectric layer is formed via atomic layer deposition (ALD). In some embodiments, the dielectric layer is formed via a metal-organic chemical vapor deposition method (MOCVD), plasma-enhanced ALD (PEALD), reactive sputtering method, or an atomic layered chemical vapor deposition method (ALCVD).

(21) As used herein, continuous planar surface refers generally to an uninterrupted substantially flat surface.

(22) In some embodiments, the dielectric layer is formed directly on a silicon dioxide (SiO.sub.2) interlayer that constitutes or is contained within the semiconductor substrate.

(23) In some embodiments, the hafnium dioxide (HfO.sub.2) and/or zirconium dioxide (ZrO.sub.2) that is deposited to form the dielectric layer is in the monoclinic phase.

(24) After forming the dielectric layer, plasma deposition of an inert gas is performed. For example, in some embodiments, low energy (100-500V) is applied to generate high density plasma with a high dose of inert gas (dose>1e15). This results in the inert gas penetrating the continuous planar surface of the dielectric layer, thereby forming an inert gas impregnated dielectric layer.

(25) In some embodiments, the inert gas is selected from helium (He) and argon (Ar). After performing the plasma deposition, a high voltage bias is applied to the inert gas impregnated dielectric layer, thereby forming a high-k dielectric layer that contains at least some tetragonal phase HfO.sub.2 or tetragonal phase ZrO.sub.2. For example, the bias voltage can be applied between wafer chuck/substrate with dielectric film as anode and the process chamber wall. The process chamber may be connected to ground to generate high voltage bias, in a range of, e.g., 7 kV-15 kV, including any and all ranges and subranges therein.

(26) Without being bound to theory, it is believed that the plasma deposition of the inert gas (e.g., He) results in an oxygen deficiency within the dielectric layer during the subsequent high voltage bias, which contributes to the ready transformation of at least a portion of the metal oxide in the as-formed dielectric film (HfO.sub.2 and/or ZrO.sub.2) into tetragonal phase, which is a crystalline phase known to have a higher dielectric constant.

(27) In some embodiments, the high-k dielectric layer, as described above, contains both tetragonal phase HfO.sub.2 and tetragonal phase ZrO.sub.2.

(28) In some embodiments, the high voltage bias results in at least 50% of the HfO.sub.2 and/or ZrO.sub.2 present in the high-k dielectric being in the tetragonal phase.

(29) FIGS. 1A and 1B depict a simple schematic showing the plasma deposition and high voltage bias steps performed in accordance with an embodiment of the invention in an Applied materials Pulsed plasma (PLAD) tool. The depicted embodiments show a first He plasma step, followed by a high voltage bias step. As shown, PLAD and a high voltage bias are used to deposit an inert gas, e.g., helium, which penetrates the continuous planar surface of the dielectric layer.

(30) FIG. 2 depicts a flow chart showing an embodiment of the inventive method of forming a semiconductor device. As shown, the depicted embodiment includes process steps 100, 110, 112, 114, 116, 118, 120, 122, 124, and 126. Process step 118 (PLAD+High Voltage Bias) refers to the above-discussed steps of (i) performing plasma deposition (PLAD) of an inert gas to form the inert gas impregnated dielectric layer; and (ii) applying the high voltage bias to the inert gas impregnated dielectric layer, thereby forming a high-k dielectric layer that contains at least some tetragonal phase HfO.sub.2 or tetragonal phase ZrO.sub.2. In some embodiments, process step 118 replaces a PDA used in the prior art process of record, thereby eliminating the problem of uncontrolled IL regrowth experienced in the prior art due to additional thermal budget. In other embodiments, a PDA is optionally still performed after process step 118 (e.g., before process step 120).

(31) Methods of the invention may include, or be used together with other semiconductor fabrication processes, which are well known in the art.

EXAMPLES

(32) The invention will now be illustrated, but not limited, by reference to the specific embodiments described in the following examples.

Example 1

(33) On a blanket silicon wafer, a silicon dioxide interlayer was deposited. An 11.5 thick HfO.sub.2 high-k dielectric film was deposited directly on the SiO.sub.2 interlayer. In an ASM Eagle XP for ALD, PLAD of helium was performed, followed by application of a high voltage bias at 10 kV, thereby forming an 11.5 thick HfO.sub.2 high-k dielectric film containing both monoclinic and tetragonal phase HfO.sub.2. FIG. 3A provides a Grazing incident X-ray diffraction(GIXRD) chart for the HfO.sub.2 high-k dielectric film post PLAD and high voltage bias. As shown, HfO.sub.2 in the film was primarily monoclinic. FIG. 3E shows a corresponding capacitance vs. voltage chart for the example, evidencing no current leakage, thereby indicating that the quality of the HfO.sub.2 has been substantially improved as compared to prior art HfO.sub.2 films (see also, e.g., comparative examples below).

Example 2

(34) An HfO.sub.2 film was prepared as described in Example 1 above, then, following application of the high voltage bias, a post deposition anneal (fRTP) (1200 C. flash-RTP) was performed. FIG. 3B provides a Grazing incident X-ray diffraction chart for the HfO.sub.2 high-k dielectric film post PLAD, high voltage bias, and fRTP anneal. As shown, the peak was more pronounced, and there was significantly more tetragonal phase HfO.sub.2 present in the film as compared to Example 1. FIG. 3F shows a corresponding capacitance vs. voltage chart for the example, evidencing no current leakage, thereby indicating that the quality of the HfO.sub.2 has been substantially improved as compared to prior art HfO.sub.2 films (see also, e.g., comparative examples below).

Comparative Example 3

(35) On a blanket silicon wafer, a silicon dioxide interlayer was deposited. An 11.5 thick HfO.sub.2 high-k dielectric film was deposited directly on the SiO.sub.2 interlayer. fRTP anneal was performed to enhance densification of the HfO.sub.2. FIG. 3C provides a gradient incident X-ray diffraction chart for the HfO.sub.2 high-k dielectric film post fRTP anneal (1200 C. flash-RTP). As shown, no tetragonal phase HfO.sub.2 was detected. FIGS. 3G and 3H are corresponding charts for the comparative example. As can be seen, compared to the above inventive examples, high leakage is present. Accordingly, unlike the inventive examples (see, e.g., FIGS. 3E and 3F) no S feature is present. This is because accumulation/inversion region could not be obtained, due to higher leakage beyond the biases shown.

Comparative Example 4

(36) An HfO.sub.2 film was prepared as described in Comparative Example 3 above, except, instead of the fRTP (1200 C. flash-RTP) post-deposition anneal, a 1200 C. LSA was performed. FIG. 3D provides a gradient incident X-ray diffraction chart for the HfO.sub.2 high-k dielectric film post ms LSA anneal. As shown, no tetragonal phase HfO.sub.2 was detected. Further testing revealed that high leakage was present, and an accumulation/inversion region could not be obtained, due to the high leakage.

Comparative Example 5

(37) An HfO.sub.2 film was prepared as described in Comparative Example 3 above, except, instead of the fRTP (1200 C. flash-RTP) post-deposition anneal, a spike 900 C. anneal was performed. As was the case for Comparative Example 3, no tetragonal phase HfO.sub.2 was detected, high leakage was present, and an accumulation/inversion region could not be obtained, due to the high leakage.

(38) The above data demonstrate advantages associated with embodiments of the invention.

(39) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprise (and any form of comprise, such as comprises and comprising), have (and any form of have, such as has and having), include (and any form of include, such as includes and including), and contain (and any form contain, such as contains and containing) are open-ended linking verbs. As a result, a method or device that comprises, has, includes or contains one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that comprises, has, includes or contains one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

(40) As used herein, the terms comprising and including or grammatical variants thereof are to be taken as specifying the stated features, integers, steps or components but do not preclude the addition of one or more additional features, integers, steps, components or groups thereof. This term encompasses the terms consisting of and consisting essentially of.

(41) The phrase consisting essentially of or grammatical variants thereof when used herein are to be taken as specifying the stated features, integers, steps or components but do not preclude the addition of one or more additional features, integers, steps, components or groups thereof but only if the additional features, integers, steps, components or groups thereof do not materially alter the basic and novel characteristics of the claimed composition, device or method.

(42) Where one or more ranges are referred to throughout this specification, each range is intended to be a shorthand format for presenting information, where the range is understood to encompass each discrete point within the range as if the same were fully set forth herein.

(43) While several aspects and embodiments of the present invention have been described and depicted herein, alternative aspects and embodiments may be affected by those skilled in the art to accomplish the same objectives. Accordingly, this disclosure and the appended claims are intended to cover all such further and alternative aspects and embodiments as fall within the true spirit and scope of the invention.