Solid-state neutron detector device

Abstract

The structure and methods of fabricating a high efficiency compact solid state neutron detector based on III-Nitride semiconductor structures deposited on a substrate. The operation of the device is based on absorption of neutrons, which results in generation of free carriers.

Claims

1. A solid-state neutron detector device comprising: a layered structure, having the following layers interposed relative to one another as follows: a first contact; a capping layer; a neutron absorption layer comprising a plurality of interdigitated layers of at least two distinct materials, wherein the plurality of interdigitated layers comprises a first material layer and a second material layer, wherein the first material layer comprises lithium nitride, boron nitride, gadolinium nitride, or a combination thereof, wherein the second material layer comprises indium nitride or other materials, and wherein the first and second material layers have a lattice mismatch of no greater than about 0.4%; a graded layer; a substrate further comprising a top substrate layer; and a second contact.

2. The device of claim 1, wherein the top substrate layer is comprised of gallium nitride.

3. The device of claim 1, wherein the graded layer reduces material structure defects associated with lattice mismatch between the top substrate layer and the neutron absorption layer.

4. The device of claim 1, wherein the graded layer comprises gallium nitride, indium gallium nitride, indium nitride, or a combination thereof.

5. The device of claim 1, wherein the total thickness of the first material layer is between about 6 m to about 12 m.

6. The device of claim 1, wherein the capping layer comprises zirconium nitride, titanium nitride or other materials which prevent oxidation of the neutron absorption layer.

7. The device of claim 1, wherein the second contact is composed of a metal or combination of metals making it Ohmic to the top substrate layer.

8. The device of claim 1, wherein the neutron absorption layer and the top substrate layer form a p-n junction.

9. The device of claim 1, wherein at least one of the plurality of interdigitated layers or grading layer exhibits dielectric properties.

10. The device of claim 1, wherein all of the layers are electrically conductive.

11. A solid-state neutron detector device comprising: a layered structure, having the following layers interposed relative to one another as follows: a first contact; a capping layer; a neutron absorption layer comprising a plurality of micro- or nano- column structures of at least two distinct materials; a substrate; and a second contact.

12. The device of claim 11, wherein the substrate comprises a semiconductor silicon wafer.

13. The device of claim 12, wherein the semiconductor silicon wafer has an n-type doping concentration from about 10.sup.14 cm.sup.3 to about 10.sup.18 cm.sup.3.

14. The device of claim 11, wherein the plurality of micro- or nano- column structures comprise gadolinium, boron, lithium, or a combination thereof, and wherein the micro- or nano- column structures have a height-to-base diameter aspect ratio of at least about 1.5.

15. The device of claim 11, wherein the plurality of micro- or nano- column structures comprise doped semiconductor silicon.

16. The device of claim 11, wherein the neutron absorption layer has a p-type doping.

17. The device of claim 11, wherein the capping layer comprises zirconium nitride, titanium nitride, or other materials which prevent oxidation of the neutron absorption layer and are transparent to neutrons.

18. The device of claim 11, wherein all of the layers are electrically conductive.

19. The device of claim 11, wherein the neutron absorption layer and the substrate form a p-n junction.

20. The device of claim 11, wherein at least one of the materials of the neutron absorption layer exhibits dielectric properties.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views, and in which:

(2) FIG. 1 shows a schematic representation of GdN lattice alignment with GaN structure.

(3) FIG. 2 shows a side view in accordance with an exemplary embodiment of the present disclosure.

(4) FIG. 3 shows a side view in accordance with an exemplary embodiment of the present disclosure.

(5) FIG. 4 shows a side view SEM image of micro columns fabricated on a silicon wafer using pulsed laser ablation in accordance with an exemplary embodiment of the present disclosure.

(6) FIG. 5 shows an x-ray diffraction pattern of sputtered GdN layers.

(7) FIG. 6 shows high quality AlN and AlGaN films grown on a silicon substrate and InGaN film grown on a sapphire substrate.

(8) FIG. 7 shows x-ray data for p-n junction InGaN devices with thickness 425-450 nm and various indium compositions, along with a 570 nm In.sub.0.84Ga.sub.0.16N single layer for reference.

(9) FIG. 8 shows front illuminated photodiode structures.

(10) FIG. 9 shows back illuminated photodiode structures.

(11) FIG. 10 shows x-ray diffraction data for various sputtered layers (including ZrN) deposited on sapphire substrates.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(12) In the description that follows, like parts are marked throughout the specification and drawings with the same reference numerals. The drawing figures might not be to scale and certain components can be shown in generalized or schematic form and identified by commercial designations in the interest of clarity and conciseness.

(13) Interdigitated Layer Structure

(14) The device structure of a first exemplary embodiment is shown in FIG. 2. It consists of a high crystalline quality GaN layer (1), a graded GaN/InGaN/InN layer (2), interdigitated GdN (3) and InN (4) layers, a capping ZrN layer (5), and metal contacts to the top ZrN layer and the bottom GaN layer(6).

(15) The operation of the device is based on absorption of neutrons by the Gd atoms in the GdN layers, which results in generation of free carriers. These carriers can be collected if a p-n junction is present in the structure. For example, such p-n junction is formed if the GdN/InGaN interdigitated structure is of n-type, and the bottom GaN layer is of p-type.

(16) If all the layers in the structure are electrically conductive, but do not form a p-n junction, generated carriers will add to the current resulted from a bias applied between the two contacts in the bottom and on the top of the device structure.

(17) If any of the layers in the GaN/InGaN/InN graded layer or in the interdigitated GdN/InN exhibit dielectric properties (because, for example, of extremely low doping concentration or amorphous nature) the capacitance of the structure can be measured at a pulsed voltage applied to the contacts as a function of charge carriers generated during absorption of neutrons by Gd atoms.

(18) While using Gd isotopes will greatly benefit the device efficiency, naturally occurring Gd can be used for a proof of concept in the first embodiment. Naturally occurring Gd has a neutron capture cross-section of 49,700 barns, which is still much higher than many other materials used for neutron detection.

(19) The lattice constants of InN and GaN are 3.54 and 3.19 , respectively, which results in up to 10% lattice mismatch. In order to generate minimum defects associated with this mismatch, a graded GaN/InGaN/InN layer (2) is grown first by PAMBE on commercial templates of low defect density GaN pre-grown by MOCVD on sapphire substrates(1). Then >12 m thick heterostructure comprising of interdigitated GdN (3) and InN (4) layers(>1.2 m thick each) is grown using RF assisted DC magnetron co-sputtering, followed by the deposition of a capping ZrN layer (5). The structure is patterned, and etched by using reactive ion etching (RIE) to expose the bottom GaN layers (1) and separate pixels in the array. Metal contacts (6) are deposited then on the top of the capping layer (5) and onto the exposed GaN template layer (1) by using vacuum evaporation or sputtering.

(20) In one embodiment of the present disclosure, the capping layer, interdigitated layer, and graded layer do not alter their performance under harsh environments (unless exposed to Cl.sup.+ and/or F.sup.+ ion containing plasmas and/or temperatures above 250 C.)

(21) Method of Fabricating Interdigitated Layer Structure

(22) First the GaN on sapphire template wafer is cleaned using a standard process followed by etching in concentrated sulfuric acid, DI water rinse, and nitrogen dry, before it is loaded into the PAMBE system and a graded GaN/InGaN/InN structure is grown by using conditions optimized in our previous experiments on the growth of InGaN with high (>80%) In content. The sample then is loaded into the sputtering chamber for deposition of interdigitated InN and GdN layers.

(23) The sputtering chamber is equipped with 3 sputter guns that allow for co-sputtering. Each gun has a separate individually controlled N.sub.2 input allowing for variation of the N.sub.2 flow rate and optimization of the deposition conditions for each individual layer. The sputtering system is also equipped with a water cooled quartz crystal monitor that allows in situ monitoring of the deposition rate.

(24) The substrate is degassed in the chamber at a temperature above 800 C. and then the substrate temperature is kept at 700 C. and 500 C. during the GdN and InN depositions, respectively. The individual sputter rates and deposition parameters for of each of the materials has to be optimized by utilizing the growth conditions developed in the previous experiments.

(25) The next step requires a capping layer to prevent the GdN layer from oxidation. A recommended option is to sputter ZrN as the capping layer, since it is highly conductive, almost transparent to neutrons, and can act as a contact layer while also being a very inert material.

(26) The RIE etching is performed through a pre-patterned photoresist mask by using a mixture of chlorine and argon gases. The etch rates have to be accurately determined in order to etch mesas that will divide the active device structure on pixels and expose the bottom contact layer. Ohmic metal contacts are deposited on the exposed by RIE bottom GaN layer and the top ZrN layer by using standard vacuum evaporation or sputtering.

(27) Nano or Micro Column Structure

(28) The device structure of the second embodiment is shown in FIG. 3. It consists of a semiconductor silicon substrate (7), a nano or micro column structured Gd containing layer (8), a capping ZrN layer (5), and metal contacts to the top ZrN layer and the bottom of the silicon substrate (6).

(29) The operation of the device is based on absorption of neutrons by the Gd atoms in the nano or micro column structured Gd containing layer. After passing through almost completely transparent ZrN layer (5) the neutrons interact with the Gd atoms generating free carriers. These carriers can be collected if a p-n junction is present in the structure. For example, such p-n junction is formed if the laser ablation structured Gd containing layer is of p-type, and the semiconductor silicon substrate is of n-type.

(30) The Gd containing layer (8) is structured as an array of nano or micro columns with high height-to-width aspect ratio and density. Upon absorption of neutrons by the Gd atoms these nano or micro columns will emit scattered charged particles that can generate additional electron hole pairs resulting in the increase of the detection efficiency of the device.

(31) If all the layers in the structure are electrically conductive, but do not form a p-n junction, generated carriers will add to the current resulted from a bias applied between the two contacts in the bottom and on the top of the device structure.

(32) If any of the layers in the structure exhibit dielectric properties (because, for example, of extremely low doping concentration or amorphous nature) the capacitance of the structure can be measured at a pulsed voltage applied to the contacts as a function of charge carriers generated during absorption of neutrons by Gd atoms.

(33) Method of Fabricating Nano or Micro Column Structure

(34) First a commercial n-type doped silicon substrate with doping concentration in the range 10.sup.14-10.sup.18 cm.sup.3 is cleaned and placed in the sputtering system chamber. Then 6 interdigitated Gd and B layers (1 m thick each) are sputtered starting with Gd and ending with B on entire silicon wafer surface. Ending with a B layer protects highly oxidizing Gd during exposure to the atmosphere. The silicon wafer covered with interdigitated Gd/B layer structure is then placed in the pulsed laser ablation processing chamber. The laser ablation is performed in vacuum or argon atmosphere provided by the processing chamber gas supply system.

(35) The laser wavelength, power, pulse duration, frequency, and scanning speed are selected to produce a deep narrow groove (about 50 to 150 m deep) in the silicon with a single line scan. Then the scan overlapping distance is adjusted to produce tall ridges with overlapping consecutive scans. After processing the required area, the same number of consecutive overlapping scans is repeated in the 90 direction to produce an array of equally spaced nano or micro (depending on the laser pulse duration and frequency) columns protruding from the silicon surface and shown in FIG. 4.

(36) In one exemplary embodiment of the present disclosure, the pulsed laser ablation may implement a laser wavelength shorter than about 1.2 m, a laser pulsing frequency higher than about 3 kHz, and a laser pulse width shorter than about 1.5 s. The pulsed laser ablation may implement a laser power flux F.sub.d1.9 Mcal/s, wherein:

(37) $F_d=\left(T_m-T_a\right)\frac{\sqrt{K{C}_v}}{2\sqrt{t_p}},$
where T.sub.m1410 C.; (Si melting temperature); T.sub.a25 C.; K0.31 cal.Math.cm.sup.1 C..sup.1 (thermal conductivity of Si); p2.3296 g.Math.cm.sup.3 (density of Si); and C.sub.v1673 cal/(g- C.) (heat capacity of Si); t.sub.p0.0005 s (minimum laser pulse width).

(38) The formation of periodic arrays of nano or micro columns results from local rapid melting and solidification of the top surface layer due to the effect of thermal waves created by a large number of laser pulses and linear sample transaction. During such melting, the top interdigitated Gd/B layer materials form with silicon an alloy that contains Gd and B atoms. Therefore at least the top surface layer of nano or micro columns formed during the lased processing will have a high concentration of Gd and B atoms, which will enable efficient neutron absorption capabilities of the laser structured layer. In addition, the p-type conductivity of at least the top part of the nano or micro column surface layer will result from the over compensation of the n-type dopant in silicon by Gd and B acceptors.

(39) The next step is sputtering of ZrN on the top of nano or micro columns in order to form a window and contact layer for the neutron detector. Ohmic metal contacts are deposited then by using conventional vacuum evaporation or sputtering on the top of ZrN layer and the bottom of the silicon substrate. Similarly to the first embodiment, the device structure of the second embodiment can be fabricated as a multi-pixel device with individual pixels addressing in order to enable imaging capabilities.

(40) It should be emphasized that the above-described embodiments are merely examples of possible implementations. Many variations and modifications may be made to the above-described embodiments without departing from the principles of the present disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.

EXAMPLES

(41) Polycrystalline GdN layers by sputter deposition of Gd targets in a nitrogen plasma environment onto sapphire wafers were demonstrated. FIG. 5 shows the x-ray diffraction pattern of the sputtered GdN layers. Gd is very reactive with oxygen and oxidizes rapidly in air, thus the GdN layer was capped with a ZrN layer. While being polycrystalline, the structure is predominantly of (111) or (100) orientation.

(42) Optimization of III-Nitride growth conditions resulted in high quality films for applications in UV/IR photodetectors, solar cells, LEDs, cold cathode devices, enhancement of MCP performance, avalanche LEDs, and many other devices. FIG. 6 shows high quality AlN and AlGaN films grown on silicon, and InGaN film grown on sapphire. For the InGaN films the color variation is observed due to a different content of In in In.sub.xGa.sub.i-xN.

(43) High quality InGaN films grown using a custom built RF Plasma Assisted Molecular Beam Epitaxy (PAMBE) system have been confirmed by x-ray data shown in FIG. 7. Presence of (0002) InGaN peak is evidence of the high quality single crystalline InGaN layers with no phase separation.

(44) FIG. 8 and FIG. 9 show front and back illuminated photodiode structures, respectively. The silicon substrate was also used as a visible light passive filter in the back illuminated structures to generate the narrow band IR response shown in FIG. 10.

(45) High crystalline quality nitride layers deposited on sapphire substrates have been demonstrated by using RF assisted magnetron sputtering system equipped with high temperature substrate capability. FIG. 10 shows the X-Ray Diffraction (XRD) spectroscopy data for various (including ZrN) layers deposited by using the above method on sapphire (Al.sub.2O.sub.3) substrates.

(46) Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims.