Apparatus for delay angle compensation of flying start function

09673734 ยท 2017-06-06

Assignee

Inventors

Cpc classification

International classification

Abstract

An apparatus for delay angle compensation for flying start function in a medium-voltage inverter is disclosed. The apparatus generates generate a phase angle () by converting a three-phase voltage of an inverter output terminal to dq-axis voltages (Vd, Vq), and calculate a compensation phase angle by a predetermined delay time. In addition, the apparatus generates an initial angle for the flying start by aggregating the compensation phase angle with the phase angle (). The apparatus may drive a high-voltage motor more stably, because an error between a command voltage phase angle and an actual output voltage phase angle may be reduced, when electric power of the medium voltage inverter is restored after a trip or an instantaneous blackout occurs.

Claims

1. An apparatus for delay angle compensation for a flying start function in a medium-voltage inverter, the apparatus comprising: a signal processing unit configured, by converting a three-phase voltage of an inverter output terminal to a two-phase stationary reference frame voltage (V), to generate an AC signal (V) corresponding to a frequency applied by the inverter and an AC signal (qV) having a phase angle delayed by 90 degrees to V and to generate a reference frequency () for phase angle compensation; a phase generating unit configured to convert V and qV to dq-axis voltages (Vd, Vq) through a rotary coordinate conversion and to generate a phase angle () using Vq; and a phase compensating unit configured to calculate a compensation phase angle by multiplying by a predetermined delay time and to generate an initial angle for the flying start function by aggregating the compensation phase angle with .

2. The apparatus of claim 1, wherein the signal processing unit is further configured to: calculate a frequency error (Ef) by multiplying an error between V and V by qV; perform an integral of Ef multiplied by a certain minus value; and generate by aggregating an initial frequency (.sub.c) with the integral value.

3. The apparatus of claim 1, wherein the phase generating unit is further configured to: perform a proportional-integral of Vq; aggregate the proportional-integral value with an initial frequency (.sub.c); and generate by performing an integral of the aggregated value.

4. The apparatus of claim 1, wherein the signal processing unit is formed by using a SOGI (Second Order Generalized Integrator) and is further configured to generate V and qV according to the following transfer functions: D ( s ) = V V ( s ) = k 1 s s 2 + k 1 s + 2 ; and Q ( s ) = qV V ( s ) = k 1 s s 2 + k 1 s + 2 wherein k1 is a gain multiplied by a difference between V and V.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is an exemplary view illustrating a conventional medium-voltage inverter system.

(2) FIG. 2 is an exemplary view illustrating a structure of a power cell.

(3) FIG. 3 is an exemplary view illustrating a conventional flying start method.

(4) FIG. 4 is a view illustrating an apparatus for delay angle compensation of flying start function according to an exemplary embodiment of the present disclosure.

(5) FIG. 5 is a view illustrating a signal processing unit according to an exemplary embodiment of the present disclosure.

(6) FIG. 6 is a view illustrating a phase generating unit according to an exemplary embodiment of the present disclosure.

(7) FIG. 7 is a view illustrating a phase compensating unit according to an exemplary embodiment of the present disclosure.

(8) FIG. 8 is an exemplary view illustrating a starting point using a flying start initial angle.

DETAILED DESCRIPTION

(9) Hereinafter, referring to enclosed figures, an exemplary embodiment of the present disclosure will be described in detail.

(10) Referring to FIG. 4, an apparatus (40) for delay angle compensation of flying start function according to an exemplary embodiment of the present disclosure may include a signal processing unit (41), a phase generating unit (42), and a phase compensating unit (43). The apparatus (40) may generate an initial angle for the flying start function through phase angle compensation. The flying start initial angle does not have an error between a command voltage and an output voltage.

(11) FIG. 5 is a view illustrating a signal processing unit (41) according to an exemplary embodiment of the present disclosure. The signal processing unit (41) may be formed by using a SOGI (Second Order Generalized Integrator).

(12) The signal processing unit (41) may receive a voltage (Vabc) from an output terminal of an inverter (input terminal of a motor). The signal processing unit (41) may receive a phase voltage or a line-to-line voltage of an inverter. The signal processing unit (41) may convert the voltage (Vabc) from an output terminal of an inverter to a two-phase stationary reference frame voltage (V) using a transfer matrix (50-1, T).

(13) In addition, the signal processing unit (41) may, by using the V, generate an AC (Alternating Current) signal V corresponding to a frequency applied by the inverter and an AC signal qV having a phase angle delayed by 90 degrees to the V, and may generate a reference frequency () for phase angle compensation.

(14) Considering more particularly, the signal processing unit (41) may generate V, by multiplying a gain K1 (51-1) by a difference (Ei) between V and V, subtracting qV from the multiplied signal (51-2), multiplying the subtracted value by (51-3), and performing an integral of the multiplied value (51-4).

(15) V may become qV, by being multiplied by (52-2), after being integrated (52-1).

(16) A transfer function (D(s)) between V and V may be expressed by the following equation:

(17) D ( s ) = V V ( s ) = k 1 s s 2 + k 1 s + 2 [ Equation 1 ]

(18) In addition, a transfer function (Q(s)) between V and qV may be expressed by the following equation:

(19) Q ( s ) = qV V ( s ) = k 1 s s 2 + k 1 s + 2 [ Equation 2 ]

(20) Ef is a frequency error, which is calculated by multiplying Ei by qV (53-1).

(21) is calculated, by multiplying Ef by a negative () value (K2) (53-2, 53-3), integrating the multiplied value (53-4), and aggregating the integrated value with an initial frequency (.sub.c) (53-5).

(22) The phase generating unit (42) may convert V and qV signals to dq-axis voltages (Vd, Vq) through a rotary coordinate conversion, and may generate a phase angle () using the q-axis voltage Vq.

(23) FIG. 6 is a view illustrating a phase generating unit (42) according to an exemplary embodiment of the present disclosure. The phase generating unit (42) may be formed by using a PLL (Phase Locked Loop).

(24) A coordinate conversion unit (61) may convert V and qV signals generated from the signal processing unit (41) to dq-axis voltages (Vd, Vq), by performing a proportional-integral of V and qV signals. Subsequently, the coordinate conversion unit (61) may perform a proportional-integral (62) of the q-axis voltage qV, and may aggregate the proportional-integral value with an initial frequency (.sub.c) (63).

(25) The proportional-integral (62) may be performed according to the following Equation 3:

(26) Kp ( 1 + 1 TiSs ) , [ Equation 3 ]
where Kp is a gain, and Ti is a time constant.

(27) Henceforth, a phase angle () may be generated (64) by performing an integral of the aggregated value of an output (Vf) from the proportional-integral unit (62) and the initial frequency (.sub.c). The generated phase angle () may be fed back to the coordinate conversion unit (61) to be used for the coordinate conversion.

(28) FIG. 7 is a view illustrating a phase compensating unit (43) according to an exemplary embodiment of the present disclosure. A compensation phase angle (c) may be calculated by multiplying generated from the signal processing unit (41) by a predetermined delay time (71, 72). An initial angle () for flying start may be generated by aggregating the calculated compensation phase angle (c) with the phase angle () generated from the phase generating unit (42).

(29) At this moment, the delay occurs by a time constant of a filter or a sampling time of the system. The delay time may be predetermined in consideration of such delay factors.

(30) An error caused by the delay time may be reduced in the initial angle () generated from the phase compensating unit (43). Thus, a fast and precise flying start may be performed, and a motor inrush current may be reduced, because an output voltage equal to a phase of a command voltage may be applied.

(31) FIG. 8 is an exemplary view illustrating a starting point using a flying start initial angle. A motor residual voltage and outputs of inverters are compared to each other, when an electric power of each inverter is inputted as illustrated in FIG. 8a.

(32) When an abnormality occurs in the input power supply, a motor runs in a state of free run due to inertia, and an output of an inverter is shut off, because no voltage is applied to the motor.

(33) As illustrated in FIG. 8b, while running in a free run state, the residual voltage (counter electromotive force) of the motor may be generated for about 10 seconds in general (although may be different by types of motors).

(34) Conventionally, the flying start operation is started after waiting until the time point (t2) when the residual voltage of the motor becomes extinct, as illustrated in FIG. 8c.

(35) However, when using the apparatus (40) for delay angle compensation of flying start function according to an exemplary embodiment of the present disclosure, the flying start operation can be driven even at the time point (t1) while the residual voltage of the motor still remains, as illustrated in FIG. 8d.

(36) The exemplary embodiments described in the above are proposed in order to facilitate understanding of the present disclosure. Thus, the present disclosure is not limited by the exemplary embodiments described in the above. Therefore, it will be apparent that the persons who skilled in the art of the present disclosure may easily perform various transformed or modified embodiments within the limit of the claimed technical spirit of the present disclosure.