LED ELEMENT
20170155013 ยท 2017-06-01
Assignee
Inventors
Cpc classification
H10H20/811
ELECTRICITY
H10H20/0137
ELECTRICITY
H01L21/0262
ELECTRICITY
International classification
H01L33/00
ELECTRICITY
Abstract
An LED element is provided with: a first semiconductor layer formed of an n-type nitride semiconductor; a second semiconductor layer formed on top of the first semiconductor layer and formed of quaternary mixed crystals of Al.sub.x1Ga.sub.y1In.sub.z1N (0<x1<1, 0<y1<1, 0<z1<1 and x1+y1+z1=1); a heterostructure formed on top of the second semiconductor layer and constituted of a laminate structure of a third semiconductor layer formed of In.sub.x2Ga.sub.1-x2N (0<x2<1) having a film thickness of greater than or equal to 10 nm, and a fourth semiconductor layer formed of Al.sub.x3Ga.sub.y3In.sub.z3N (0<x3<1, 0<y3<1, 0z3<1 and x3+y3+z3=1); and a fifth semiconductor layer formed on top of the heterostructure and formed of a p-type nitride semiconductor.
Claims
1. An LED element comprising: a first semiconductor layer formed of an n-type nitride semiconductor; a second semiconductor layer formed on top of the first semiconductor layer, and formed of quaternary mixed crystals of Al.sub.x1Ga.sub.y1In.sub.z1N (0<x1<1, 0<y1<1, 0<z1<1, x1+y1+z1=1); a heterostructure formed on top of the second semiconductor layer, and constituted of a laminate structure of a third semiconductor layer formed of In.sub.x2Ga.sub.1-x2N (0<x2<1) having a film thickness of greater than or equal to 10 nm, and a fourth semiconductor layer formed of Al.sub.x3Ga.sub.y3In.sub.z3N (0<x3<1, 0<y3<1, 0z30.05, x3+y3+z3=1); and a fifth semiconductor layer formed on top of the heterostructure and formed of a p-type nitride semiconductor, wherein the peak emission wavelength is greater than or equal to 362 nm and less than or equal to 395 nm, and the first semiconductor layer, the second semiconductor layer, the heterostructure, and the fifth semiconductor layer are laminated in the c-axis direction.
2. The LED element according to claim 1, wherein the film thickness of the third semiconductor layer is less than or equal to 25 nm.
3. The LED element according to claim 1, wherein the heterostructure is made up of repeated multiple periods of the third semiconductor layer and the fourth semiconductor layer.
4. The LED element according to claim 1, wherein the fourth semiconductor layer is formed of Al.sub.x3Ga.sub.1-x3N (0<x3<1).
5. The LED element according to claim 1, wherein the fourth semiconductor layer is formed of quaternary mixed crystals of Al.sub.x3Ga.sub.y3In.sub.z3N (0<x3<1, 0<y3<1, 0z30.05, x3+y3+z3=1).
6. (canceled)
7. The LED element according to claim 1, wherein the film thickness of the second semiconductor layer is greater than or equal to 10 nm and less than or equal to an critical film thickness.
8. The LED element according to claim 2, wherein the heterostructure is made up of repeated multiple periods of the third semiconductor layer and the fourth semiconductor layer.
9. The LED element according to claim 2, wherein the fourth semiconductor layer is formed of Al.sub.x3Ga.sub.1-x3N (0<x3<1).
10. The LED element according to claim 3, wherein the fourth semiconductor layer is formed of Al.sub.x3Ga.sub.1-x3N (0<x3<1).
11. The LED element according to claim 8, wherein the fourth semiconductor layer is formed of Al.sub.x3Ga.sub.1-x3N (0<x3<1).
12. The LED element according to claim 2, wherein the fourth semiconductor layer is formed of quaternary mixed crystals of Al.sub.x3Ga.sub.y3In.sub.z3N (0<x3<1, 0<y3<1, 0z30.05, x3+y3+z3=1).
13. The LED element according to claim 3, wherein the fourth semiconductor layer is formed of quaternary mixed crystals of Al.sub.x3Ga.sub.y3In.sub.z3N (0<x3<1, 0<y3<1, 0z30.05, x3+y3+z3=1).
14. The LED element according to claim 8, wherein the fourth semiconductor layer is formed of quaternary mixed crystals of Al.sub.x3Ga.sub.y3In.sub.z3N (0<x3<1, 0<y3<1, 0z30.05, x3+y3+z3=1).
15. The LED element according to claim 2, wherein the film thickness of the second semiconductor layer is greater than or equal to 10 nm and less than or equal to an critical film thickness.
16. The LED element according to claim 3, wherein the film thickness of the second semiconductor layer is greater than or equal to 10 nm and less than or equal to an critical film thickness.
17. The LED element according to claim 4, wherein the film thickness of the second semiconductor layer is greater than or equal to 10 nm and less than or equal to an critical film thickness.
18. The LED element according to claim 5, wherein the film thickness of the second semiconductor layer is greater than or equal to 10 nm and less than or equal to an critical film thickness.
19. The LED element according to claim 8, wherein the film thickness of the second semiconductor layer is greater than or equal to 10 nm and less than or equal to an critical film thickness.
20. The LED element according to claim 9, wherein the film thickness of the second semiconductor layer is greater than or equal to 10 nm and less than or equal to an critical film thickness.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0042]
[0043]
[0044]
[0045]
[0046]
[0047]
[0048]
[0049]
[0050]
[0051]
[0052]
[0053]
[0054]
MODE FOR CARRYING OUT THE INVENTION
[0055] [Structure]
[0056]
[0057] A LED element 1 has an undoped layer 13 on top of a growth substrate 11 of sapphire or the like, and a first semiconductor layer 15 formed of an n-type nitride semiconductor on top of the undoped layer 13. The first semiconductor layer 15 constitutes an n-type cladding layer.
[0058] The LED element 1 further has, on top of the first semiconductor layer 15, a second semiconductor layer 5 formed of quaternary mixed crystals of Al.sub.x1Ga.sub.y1In.sub.z1N (0<x1<1, 0<y1<1, 0<z1<1, x1+y1+z1=1). The LED element 1 also has, on top of the second semiconductor layer 5, a heterostructure 2 made up of a laminate structure of a third semiconductor layer 3 formed of In.sub.x2Ga.sub.1-x2N (0<x2<1), and a fourth semiconductor layer 4 formed of Al.sub.x3Ga.sub.y3In.sub.z3N (0<x3<1, 0<y3<1, 0 z3<1, x3+y3+z3=1).
[0059] The LED element 1 further has, on top of the heterostructure 2, a fifth semiconductor layer 19 formed of a p-type nitride semiconductor. The fifth semiconductor layer 19 constitutes a p-type cladding layer. The LED element 1 shown in
[0060] (Growth Substrate 11)
[0061] The growth substrate 11 is constituted of a sapphire substrate. The growth substrate 11 may be formed of Si, SiC, GaN, YAG or the like besides sapphire.
[0062] (Undoped Layer 13)
[0063] The undoped layer 13 is formed of GaN. More specifically, the undoped layer 13 is formed of a low-temperature buffer layer formed of GaN, and an under layer formed of GaN on top of the low-temperature buffer layer.
[0064] (First Semiconductor Layer 15)
[0065] The first semiconductor layer 15 is formed of an n-AlGaN in this embodiment, and is doped with Si, Ge, S, Se, Sn, Te or the like as an n-type impurity. A layer formed of n-GaN (protective layer) may be contained in the region being in contact with the undoped layer 13. In this case, the protective layer is doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te, and is particularly preferably doped with Si. In the present embodiment, as one example, the first semiconductor layer 15 is formed of n-Al.sub.0.1Ga.sub.0.9N.
[0066] The first semiconductor layer 15 may be formed of n-GaN.
[0067] (Fifth Semiconductor Layer 19)
[0068] The fifth semiconductor layer 19 is formed of p-AlGaN in the present embodiment, and is doped with a p-type impurity such as Mg, Be, Zn, or C. In the present embodiment, as one example, the fifth semiconductor layer 19 is formed by a laminate structure of p-Al.sub.0.3Ga.sub.0.7N and p-Al.sub.0.07Ga.sub.0.93N. A layer formed of GaN (protective layer) may be contained in the region being in contact with the p-type contact layer 21. In this case, the protective layer may be doped with a p-type impurity such as Mg, Be, Zn, or C.
[0069] (P-Type Contact Layer 21)
[0070] The p-type contact layer 21 is formed, for example, of p-GaN. In particular, doping with a high concentration of a p-type impurity such as Mg, Be, Zn, or C results in the p-type contact layer 21 constituted of a p.sup.+-GaN layer.
[0071] (Second Semiconductor Layer 5)
[0072] The second semiconductor layer 5 is formed of quaternary mixed crystals of Al.sub.x1Ga.sub.y1In.sub.z1N (0<x1<1, 0<y1<1, 0<z1<1, x1+y1+z1=1). In the present embodiment, description will be made for the exemplary case where the second semiconductor layer 5 is formed of Al.sub.0.06Ga.sub.0.92In.sub.0.02N having a film thickness of 20 nm.
[0073] (Heterostructure 2)
[0074] As described above, the heterostructure 2 is constituted of a laminate structure of the third semiconductor layer 3 formed of In.sub.x2Ga.sub.1-x2N (0<x2<1), and the fourth semiconductor layer 4 formed of Al.sub.x3Ga.sub.y3In.sub.z3N (0<x3<1, 0<y3<1, 0 z3<1, x3+y3+z3=1). In the present embodiment, the heterostructure 2 constitutes an active layer of the LED element 1. That is, the third semiconductor layer 3 formed of In.sub.x2Ga.sub.1-x2N constitutes a light emitting layer, and the fourth semiconductor layer 4 formed of Al.sub.x3Ga.sub.y3In.sub.z3N constitutes a barrier layer.
[0075] In the present embodiment, description will be made for the exemplary case where the third semiconductor layer 3 is formed of In.sub.0.02Ga.sub.0.98N having a film thickness of 15 nm, and the fourth semiconductor layer 4 is formed of n-Al.sub.0.06Ga.sub.0.94N having a film thickness of 20 nm.
[0076] By the way, the active layer 94 provided in the conventional LED element 1 shown in
[0077] On the other hand, in the LED element 1, the second semiconductor layer 5 formed of Al.sub.x1Ga.sub.y1In.sub.z1N constitutes the first barrier layer (first barrier) on the n-side. In comparison with the second semiconductor layer 5 formed of Al.sub.x1Ga.sub.y1In.sub.z1N, and the fourth semiconductor layer 4 formed of Al.sub.x3 Ga.sub.y3In.sub.z3N, the band gap of the third semiconductor layer 3 formed of In.sub.x2Ga.sub.1-x2N is small. Therefore, the second semiconductor layer 5 and the fourth semiconductor layer 4 constitute a barrier layer, and the third semiconductor layer 3 constitutes a light emitting layer.
[0078] As shown in
[0079] In the LED element 1 shown in
[0080] While
[0081] In place of the configuration of
[0082] [Description of Function of Heterostructure 2]
[0083] Hereinafter, improvement in emission efficiency in the LED element 1 compared with the conventional LED element 90 by having the heterostructure 2 of the aforementioned configuration will be described by referring to Examples. In the following description, description will be made on the assumption that the In composition contained in the fourth semiconductor layer formed of Al.sub.x3Ga.sub.y3In.sub.z3N is 0% (namely z3=0). However, the same discussion is applicable also when the fourth semiconductor layer is formed of Al.sub.x3Ga.sub.y3In.sub.z3N containing 5% or less of In.
[0084] In the following description, as the LED element 90 used for comparative verification, the one formed by alternately laminating InGaN having a film thickness of 2 nm and AlGaN having a film thickness of 5 nm periodically five times was employed as the active layer 94 formed by a MQW.
[0085] (Discussion about Peak Emission Wavelength)
[0086]
[0087] Here, as the LED element 1, the configuration having the second semiconductor layer 5 formed of Al.sub.0.08Ga.sub.0.91In.sub.0.01N having a film thickness of 15 nm on top of the first semiconductor layer 15 which is an n-type semiconductor layer, and having the multilayer structure part 2A on top of the second semiconductor layer 5 is employed. The multilayer structure part 2A is formed by periodically repeating five times the heterostructure 2 made up of the third semiconductor layer 3 formed of In.sub.0.92Ga.sub.0.98N having a film thickness of 15 nm, and the fourth semiconductor layer 4 formed of n-Al.sub.0.06Ga.sub.0.94N having a film thickness of 20 nm.
[0088] For comparison,
[0089] In
[0090] According to
[0091]
[0092] AlGaN has a larger band gap than InGaN. Therefore, as shown in
[0093] Here, as previously mentioned, the film thickness of the third semiconductor layer 3 (InGaN) is 15 nm in the present example, which is much larger than 2 nm which is the film thickness of InGaN forming the active layer 94 of the conventional LED element 90. Therefore, in the region of the third semiconductor layer 3, the substantially flat band region is broadly formed.
[0094] In the LED element 1, piezoelectric polarization (piezo polarization) arises in the c-axis direction which is perpendicular to the plane of the flat band region formed by the third semiconductor layer 3 (InGaN).
[0095] As the distortion of the energy band increases, overlapping between the wave function of an electron and the wave function of a hole reduces, and the rate of light emission caused by recombination an electron and a hole reduces. This is called a quantum Stark effect. The distortion increases as the In composition ratio of the third semiconductor layer 3 (InGaN) increases. The reduction in the light output in the LED element 1 having a peak emission wavelength of greater than or equal to 400 nm as compared with the conventional LED element 90 would be ascribable to emergence of the quantum Stark effect due to the high In composition ratio. Also the aforementioned influence of the misfit dislocation resulting from the difference in the lattice constant would be unignorable.
[0096] On the other hand, for realizing the light having a peak emission wavelength of 357 nm that is lower than 360 nm, it is necessary to set the In ratio of the third semiconductor layer 3 (InGaN) to be extremely small. In the case of the conventional LED element 90, since the film thickness of InGaN forming the active layer 94 is about 2 nm, a small amount of In can be added, and an optimum In ratio for realizing the light of such a short wavelength can be realized. In the LED element 1 containing the third semiconductor layer 3 (InGaN) having a film thickness of 15 nm, however, the content of In is high for the larger film thickness of the third semiconductor layer 3 (InGaN), and it is difficult to realize the light of the short wavelength around 357 nm. Accordingly, when LED elements having a peak emission wavelength of 357 nm are realized, the light output is higher in the conventional LED element 90 than in the LED element 1.
[0097] On the other hand, in the range D1 where the peak emission wavelength is greater than or equal to 362 nm and less than or equal to 395 nm, the light output is higher in the LED element 1 of the present invention than in the conventional LED element 90. The conceivable reason for this is as follows.
[0098] As shown in
[0099]
[0100] These reveal that according to the configuration of the LED element 1, the effect of improving the light output than before is obtained particularly in the range where the peak emission wavelength is greater than or equal to 362 nm and less than or equal to 395 nm.
[0101] As described above by referring to
[0102] According to
[0103] (Discussion about Second Semiconductor Layer 5)
[0104] As described above by referring to
[0105] By the way, as described above by referring to
[0106] Therefore, it is expected that piezoelectric polarization that is higher than that of the conventional MQW occurs in the heterostructure 2 formed by growing InGaN having a larger film thickness than that of the conventional MQW. For relaxing the piezoelectric polarization, the LED element 1 of the present invention has the second semiconductor layer 5 formed of quaternary mixed crystals of Al.sub.x1Ga.sub.y1In.sub.z1N between the first semiconductor layer 15 and the heterostructure 2. Since the second semiconductor layer 5 is constituted of a semiconductor layer containing In, the lattice constant of the second semiconductor layer 5 approximates to the lattice constant of the third semiconductor layer 3 formed of InGaN. That is, by growing the second semiconductor layer 5, it is possible to weaken the internal field to the third semiconductor layer 3 to be grown thereon.
[0107]
[0108] The LED element 1 of Example 1 has such a structure that on top of the second semiconductor layer 5 formed of Al.sub.0.08Ga.sub.0.905In.sub.0.015N having a film thickness of 50 nm, the heterostructure 2 made up of the third semiconductor layer 3 formed of In.sub.0.015Ga.sub.0.985N having a film thickness of 15 nm and the fourth semiconductor layer 4 formed of n-Al.sub.0.08Ga.sub.0.92N having a film thickness 20 nm is periodically laminated five times.
[0109] The LED element 1 of Example 2 has such a structure that on top of the second semiconductor layer 5 formed of Al.sub.0.08Ga.sub.0.905In.sub.0.015N having a film thickness of 20 nm, the heterostructure 2 made up of the third semiconductor layer 3 formed of In.sub.0.015Ga.sub.0.985N having a film thickness of 15 nm, and the fourth semiconductor layer 4 formed of n-Al.sub.0.08Ga.sub.0.905In.sub.0.015N having a film thickness of 20 nm is periodically laminated five times. In other words, Example 2 is different from Example 1 in that every fourth semiconductor layer 4 is constituted of a layer of quaternary mixed crystals of AlGaInN.
[0110] The LED element of Reference example is different from the LED element 1 of Example 1 in that it does not have the second semiconductor layer 5. That is, directly on the first semiconductor layer 15, the heterostructure 2 made up of the third semiconductor layer 3 formed of In.sub.0.015Ga.sub.0.985N having a film thickness of 15 nm and the fourth semiconductor layer 4 formed of n-Al.sub.0.08Ga.sub.0.92N having a film thickness 20 nm is periodically laminated five times.
[0111] The LED element 90 of the Conventional example has the active layer 94 made up of a well layer formed of In.sub.0.02Ga.sub.0.98N having a film thickness of 2 nm and a barrier layer formed of n-Al.sub.0.08Ga.sub.0.92N having a film thickness of 5 nm periodically repeated five times, directly on the n-type cladding layer 93.
[0112]
[0113] As described above, by having the heterostructure 2, it is possible to realize the current spreading in the horizontal direction as compared with the conventional LED element 90. This also emerges as the improvement in light output in the element of Reference example than in the element of Conventional example in
[0114] Then according to
[0115] Further, according to
[0116]
[0117] According to
[0118] The In composition of the second semiconductor layer 5 formed of Al.sub.x1Ga.sub.y1In.sub.z1N, namely the Z1 value, and the value of the film thickness of the second semiconductor layer 5 depend on the peak emission wavelength, namely the X2 value of the third semiconductor layer 3 formed of In.sub.x2Ga.sub.1-x2N. Since the internal field caused by the difference in the lattice constant increases as the X2 value increases, it is preferred to increase the Z1 value or increase the film thickness of the second semiconductor layer 5 for relaxing the internal field. On the other hand, when the Z1 value is too large, a crystal defect arises during growth, and thus the second semiconductor layer 5 cannot be stacked thickly.
[0119] Therefore, the second semiconductor layer 5 preferably has an In composition corresponding to the In composition of the third semiconductor layer 3 and has a film thickness (film thickness less than or equal to the critical film thickness) within the range where a crystal defect does not arise. For example, when the In composition of the second semiconductor layer 5 is 10%, it is preferred that the film thickness is greater than 0 nm and less than or equal to 50 nm.
[0120] (Discussion about Film Thickness of Third Semiconductor Layer 3)
[0121] As described above, since the third semiconductor layer 3 (InGaN) forms the substantially flat band region 42, it is preferred to make the film thickness of the third semiconductor layer 3 large in order to improve the ability to accumulate electrons. However, when the film thickness of the third semiconductor layer 3 is too large, lattice relaxation occurs due to the difference in the lattice constant between GaN and InGaN, with the result that it becomes impossible to accumulate electrons adequately in the band bending region 41 and the substantially flat band region 42.
[0122]
[0123] According to
[0124] In contrast to this, in a region D3 where the film thickness is greater than or equal to 6 nm, the light output starts rising as the film thickness of the third semiconductor layer 3 becomes large again, and peaks when the film thickness is about 15 nm, and the light output starts reducing as the film thickness becomes larger than about 15 nm. The region D3 is considered as being within the range of film thickness where light emission is promoted by the quantum effect utilizing the band bending region 41 in the heterojunction boundary between the third semiconductor layer 3 and the fourth semiconductor layer 4.
[0125] According to
[0126] When the film thickness of the third semiconductor layer 3 is extremely small, inclination is formed also in the substantially flat band region 42 due to the large influence by the internal field as described above, and the ability to accumulate electrons is reduced. In contrast to this, when the film thickness is made as large as 15 nm, the flat band region 42 extends, and the ability to accumulate electrons increases. Electrons having a potential exceeding the Fermi level (32, 33) flow into the p-layer side (right in
[0127] The foregoing reveals that by setting the film thickness of the third semiconductor layer 3 to be greater than or equal to 10 nm and less than or equal to 25 nm, the effect of further improving the light output of the LED element 1 can be obtained.
[0128] Further, as in the LED element 1 of the present invention, by setting the film thickness of the third semiconductor layer 3 to be larger than that of the InGaN layer provided in the conventional LED element 90, the pressure resistance characteristics of the pressure LED element itself against ESD is improved, and the effect of improving the yield is obtained.
[0129] For each LED element of Example 1, Example 2, Reference example, and Comparative example, after applying the forward voltage and the reverse voltage of 500V, the reverse current flowing when 5 V was added as a reverse bias was measured. At this time, the yield was measured while the element showing an absolute value of the reverse current of less than or equal to (less than) 5 A was regarded as a good element, and the element showing an absolute value of the reverse current of greater than 5 A was regarded as a no-good element.
[0130] According to
[0131] As described above, the third semiconductor layer 3 (InGaN) provided in each of the respective LED elements of Example 1, Example 2, and Reference example has a higher film thickness than the InGaN layer provided in the MQW of the LED element of Conventional example. As the film thickness of the InGaN layer increases in this manner, a two-dimensional electron gas layer is more likely to arise between the third semiconductor layer 3 (InGaN) and the fourth semiconductor layer 4 (AlGaN). As described above, the two-dimensional electron gas layer has the function of spreading the current in the horizontal direction, and in association with this, the current is less likely to concentrate in a narrow region, and the electric field is relaxed. As a result of this, even when high voltage is applied instantaneously, the electric field is less likely to concentrate as a result of diffusion of the electric field in the heterostructure 2, and thus destruction of the element is less likely to occur.
[0132] The improvement in the yield in the LED elements of Example 1 and Example 2 compared with the LED element of Reference example would be ascribable to the fact that diffusion of a p-type impurity with which the fifth semiconductor layer 19 (p-type semiconductor layer) is doped into the third semiconductor layer 3 is suppressed due to decrease in the diameter of the V-shaped defect formed in the third semiconductor layer 3 (InGaN) caused by lattice mismatch.
[0133] In the above embodiments, the description was made for the case where the heterostructure 2 is formed directly on top of the second semiconductor layer 5. However, in the semiconductor light emitting element 1, also when the heterostructure 2 is formed on the upper face of the second semiconductor layer 5 with a nitride semiconductor layer having a very small film thickness interposed therebetween, the function as with the above can be realized. The present invention is not intended to exclude such a configuration.
[0134] [Method for Producing LED Element 1]
[0135] Next, one exemplary method for producing the LED element 1 of the present invention will be described. The production conditions and the dimensions such as a film thickness described in the following production method are merely examples, and the present invention is not limited to these numerical values. The exemplary production method shown below concerns the LED element shown in
[0136] <Step S1>
[0137] First, on top of the growth substrate 11, the undoped layer 13 is formed. For example, this is achieved by the following steps.
[0138] (Preparation of Growth Substrate 11)
[0139] When the sapphire substrate is used as the growth substrate 11, cleaning of the c-plane sapphire substrate is conducted. More specifically, this cleaning is conducted by placing the c-plane sapphire substrate in a processing furnace of, for example, MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and elevating the temperature within the temperature to, for example, 1150 C. while a hydrogen gas is flown at a flow rate of 10 slm in the processing furnace.
[0140] (Formation of Undoped Layer 13)
[0141] Next, on the surface of the growth substrate 11 (c-plane sapphire substrate), the low temperature buffer layer formed of GaN is formed, and the underlayer formed of GaN is formed on top of the low temperature buffer layer. These low temperature buffer layer and underlayer correspond to the undoped layer 13.
[0142] A more specific method for producing the undoped layer 13 is as follows. First, the pressure within the furnace of the MOCVD apparatus is set to be 100 kPa, and the temperature within the furnace is set to be 480 C. Then while a nitrogen gas and a hydrogen gas each at a flow rate of 5 slm are flown as carrier gases in the processing furnace, trimethylgallium (TMG) at a flow rate of 50 mol/min, and ammonia at a flow rate of 250000 mol/min are fed as source gases into the processing furnace for 68 seconds. By this process, on the surface of the growth substrate 11, a low temperature buffer layer formed of GaN having a thickness of 20 nm is formed.
[0143] Next, the temperature within the furnace of the MOCVD apparatus is elevated to 1150 C. Then, while a nitrogen gas at a flow rate of 20 slm and a hydrogen gas at a flow rate of 15 slm are flown as carrier gases in the processing furnace, TMG at a flow rate of 100 mol/min, and ammonia at a flow rate of 250000 mol/min are fed as source gases into the processing furnace for 30 minutes. By this process, on the surface of the low temperature buffer layer, an underlayer formed of GaN having a thickness of 1.7 m is formed.
[0144] <Step S2>
[0145] Next, on top of the undoped layer 13, the first semiconductor layer 15 formed of an n-type nitride semiconductor is formed.
[0146] A more specific method for forming the first semiconductor layer 15 is, for example, as follows. The pressure within the furnace of the MOCVD apparatus is set to be 30 kPa. Then, while a nitrogen gas at a flow rate of 20 slm and a hydrogen gas at a flow rate of 15 slm are flown as carrier gases in the processing furnace, TMG at a flow rate of 94 mol/min, trimethylaluminum (TMA) at a flow rate of 6 mol/min, ammonia at a flow rate of 250000 mol/min, and tetraethylsilane at a flow rate of 0.025 mol/min are fed as source gases into the processing furnace for 30 minutes. By this process, on top of the undoped layer 13, a high concentration electron supply layer having a composition of Al.sub.0.06Ga.sub.0.04N, and a Si concentration of 310.sup.19/cm.sup.3 and a thickness of 1.7 m is formed. In other words, at least in the region of the upper face, the first semiconductor layer 15 formed of n-AlGaN having a high concentration electron supply layer having a Si concentration of 310.sup.19/cm.sup.3 and a thickness of 1.7 m is formed by this step.
[0147] While the case of using Si as the n-type impurity contained in the first semiconductor layer 15 was described, Ge, S, Se, Sn, Te or the like may be used. Among these, Si is particularly preferred.
[0148] <Step S3>
[0149] Next, on top of the first semiconductor layer 15, the second semiconductor layer 5 formed of quaternary mixed crystals of Al.sub.x1Ga.sub.y1In.sub.z1N (0<x1<1, 0<y1<1, 0<z1<1, x1+y1+z1=1) is formed. A more specific method for forming the second semiconductor layer 5 is, for example, as follows.
[0150] The pressure within the furnace of the MOCVD apparatus is set to be 100 kPa, and the temperature within the furnace is set to be 830 C. Then, the step of feeding TMG at a flow rate of 10 mol/min, TMA at a flow rate of 1.6 mol/min, trimethylindium (TMI) at a flow rate of 12 mol/min and ammonia at a flow rate of 300000 mol/min as source gases into the processing furnace for 480 seconds while flowing a nitrogen gas at a flow rate of 15 slm and a hydrogen gas at a flow rate of 1 slm as carrier gases in the processing furnace is conducted. By this process, the second semiconductor layer 5 formed of Al.sub.0.06Ga.sub.0.02In.sub.0.02N having a film thickness of 20 nm is formed.
[0151] The second semiconductor layer 5 preferably has a film thickness of greater than or equal to 5 nm and less than 500 nm, more preferably has a film thickness of greater than or equal to 5 nm and less than 200 nm, and further preferably has a film thickness of greater than or equal to 5 nm and less than 100 nm.
[0152] <Step S4>
[0153] Next, on top of the second semiconductor layer 5, the heterostructure 2 constituted of a laminate structure of the third semiconductor layer 3 formed of In.sub.x2Ga.sub.1-x2N (0<x2<1), and the fourth semiconductor layer 4 formed of Al.sub.x3Ga.sub.y3In.sub.z3N (0<x3<1, 0<y3<1, 0 z3<1, x3+y3+z3=1) is formed.
[0154] A more specific method for forming the heterostructure 2 is, for example, as follows. A step of feeding TMG at a flow rate of 10 mol/min, TMI at a flow rate of 12 mol/min, and ammonia at a flow rate of 300000 mol/min as source gases into the processing furnace for 360 seconds while maintaining the pressure and the temperature within the furnace of the MOCVD apparatus employed in step S3, and flowing a nitrogen gas at a flow rate of 15 slm and a hydrogen gas at a flow rate of 1 slm as carrier gases in the processing furnace is conducted. Thereafter, a step of feeding TMG at a flow rate of 10 mol/min, TMA at a flow rate of 1.6 mol/min, tetraethylsilane at a flow rate of 0.009 mol/min and ammonia at a flow rate of 300000 mol/min into the processing furnace for 360 seconds is conducted. By this process, the heterostructure 2 constituted of a laminate structure of the fourth semiconductor layer 4 formed of In.sub.0.02Ga.sub.0.98N having a film thickness of 15 nm, and the third semiconductor layer 3 formed of n-Al.sub.0.06Ga.sub.0.94N having a film thickness of 20 nm is formed.
[0155] A configuration having multiple periods of the heterostructure 2 as shown in
[0156] The third semiconductor layer 3 formed of AlGaInN as in the aforementioned LED element of Example 2 can be realized by adding TMI as a source gas in forming the third semiconductor layer 3.
[0157] <Step S5>
[0158] Next, on top of the heterostructure 2 (the heterostructure 2 situated at the uppermost layer when having multiple periods of the heterostructure 2), the fifth semiconductor layer 19 formed of p-AlGaN is formed, and on top of the fifth semiconductor layer 19, the p-type contact layer 21 doped with a p-type impurity at high concentration is formed.
[0159] A more specific method for forming the fifth semiconductor layer 19 and the p-type contact layer 21 is, for example, as follows. First, the pressure within the furnace of the MOCVD apparatus is maintained at 100 kPa, and the temperature within the furnace is elevated to 1050 C. while a nitrogen gas at a flow rate of 15 slm and a hydrogen gas at a flow rate of 25 slm are flown as carrier gases in the processing furnace. Then as source gases, TMG at a flow rate of 35 mol/min, TMA at a flow rate of 20 mol/min, ammonia at a flow rate of 250000 mol/min, and bis(cyclopentadienyl)magnesium (Cp.sub.2Mg) at a flow rate of 0.1 mol/min are fed in the processing furnace for 60 seconds. By this process, on the surface of the uppermost layer of the heterostructure 2, a hole supply layer having a thickness of 20 nm and a composition of Al.sub.0.3Ga.sub.0.7N is formed. Thereafter, by feeding the source gases for 360 seconds while the flow rate of TMA is changed to 9 mol/min, a hole supply layer having a thickness of 120 nm and a composition of Al.sub.0.07Ga.sub.0.93N is formed. These hole supply layers form the fifth semiconductor layer 19.
[0160] Thereafter, the source gases are fed for 20 seconds while feeding of TMA is stopped, and the flow rate of Cp.sub.2Mg is changed to 0.2 mol/min. By this process, the p-type contact layer 21 formed of p-GaN having a thickness of 5 nm is formed.
[0161] While the case of using Mg as a p-type impurity contained in the fifth semiconductor layer 19 and the p-type contact layer 21 is described herein, Be, Zn, C and the like can also be used.
[0162] <Step S6>
[0163] Next, an activation process is carried out on the wafer obtained through the steps S1 to S5. More specifically, an activation process of 15 minutes at 650 C. in a nitrogen atmosphere is carried out using an RTA (Rapid Thermal Anneal: rapid heating) apparatus.
[0164] Subsequently, in the case of realizing a vertically-structured LED element, an electrode formed of a predetermined material (p-side electrode) is formed on the upper face of the p-type contact layer 21, and after peeling off the growth substrate 11, an electrode is formed in the site where the growth substrate 11 was present to form an n-side electrode. In the case of realizing a horizontally-structured LED element, etching is conducted from the p-side until the first semiconductor layer 15 is exposed, and on the upper face of the exposed first semiconductor layer 15, an n-side electrode is formed, and a p-side electrode is formed on the upper face of the p-type contact layer 21. In this case, an electrode such as a transparent electrode may be formed as necessary. Thereafter, each electrode is formed with a power feeding terminal or the like, and the exposed lateral faces and upper face of the element are covered with an insulating layer having high translucency, and connection with the substrate is conducted by wire bonding or the like.
Other Embodiment
[0165] In the aforementioned embodiment, the description was made for the case where the heterostructure 2 is formed directly on the second semiconductor layer 5. However, a nitride semiconductor layer constituted of a thin film having a film thickness of about several nanometers may be formed between the second semiconductor layer 5 and the heterostructure 2. Even when such a nitride semiconductor layer is interposed between the second semiconductor layer 5 and the heterostructure 2, the effect of suppressing the internal field in the heterostructure 2 is realized by having the second semiconductor layer 5.
DESCRIPTION OF REFERENCE SIGNS
[0166] 1: LED element [0167] 2: heterostructure [0168] 2A: multilayer structure part [0169] 3: third semiconductor layer [0170] 4: fourth semiconductor layer [0171] 5: second semiconductor layer [0172] 11: growth substrate [0173] 13: undoped layer [0174] 15: first semiconductor layer [0175] 19: fifth semiconductor layer [0176] 21: p-type contact layer [0177] 30: conduction band [0178] 31: valance band [0179] 32: Fermi level of InGaN [0180] 33: Fermi level of AlGaN [0181] 41: band bending region in the boundary between AlGaN and InGaN [0182] 42: substantially flat band region of InGaN [0183] 90: conventional LED element [0184] 91: growth substrate [0185] 92: undoped layer [0186] 93: n-type cladding layer [0187] 94: active layer made up of MQW [0188] 95: p-type cladding layer [0189] 96: p-type contact layer [0190] 99: tensile stress [0191] 101: conduction band [0192] 102: valance band