GALLIUM OXIDE SEMICONDUCTOR STRUCTURE, VERTICAL GALLIUM OXIDE-BASED POWER DEVICE, AND PREPARATION METHOD

Abstract

The present disclosure provides a gallium oxide semiconductor structure, a vertical gallium oxide-based power device, and a preparation method. An unintentionally doped gallium oxide layer (110) is transferred to a highly doped and highly thermally conductive heterogeneous substrate (200) by bonding and thinning; then a heavily doped gallium oxide layer (120) is formed on the gallium oxide layer by treating and ion implantation, thereby preparing the gallium oxide semiconductor structure including the heterogeneous substrate (200), the gallium oxide layer (110), and the heavily doped gallium oxide layer (120) stacked in sequence. In the vertical gallium oxide-based power device prepared on the basis of the gallium oxide semiconductor structure, the gallium oxide layer (110) is a thicker intermediate layer and a carrier concentration of the gallium oxide layer (110) is less than that of the heavily doped gallium oxide layer (120). Therefore, the breakdown voltage of the device is also increased through structural design. The highly thermally conductive heterogeneous substrate (200) improves the heat dissipation performance of the device. The device with multiple Fin structures provides a large amount of current.

Claims

1. A method for preparing a gallium oxide semiconductor structure, comprising the following steps: providing a gallium oxide single crystal wafer, wherein a surface of the gallium oxide single crystal wafer is a polished surface; providing a heterogeneous substrate, wherein a surface of the heterogeneous substrate is a polished surface; bonding the polished surface of the gallium oxide single crystal wafer to the polished surface of the heterogeneous substrate; thinning the gallium oxide single crystal wafer to obtain a composite structure comprising the heterogeneous substrate and the gallium oxide layer stacked in sequence; treating a top surface of the gallium oxide layer, wherein the top surface of the gallium oxide layer is facing away from the polished surface of the heterogeneous substrate; and forming a heavily doped gallium oxide layer on the top surface of the gallium oxide layer by performing an ion implantation on the gallium oxide layer, thereby obtaining the gallium oxide semiconductor structure comprising the heterogeneous substrate, the gallium oxide layer, and the heavily doped gallium oxide layer stacked in sequence.

2. The method for preparing a gallium oxide semiconductor structure according to claim 1, wherein the heterogeneous substrate comprises one of a silicon carbide substrate, a diamond substrate, an aluminum nitride substrate, and a silicon substrate.

3. The method for preparing a gallium oxide semiconductor structure according to claim 1, wherein a carrier concentration of the heterogeneous substrate is greater than 1 × 10.sup.18/cm.sup.3.

4. The method for preparing a gallium oxide semiconductor structure according to claim 1, wherein a carrier concentration of the gallium oxide layer is lower than that of the heavily doped gallium oxide layer, wherein the carrier concentration of the gallium oxide layer is in a range of 1 × 10.sup.16/cm.sup.3 to 9 × 10.sup.17/cm.sup.3, and the carrier concentration of the heavily doped gallium oxide layer is greater than 1 × 10.sup.19/cm.sup.3.

5. The method for preparing a gallium oxide semiconductor structure according to claim 1, wherein a method for bonding the polished surface of the gallium oxide single crystal wafer to the polished surface of the heterogeneous substrate comprises surface-activated bonding, and the surface-activated bonding is performed at a vacuum level of 1 × 10.sup.-7 Pa, under a stress of 16 MPa, at a temperature of 25° C.

6. The method for preparing a gallium oxide semiconductor structure according to claim 1, wherein a method for thinning the gallium oxide single crystal wafer comprises grinding or wet etching.

7. The method for preparing a gallium oxide semiconductor structure according to claim 6, wherein when the grinding is adopted to thin the gallium oxide single crystal wafer, the grinding is performed at a gear speed of 1500 rpm to 3000 rpm, a rotational speed of a workbench of 30 rpm to 120 rpm, a feed speed of 5 .Math.m/min to 30 .Math.m/min, and a grinding time of 30 s to 100 min.

8. The method for preparing a gallium oxide semiconductor structure according to claim 1, wherein a method for treating a stop surface of the gallium oxide layer comprises one of chemical mechanical polishing, plasma etching, ion sputtering and chemical etching.

9. The method for preparing a gallium oxide semiconductor structure according to claim 1, wherein the ion implantation comprises one of Si ion implantation, Ge ion implantation, Sn ion implantation and Nb ion implantation.

10. The method for preparing a gallium oxide semiconductor structure according to claim 9, wherein the Si ion implantation takes place at an energy level of 10 Kev to 80 Kev and at a dose of 1 × 10.sup.15 ions/cm.sup.2 to 5 × 10.sup.16 ions/cm.sup.2; the Ge ion implantation takes place at an energy level of 20 Kev to 170 Kev and at a dose of 1 × 10.sup.15 ions/cm.sup.2 to 5 × 10.sup.16 ions/cm.sup.2; the Sn ion implantation takes place at an energy level of 30 Kev to 275 Kev and at a dose of 1 × 10.sup.15 ions/cm.sup.2 to 5 × 10.sup.16 ions/cm.sup.2; and the Nb ion implantation takes place at an energy level of 25 Kev to 225 Kev and at a dose of 1 × 10.sup.15 ions/cm.sup.2 to 5 × 10.sup.16 ions/cm.sup.2.

11. The method for preparing a gallium oxide semiconductor structure according to claim 1, wherein the depth of the ion implantation is in a range of 10 nm to 60 nm.

12. The method for preparing a gallium oxide semiconductor structure according to claim 1, wherein a surface roughness of the polished surface of the gallium oxide single crystal wafer is less than 1 nm, and a surface roughness of the polished surface of the heterogeneous substrate is less than 1 nm.

13. A gallium oxide semiconductor structure, comprising a heterogeneous substrate, a gallium oxide layer and a heavily doped gallium oxide layer stacked in sequence.

14. The gallium oxide semiconductor structure according to claim 13, wherein a carrier concentration of the gallium oxide layer is lower than that of the heavily doped gallium oxide layer, wherein the carrier concentration of the gallium oxide layer is in a range of 1 × 10.sup.16/cm.sup.3 to 9 × 10.sup.17/cm.sup.3, and the carrier concentration of the heavily doped gallium oxide layer is greater than 1 × 10.sup.19/cm.sup.3.

15. The method for preparing a gallium oxide semiconductor structure according to claim 13, wherein the thickness of the gallium oxide layer is in a range of 5 .Math.m to 100 .Math.m, and the thickness of the heavily doped gallium oxide layer is in a range of 10 nm to 60 nm.

16. The method for preparing a gallium oxide semiconductor structure according to claim 13, wherein the heterogeneous substrate comprises one of a silicon carbide substrate, a diamond substrate, an aluminum nitride substrate, and a silicon substrate, and a carrier concentration of the heterogeneous substrate is greater than 1 × 10.sup.18/cm.sup.3.

17. A method for preparing a vertical gallium oxide-based power device, comprising preparing the vertical gallium oxide-based power device by using the method for preparing a gallium oxide semiconductor structure according to claim 1.

18. A vertical gallium oxide-based power device, comprising a gallium oxide semiconductor structure according to claim 13.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG. 1 is a flow chart of a method for preparing a gallium oxide semiconductor structure according to an embodiment of the present disclosure.

[0030] FIG. 2 is a schematic structural diagram of a gallium oxide single crystal wafer according to an embodiment of the present disclosure.

[0031] FIG. 3 is a schematic structural diagram of a heterogeneous substrate according to an embodiment of the present disclosure.

[0032] FIG. 4 is a schematic structural diagram of a structure formed after the polished surface of the gallium oxide single crystal wafer is bonded to the polished surface of the heterogeneous substrate according to an embodiment of the present disclosure.

[0033] FIG. 5 is a schematic structural diagram of a composite structure formed after the structure in FIG. 4 is thinned according to an embodiment of the present disclosure.

[0034] FIG. 6 is a schematic structural diagram of a gallium oxide semiconductor structure formed after the composite structure in FIG. 5 is treated and ion implanted according to an embodiment of the present disclosure.

[0035] FIG. 7 is a schematic structural diagram of a source electrode and a drain electrode formed in the preparation of a vertical gallium oxide-based power device according to an embodiment of the present disclosure.

[0036] FIG. 8 is a schematic structural diagram of a gate electrode formed in the preparation of a vertical gallium oxide-based power device according to an embodiment of the present disclosure.

[0037] FIG. 9 is a schematic structural diagram of a vertical gallium oxide-based power device according to an embodiment of the present disclosure.

REFERENCE NUMERALS

[0038] 100 Gallium oxide single crystal wafer [0039] 100a Polished surface of gallium oxide single crystal wafer [0040] 200 Heterogeneous substrate [0041] 200a Polished surface of heterogeneous substrate [0042] 110 Gallium oxide layer [0043] 120 Heavily doped gallium oxide layer [0044] 300 Source electrode [0045] 400 Drain electrode [0046] 500 Gate oxide layer [0047] 600 Gate electrode [0048] 700 Gate contact

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] The implementations of the present disclosure are described below by way of specific embodiments, and other advantages and effects of the present disclosure are readily comprehensible to those skilled in the art from the disclosure of the present disclosure. The present disclosure may be embodied or practiced in various other specific embodiments, the details in the specification may also be based on different perspectives and applications, and various modifications and changes may be made without departing from the spirit and scope of the present disclosure.

[0050] Referring to FIG. 1 to FIG. 9, it should be noted that drawings provided in this embodiment only exemplify the basic idea of the present disclosure. Therefore, only the components related to the present disclosure are shown in the drawings, and are not drawn according to the quantities, shapes, and sizes of the components during actual implementation. During actual implementation, the types, quantities, and proportions of the components may be randomly changed, and the layout pattern of the components may be more complicated.

[0051] As shown in FIG. 1, an embodiment of the present disclosure provides a method for preparing a gallium oxide semiconductor structure. In the embodiment, an unintentionally doped gallium oxide layer is transferred to a highly doped and highly thermally conductive heterogeneous substrate by bonding and thinning. Then a heavily doped gallium oxide layer is formed on the gallium oxide layer by treating and ion implantation, thereby preparing the gallium oxide semiconductor structure comprising the heterogeneous substrate, the gallium oxide layer, and the heavily doped gallium oxide layer stacked in sequence. Consequently, the present disclosure solves the problem of poor thermal conductivity of a gallium oxide thin film prepared by using a homo-epitaxial method, and the problem of difficulty in growing a high-quality gallium oxide thin film due to lattice mismatch when the gallium oxide thin film is prepared by using an epitaxial method on a heterogeneous substrate.

[0052] In an embodiment, FIGS. 2-6 are schematic structural diagrams of structures formed in each step of preparing the gallium oxide semiconductor structure.

[0053] As shown in FIG. 2, a gallium oxide single crystal wafer 100 is provided, where a surface of the gallium oxide single crystal wafer 100 is a polished surface 100a of the gallium oxide single crystal wafer 100.

[0054] In an embodiment, the gallium oxide single crystal wafer 100 comprises an α-type gallium oxide single crystal wafer or a β-type gallium oxide single crystal wafer, and the size of the gallium oxide single crystal wafer 100 is in a range of 2 inches to 4 inches as required. A surface orientation of the single crystal plane of the gallium oxide single crystal wafer 100 comprises one of (-201), (010), and (001). The gallium oxide single crystal wafer is an unintentionally doped gallium oxide single crystal wafer, and a carrier concentration of the gallium oxide single crystal wafer is in a range of 1 x 10.sup.16/cm.sup.3 to 9 x 10.sup.17/cm.sup.3; and a surface roughness of the polished surface 100a of the gallium oxide single crystal wafer is less than 1 nm, such as 0.2 nm, 0.4 nm, or the like.

[0055] Next, as shown in FIG. 3, a heterogeneous substrate 200 is provided, where the surface of the heterogeneous substrate 200 is a polished surface 200a of the heterogeneous substrate.

[0056] In an embodiment, the heterogeneous substrate 200 is a highly doped, highly thermally conductive heterogeneous substrate, and the heterogeneous substrate 200 comprises one of a silicon carbide substrate, a diamond substrate, an aluminum nitride substrate, and a silicon substrate. A doping concentration of the heterogeneous substrate 200 is greater than 1 x 10.sup.18/cm.sup.3, and a surface roughness of the polished surface 200a of the heterogeneous substrate is less than 1 nm, such as 0.2 nm, 0.4 nm, or the like.

[0057] Next, as shown in FIG. 4, the polished surface 100a of the gallium oxide single crystal wafer is bonded to the polished surface 200a of the heterogeneous substrate.

[0058] In an embodiment, a method for bonding the polished surface 100a of the gallium oxide single crystal wafer to the polished surface 200a of the heterogeneous substrate comprises one of surface-activated bonding, metal bonding and anodic bonding. When the surface-activated bonding is adopted, the surface-activated bonding is performed at a vacuum level of 1 x 10.sup.-7 Pa, under a stress of 16 MPa, and at a temperature of 25° C. In this embodiment, the surface activated bonding is preferred, but the present disclosure is not limited herein.

[0059] Next, as shown in FIG. 5, the gallium oxide single crystal wafer 100 is thinned to obtain a composite structure comprising the heterogeneous substrate 200 and a gallium oxide layer 110 stacked in sequence.

[0060] In an embodiment, a method for thinning the gallium oxide single crystal wafer comprises grinding or wet etching. when the grinding is adopted to thin the gallium oxide single crystal wafer, the grinding is performed at a gear speed of 1500 rpm to 3000 rpm, for example, 1800 rpm, 2000 rpm, or 2500 rpm, a rotational speed of a workbench of 30 rpm to 120 rpm, for example, 60 rpm, 80 rpm, or 100 rpm, a feed speed of 5 .Math.m/min to 30 .Math.m/min, for example, 10 .Math.m/min, 15 .Math.m/min, or 25 .Math.m/min, and a grinding time of 30 s to 100 min, for example, 1 min, 10 min, or 60 min. Grinding is preferred in this embodiment, and the grinding device is an OKAMOTO 200 thinning machine. However, the thinning method and the grinding device are not limited herein, and may be selected as desired. A gallium oxide layer 110 is obtained after the gallium oxide single crystal wafer is thinned, and the thickness of the gallium oxide layer 110 is in the order of microns.

[0061] Next, as shown in FIG. 6, a heavily doped gallium oxide layer 120 is formed on the top surface of the gallium oxide layer 110 by treating a top surface of the gallium oxide layer and performing an ion implantation on the gallium oxide layer, thereby obtaining the gallium oxide semiconductor structure comprising the heterogeneous substrate 200, the gallium oxide layer 110 and the heavily doped gallium oxide layer 120 stacked in sequence. Where the top surface of the gallium oxide layer is facing away from the polished surface of the heterogeneous substrate.

[0062] In an embodiment, a method for treating a top surface of the gallium oxide layer comprises one of chemical mechanical polishing, plasma etching, ion sputtering and chemical etching. The high-quality gallium oxide layer 110 may be acquired through above methods, which facilitates obtaining the heavily doped gallium oxide layer 120 with high-quality through the ion implantation. The ion implantation comprises one of Si ion implantation, Ge ion implantation, Sn ion implantation, and Nb ion implantation. When Si ion implantation is adopted, the Si ion implantation takes place at an energy level of 10 Kev to 80 Kev, for example, 25 Kev, 50 Kev, or 60 Kev, and at a dose of 1 x 10.sup.15 ions/cm.sup.2 to 5 x 10.sup.16 ions/cm.sup.2, for example, 1 x 10.sup.16 ions/cm.sup.2, or 2 x 10.sup.16 ions/cm.sup.2. When Ge ion implantation is adopted, the Ge ion implantation takes place at an energy level of 20 Kev to 170 Kev, for example, 50 Kev, 100 Kev, or 150 Kev, and at a dose of 1 x 10.sup.15 ions/cm.sup.2 to 5 x 10.sup.16 ions/cm.sup.2, for example, 1 x 10.sup.16 ions/cm.sup.2, or 2 x 10.sup.16 ions/cm.sup.2. When Sn ion implantation is adopted, the Sn ion implantation takes place at an energy level of 30 Kev to 275 Kev, for example, 60 Kev, 100 Kev, or 200 Kev, and at a dose of 1 x 10.sup.15 ions/cm.sup.2 to 5 x 10.sup.16 ions/cm.sup.2, for example, 1 x 10.sup.16 ions/cm.sup.2 or 2 x 10.sup.16 ions/cm.sup.2. When Nb ion implantation is adopted, the Nb ion implantation takes place at an energy level of 25 Kev to 225 Kev, for example, 50 Kev, 150 Kev, or 200 Kev, and at a dose of 1 x 10.sup.15 ions/cm.sup.2 to 5 x 10.sup.16 ions/cm.sup.2, for example 1 x 10.sup.16 ions/cm.sup.2, or 2 x 10.sup.16 ions/cm.sup.2. The ion implantation determines the carrier concentration of the heavily doped gallium oxide layer 120. Wherein the carrier concentration of the heavily doped gallium oxide layer 120 is greater than 1 x 10.sup.19 /cm.sup.3. The depth of the ion implantation is in a range of 10 nm to 60 nm, that is, the heavily doped gallium oxide layer 120 is formed to have a thickness of 10 nm to 60 nm, such as 20 nm, 40 nm, 50 nm, or the like. As a result, the gallium oxide semiconductor structure is obtained. In this embodiment, the gallium oxide layer 110 is a thicker intermediate layer, and the carrier concentration of the gallium oxide layer 110 is lower than that of the heavily doped gallium oxide layer 120, which may increase the breakdown voltage of a subsequently prepared device. The highly thermally conductive heterogeneous substrate 200 improves the heat dissipation capacity of the device.

[0063] As shown in FIG. 6, an embodiment of the present disclosure also provides a gallium oxide semiconductor structure. The gallium oxide semiconductor structure can be prepared by the above-mentioned method for preparing a gallium oxide semiconductor structure; however, the present disclosure is not limited herein. The material and structure of the gallium oxide semiconductor structure will not be repeated here. The gallium oxide semiconductor structure comprises a heterogeneous substrate 200, a gallium oxide layer 110 and a heavily doped gallium oxide layer 120 stacked in sequence.

[0064] For example, the carrier concentration of the gallium oxide layer 110 is lower than that of the heavily doped gallium oxide layer 120. Wherein the carrier concentration of the gallium oxide layer 110 is in a range of 1 x 10.sup.16/cm.sup.3 to 9 x 10.sup.17/cm.sup.3, e.g., 6 x 10.sup.16/cm.sup.3, or 6 x 10.sup.17/cm.sup.3, and the carrier concentration of the heavily doped gallium oxide layer 120 is greater than 1 x 10.sup.19 /cm.sup.3.

[0065] For example, the thickness of the gallium oxide layer 110 is in a range of 5 .Math.m and 100 .Math.m, e.g., 10 .Math.m, 25 .Math.m, 50 .Math.m, 75 .Math.m, or the like, and the thickness of the heavily doped gallium oxide layer 120 is in a range of 10 nm and 60 nm, e.g., 20 nm, 40 nm, 50 nm, or the like.

[0066] For example, the heterogeneous substrate 200 comprises one of a silicon carbide substrate, a diamond substrate, an aluminum nitride substrate, and a silicon substrate, and the carrier concentration of the heterogeneous substrate is greater than 1 x 10.sup.18/cm.sup.3.

[0067] An embodiment of the present disclosure also provides a method for preparing a vertical gallium oxide-based power device, which comprises preparing the vertical gallium oxide-based power device by using the method for preparing a gallium oxide semiconductor structure as described above. Details may be made reference to following embodiments, which will not be described here.

[0068] In an embodiment, the vertical gallium oxide-based power device prepared on the basis of the gallium oxide semiconductor structure is provided. In the vertical gallium oxide-based power device, the gallium oxide layer is a thicker intermediate layer, the carrier concentration of the gallium oxide layer is lower than that of the heavily doped gallium oxide layer, and a breakdown voltage of the vertical gallium oxide-based power device is also increased through structural design. In addition, the highly thermally conductive heterogeneous substrate improves the heat dissipation capacity of the vertical gallium oxide-based power device. Therefore, above characteristics are extremely important for the development of vertical gallium oxide-based high-power devices in the future.

[0069] An embodiment of the present disclosure also provides a vertical gallium oxide-based power device, which comprises a gallium oxide semiconductor structure as described above.

[0070] In an embodiment, as shown in FIG. 9, the vertical gallium oxide-based power device comprises the gallium oxide semiconductor structure, a drain electrode 400, a source electrode 300, a gate oxide layer 500, a gate electrode 600, and a gate contact 700. Where the gallium oxide semiconductor structure includes the heterogeneous substrate 200, the gallium oxide layer 110 and the heavily doped gallium oxide layer 120 stacked in sequence. The drain electrode 400 is in contact with the heterogeneous substrate 200. The source electrode 300 is located on the heavily doped gallium oxide layer 120. The gate oxide layer 500 and a gate electrode 600 are stacked in sequence and located on the gallium oxide layer 110. And the gate contact 700 is located on the gate electrode 600.

[0071] FIGS. 7-9 are schematic structural diagrams of structures formed in each step of preparing a vertical gallium oxide-based power device on the basis of the gallium oxide semiconductor structure.

[0072] In an embodiment, FIG. 7 is a schematic structural diagram of a source electrode 300 and a drain electrode 400 formed in the preparation of a vertical gallium oxide-based power device according to an embodiment of the present disclosure. In FIG. 7, a Fin is formed after the heavily doped gallium oxide layer 120 and the gallium oxide layer 110 are etched, the source electrode 300 is formed on the heavily doped gallium oxide layer 120 and the drain electrode 400 is formed on the surface of the heterogeneous substrate 200. The number of the Fin is preferably greater than 4. the present disclosure is described by taking 4 fins as an example, however, the present disclosure is not limited herein. The device with multiple Fins further provides a large amount of current. The source electrode 300 or the drain electrode 400 may be an Au/Ti electrode; however, the present disclosure is not limited herein. The method for preparing the source electrode 300 or the drain electrode 400 is not limited herein. FIG. 8 is a schematic structural diagram of a gate electrode formed in the preparation of a vertical gallium oxide-based power device according to an embodiment of the present disclosure. In FIG. 8, the gate oxide layer 500 and the gate electrode 600 are prepared on the basis of the structure formed in FIG. 7. The gate oxide layer 500 may be made of alumina, silica, or the like, and the gate electrode 600 may be a Pt/Ti electrode or a Pt electrode, etc. FIG. 9 is a schematic structural diagram of a vertical gallium oxide-based power device according to an embodiment of the present disclosure. In FIG. 9, the source electrode 300 is exposed by etching, a gate contact 700 is formed on the gate electrode 600, then the vertical gallium oxide-based power device is prepared.

[0073] The present disclosure is further described in conjunction with specific embodiments.

[0074] A β-type unintentionally doped gallium oxide single crystal wafer having a polished surface, a size of 2 inches, a surface orientation of (-201), and a thickness of 680 .Math.m, and a silicon carbide substrate having a polished surface, a size of 4 inches, a surface orientation of (0001), and a thickness of 350 .Math.m are provided. The polished surface of the gallium oxide single crystal wafer is bonded to the polished surface of the silicon carbide substrate to form a bonded sheet. The gallium oxide single crystal wafer on the bonded sheet was ground and chemically polished, to obtain a gallium oxide layer with a thickness of 50 .Math.m on the silicon carbide substrate. Si ion implantation is performed on the gallium oxide layer to form a heavily doped gallium oxide layer with a thickness of 40 nm. Wherein Si ion implantation is performed at an energy level of 20 Kev, a dose of 2 x 10.sup.16 ions/cm.sup.2, and a temperature of 20° C. Accordingly, a gallium oxide semiconductor structure on a highly doped, highly thermally conductive heterogeneous substrate is formed.

[0075] A vertical gallium oxide-based power device is prepared on the basis of the gallium oxide semiconductor structure on a highly doped, highly thermally conductive heterogeneous substrate through the following process:

[0076] A hard mask is formed after the metal chromium (Cr) with a thickness of 150 nm is exposure to electron beam or by thermal evaporation.

[0077] Next, the hard disk is etched by using inductive coupled plasma (ICP), to form a Fin with a height of 1.5 .Math.m and a width of 400 nm. Wherein an etching time is 15 min, and an etching gas is Bcl.sub.3/Cl.sub.2/Ar. The number of the Fin is preferably greater than 4. The present disclosure takes 4 Fins as an example; however, the present disclosure is not limited herein. Referring to FIG. 7.

[0078] The remaining chromium is then removed by using a chromium removing agent, and then metal deposition is performed on the Fin to form a source electrode. Wherein the source electrode is an Au/Ti electrode, the thickness of metal Ti is 20 nm, and the thickness of metal Au is 100 nm. A drain electrode is formed on a bottom surface of the silicon carbide substrate. The preparation method and material of the drain electrode are similar to those of the source electrode. A step of thinning the silicon carbide substrate may be performed before the drain electrode is formed.

[0079] Next, a 20 nm-thick gate oxide layer and a 50 nm-thick gate electrode are formed on the Fin by using atomic layer deposition process (ALD), as shown in FIG. 8. Wherein the material of the gate oxide layer is alumina (AI.sub.2O.sub.3), and the material of the gate electrode is metal Pt.

[0080] Finally, the gate electrode and the gate oxide layer on the Fin are partially removed, to expose the source electrode, and the gate contact is prepared by using electron beam lithography system (EBL), as shown in FIG. 9. In this way, the preparation of the vertical gallium oxide-based power device is completed.

[0081] As described above, the present disclosure provides the gallium oxide semiconductor structure, the vertical gallium oxide-based power device and the preparation method. An unintentionally doped gallium oxide layer is transferred to a highly doped and highly thermally conductive heterogeneous substrate by bonding and thinning. Then a heavily doped gallium oxide layer is formed on the gallium oxide layer by treating and ion implantation, thereby preparing the gallium oxide semiconductor structure comprising the heterogeneous substrate, the gallium oxide layer, and the heavily doped gallium oxide layer stacked in sequence. Consequently, the present disclosure solves the problem of poor thermal conductivity of a gallium oxide thin film prepared by using a homo-epitaxial method, and the problem of difficulty in growing a high-quality gallium oxide thin film due to lattice mismatch when the gallium oxide thin film is prepared by using an epitaxial method on a heterogeneous substrate. In a vertical gallium oxide-based power device prepared on the basis of the gallium oxide semiconductor structure, the gallium oxide layer is a thicker intermediate layer and a carrier concentration of the gallium oxide layer is less than that of the heavily doped gallium oxide layer. In addition, the breakdown voltage of the device is also increased through structural design. The highly thermally conductive heterogeneous substrate improves the heat dissipation performance of the device. The device with multiple Fin structures provides a large amount of current. The present disclosure is of great significance for the development of vertical gallium oxide-based high-power devices in the future. Thus, the present disclosure effectively overcomes various shortcomings in the prior art and has high industrial application value.

[0082] The above embodiments are merely illustrative of the principles and advantages of the present disclosure, and not intended to limit the present disclosure. Modifications or variations can be made to the above embodiments by those skilled in the art without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the present disclosure are covered by the appended claims of the present disclosure.