Ion trap

Abstract

An ion trap is generally constructed as a linear Paul trap in which at least one charged particle is radially trapped with the aid of a quadrupole radio frequency field. The ion trip has a first chip and a second chip aligned with respect to each other, and the two chips are preferably structurally identical. Both chips have a front side, a reverse side, and a chip slot. The second chip is attached to the first chip such that a vertical projection onto a first-chip plane, along which the first chip extends, results in an ion trap slot. The first and second chips each have DC voltage electrode, a compensation electrode, and a high-frequency electrode, and each electrode is designed to receive a DC voltage, and preferably all of the electrodes are electrically insulated from one another.

Claims

1. An ion trap, comprising: a first chip comprising a first-chip front side and a first-chip reverse side, and a first-chip slot; and a second chip comprising a second-chip front side and a second-chip reverse side, and a second-chip slot, wherein the second chips fixed to the first chip such that a slot of the ion trap is formed in vertical projection onto a first-chip plane along which the first chip extends, wherein the first chip comprises a first-chip segment comprising a first DC voltage electrode which is arranged on the first-chip reverse side, extends at least in sections along the first-chip plane, is designed to apply a first DC voltage, is arranged on a first edge side with respect to the first-chip slot, and abuts the slot of the ion trap, and a first compensation electrode which is arranged on the first-chip front side, extends at least in sections along the first-chip plane, is designed to apply a second DC voltage, and is arranged on the first edge side with respect to the first-chip slot, wherein the first chip comprises a first-chip high-frequency electrode, which is arranged opposite the first compensation electrode and a second compensation electrode on a second edge side opposite the first edge side with respect to the first-chip slot, and is designed to apply a high-frequency voltage, wherein the second chip comprises a second-chip segment located downstream of the first-chip high-frequency electrode in a direction of a normal to the first-chip plane, a second DC voltage electrode which is arranged on the second-chip front side, extends at least in sections along a second-chip plane along which the second chip extends, and is designed to apply a third DC voltage, and a second compensation electrode which is arranged on the second-chip reverse side, extends at least in sections along the second-chip plane, and is designed to apply a fourth DC voltage, wherein the second chip comprises a second-chip high-frequency electrode located downstream of the first-chip segment in the direction of the normal to the first-chip plane, and wherein the first compensation electrode and the second compensation electrode are electrically insulated against each other.

2. The ion trap according to claim 1, wherein the first-chip segment has a recess on an edge surface that is adjacent to the first-chip slot and extends transversely to the first-chip plane, and wherein the first compensation electrode has a first-electrode recess section that extends along the first-chip plane and is spaced apart from the first-chip reverse side and the first-chip front side.

3. The ion trap according to claim 1 wherein the first DC voltage electrode extends along the first-chip plane in a recess section and is spaced apart from the first-chip reverse side; and further comprising an insulating strip between the first-electrode recess section and the recess section.

4. The ion trap according to claim 1, wherein (a) the first-chip segment is tongue-shaped and extends in a segment extension direction that extends transversely to a slot extension direction along which the first-chip slot (14) extends, and/or (b) the second-chip segment is tongue-shaped and extends in a segment extension direction that extends transversely to a slot extension direction along which the second-chip slot extends.

5. The ion trap according to claim 3, wherein o a distance between the recess section and the first-chip reverse side is smaller than 0.7 times a substrate thickness of the first chip.

6. The ion trap according to claim 2 wherein the recess is designed such that the first compensation electrode is covered by the first DC voltage electrode as viewed from a trap volume of the ion trap.

7. The ion trap according to claim 6, wherein the sine of half the opening angle of a cone comprising a tip that lies in the center of the trap volume and which does not intersect the ion trap is at least 0.45.

8. The ion trap according to claim 1 wherein a clear chip distance of the first chip and the second chip from each other deviates by at most 15% from a first slot width of the first-chip slot and/or from a second slot width of the second-chip slot.

9. The ion trap according to claim 1 wherein the first chip comprises at least a second first-chip segment (configured next to the first-chip segment with respect to the slot extension direction, wherein the second first-chip segment is constructed in the same way as the first-chip segment.

10. The ion trap according to claim 1 wherein (a) the first chip comprises at least three first-chip segments (that are arranged next to each other along the first-chip slot, and/or (b) the second chip comprises at least three second-chip segments (that are arranged next to each other along the second-chip slot.

11. An ion trap system, comprising: (a) an ion trap according to claim 1; and (b) a control unit which (i) is electrically connected to the first DC voltage electrode, the first compensation electrode, the first-chip high-frequency electrode, the second DC voltage electrode, the second compensation electrode, and the second-chip high-frequency electrode of the ion trap, and (ii) is configured to automatically apply a high-frequency voltage to the first-chip high-frequency electrode and the second-chip high-frequency electrod, thereby forming the trap volume, and a predetermined DC voltage on each of the first compensation electrode and the second compensation electrode, and/or each of the first DC voltage electrode and the second DC voltage electrode.

12. The ion trap system according to claim 11, further comprising a photodetector arranged to detect photons emitted by an ion arranged in the trap volume.

Description

DESCRIPTION OF THE DRAWINGS

[0053] In the following, the invention will be explained with the aid of the accompanying drawings. They show

[0054] FIG. 1a a cross-section view through an ion trap according to the invention,

[0055] FIG. 1b a top view of the ion trap according to the invention according to FIG. 1a, and

[0056] FIG. 2 the second chip of the ion trap according to FIG. 1a.

DETAILED DESCRIPTION

[0057] FIG. 1a shows an ion trap 10 comprising a first chip 12, which has a first-chip front side F.sub.12 and a first-chip reverse side R.sub.12 and features a first-chip slot 14. In addition, the ion trap 10 has a second chip 16, which has a second-chip front side F.sub.16 and a second-chip reverse side R.sub.16 and features a second-chip slot 18. The second chip 16 is fixed to the first chip 12 such that a slot 20 of the ion trap 10 is formed in vertical projection onto a first-chip plane E.sub.12 along which the first chip 12 extends.

[0058] The first chip 12 has a first-chip segment S.sub.1.1, in which the first chip 12 has a first DC voltage electrode 22 that is at least also arranged on the first-chip reverse side R.sub.12 and extends in sections along the first-chip plane E.sub.12. During operation, a first DC voltage U.sub.DC1,1 acts on the first DC voltage electrode 22, said voltage serving to trap an ion 24 in a trap volume V.

[0059] The first DC voltage electrode 22 is arranged on a first edge side U1 with respect to the first-chip slot 44 and abuts the slot 20. In the first-chip segment S1.1, the first chip 12 has a first compensation electrode 26, which is arranged on the first-chip front side F.sub.12, extends along the first-chip plane E.sub.12 and is arranged on the first edge side U1 with respect to the first-chip slot 14.

[0060] During operation of the ion trap 10, a second DC voltage U.sub.DC2,1 acts on the first compensation electrode 26, by means of which the ion 24 can be displaced along a slot extension direction along a combination of d2+d1.

[0061] The first chip 12 has a first-chip high-frequency electrode 28, which is arranged on the second edge side U2 opposite the first edge side U1 in relation to the slot 20. The first-chip high-frequency electrode 28 thus lies opposite the first DV voltage electrode 22 and the first compensation electrode 26. During operation, a high-frequency voltage U.sub.RF acts on the first-chip high-frequency electrode 28.

[0062] The second chip 16 has a second-chip segment S2.1 (see FIG. 2) that is located downstream of the first-chip high-frequency electrode 28 in the direction of a normal N to the first-chip plane E.sub.12. The second chip 16 has a second DC voltage electrode 30, which is arranged on the second-chip front side F.sub.16 and extends in sections along a second-chip plane E.sub.16. During operation of the ion trap 10, a third DC voltage U.sub.DC3,1 acts on the second DC voltage electrode 30, by means of which the ion 24 is held in the trap volume V.

[0063] In addition, the second chip 16 has a second compensation electrode 32, which is arranged on the second-chip reverse side R.sub.16 and extends largely along a second-chip plane E.sub.16. During operation of the ion trap 10, a fourth DC voltage U.sub.DC4,1 acts on the second compensation electrode 32.

[0064] The second chip 16 also has a second-chip high-frequency electrode 34, which is located downstream of the first-chip segment S1.1 in the direction of the normal N. The compensation electrodes 26, 32 are electrically insulated against each other. Correspondingly, the DC current electrodes 22, 30 are electrically insulated against each other.

[0065] The enlargement in FIG. 1a shows that the first-chip segment S1.1 has a recess 38 on an edge surface 36 that is adjacent to the first-chip slot 14 and extends transversely to the first-chip plane E.sub.12.

[0066] The first compensation electrode 26 has a first-electrode recess section 39 that extends along the first-chip plane E.sub.12preferably, but not necessarily, parallel to the first-chip plane E.sub.12and is spaced apart from the first-chip reverse side R.sub.12. A distance h.sub.0 between the first compensation electrode 26 in the first-electrode recess section 39 and the first DC voltage electrode 22 is thus smaller than a substrate thickness D.sub.12=b.sub.1+h.sub.0 with a recess height b.sub.1. The recess 39 has a recess depth b.sub.2.

[0067] Between the first compensation electrode 26 and the first DC voltage electrode 22 is an insulating strip 40, in which a substrate 42 of the first chip 12 does not have a metallization. The insulating strip 40 can be at an insulating strip distance 8 from the edge surface 36. As in the present embodiment, the insulating strip 40 may extend between the first-electrode recess section 39 and a recess section 41 of the first DC voltage electrode 22. The recess section 41 extends along the first-chip plane E.sub.12 and is spaced apart from the first-chip reverse side R.sub.12 and is preferably at the same distance to the first-chip reverse side R.sub.12 as the first-electrode recess section 39. However, the recess 38 may also have a form different to the one illustrated in FIG. 1a.

[0068] According to a preferred embodiment, the first DC voltage electrode 22 covers the insulating strip 40, as viewed from the trap volume V.

[0069] The second compensation electrode 32 may also feature a recess. It is preferably designed like the recess 39. The second chip 16 preferably, but not necessarily, has the structure shown in the enlargement, wherein the second compensation electrode 32 then corresponds to the first compensation electrode 26 and the second DC voltage electrode 30 corresponds to the first DC voltage electrode 22.

[0070] If the ion 24 in the trap volume V emits a photon 44, it can be absorbed by a photodetector 44 if it is emitted at an opening angle . A second photodetector for light emitted in the opposite direction is not depicted.

[0071] FIG. 1b shows that the first chip 12 may comprise a first-chip segment S1.2 and, if necessary, at least a third first-chip segment S1.3. The first-chip segments S1.i (i=1, 2, . . . . N) are arranged next to one another along the slot extension direction R.sub.20. It is favorable if the first-chip segments S1.i are constructed in the same way.

[0072] The first-chip high-frequency electrode 28 may comprise tongues 46.i, each of which is arranged opposite the first-chip segment S1.i and extends in a segment extension direction R.sub.S.

[0073] FIG. 2 depicts the second chip 16, which is constructed in the same way as the first chip 12 and comprises second-chip segments S2.i. Each second-chip segment S2.i is arranged at the same height along the slot extension direction R.sub.20 as the corresponding first-chip segment S1.i.

[0074] FIG. 1a schematically depicts a control unit 48 next to the photodetector, the former being connected to the electrodes and applying the respective voltage to them; it also constitutes part of an ion trap system 52. The voltages are controlled, for example, according to a predetermined program by means of a processor 50 of the control unit 48.

REFERENCE SIGNS

[0075] 10 ion trap [0076] 12 first chip [0077] 14 first-chip slot [0078] 16 second chip [0079] 18 second-chip slot [0080] 20 slot [0081] 22 first DC voltage electrode (U.sub.DC1,1) [0082] 24 ion [0083] 26 first compensation electrode (U.sub.DC2,1) [0084] 28 first-chip high-frequency electrode [0085] 30 second DC voltage electrode (U.sub.DC3,1) [0086] 32 second compensation electrode (U.sub.DC4,1) [0087] 34 second-chip high-frequency electrode [0088] 36 edge surface [0089] 38 recess [0090] 39 first-electrode recess section [0091] 40 insulating strip [0092] 41 recess section [0093] 42 substrate [0094] 44 photodetector [0095] 46 tongue [0096] 48 control unit [0097] 50 processor [0098] 52 ion trap system [0099] acceptance angle [0100] insulating strip distance [0101] b.sub.1 recess height [0102] b.sub.2 recess depth [0103] D.sub.12 substrate thickness [0104] E.sub.12 first-chip plane [0105] E.sub.16 second-chip plane [0106] 12 first-chip front side [0107] 16 second-chip front side [0108] h.sub.0 distance [0109] i numerical index [0110] N normal [0111] P photon [0112] 12 first-chip reverse side [0113] 16 second-chip reverse side [0114] R.sub.20 slot extension direction [0115] R.sub.S segment extension direction [0116] S.sub.1.i i-th first-chip segment [0117] S.sub.2.1 second-chip segment [0118] U.sub.DC1,1 first DC voltage [0119] U.sub.DC2,1 second DC voltage [0120] U.sub.DC3,1 third DC voltage [0121] U.sub.DC4,1 fourth DC voltage [0122] U.sub.1 first edge side [0123] U.sub.2 second edge side [0124] U.sub.RF high-frequency voltage (radio frequency) [0125] V trap volume