SEMICONDUCTOR POWER DEVICE

Abstract

A semiconductor power device includes a substrate, a channel layer, a barrier layer, a gate, a source, and a drain. The channel layer is located on the substrate. The barrier layer is located on the channel layer and includes a first region and a second region outside the first region. There is a first compound in the first region and a second compound in the second region. The first compound and the second compound each have an aluminum atom of a different ratio, and the aluminum composition ratio of the first compound is less than the aluminum composition ratio of the second compound. The ratio consists of a plurality of different atoms in the first compound and the second compound.

Claims

1. A semiconductor power device, comprising: a substrate; a channel layer, located on the substrate; a barrier layer, located on the channel layer, wherein the barrier layer comprises a first region and a second region outside the first region, there is a first compound in the first region and a second compound in the second region, the first compound and the second compound each have an aluminum atom of a different ratio, the ratio consists of a plurality of different atoms in the first compound and the second compound, and an aluminum composition ratio of the first compound is less than an aluminum composition ratio of the second compound; a source and a drain, wherein the source and the drain are respectively located on the second region; and a gate, located between the source and the drain and on the first region, wherein the gate, the source, and the drain each comprise Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, Pb, Ti/Al, Ti/Au, Ti/Pt, Al/Au, Ni/Au, or Au/Ni.

2. The semiconductor power device according to claim 1, wherein the first compound further comprises a gallium atom, which replaces a part of the aluminum atom in the first compound, and the second compound further comprises another gallium atom, which replaces a part of the aluminum atom in the second compound.

3. The semiconductor power device according to claim 1, wherein the aluminum composition ratio of the second compound is less than 0.8.

4. The semiconductor power device according to claim 1, wherein the channel layer comprises GaN, InGaN, or Ga.sub.2O.sub.3.

5. The semiconductor power device according to claim 1, wherein the first compound comprises Al.sub.xGa.sub.(1x)N, and the second compound comprises Al.sub.yGa.sub.(1y)N, wherein x represents a first ratio and y represents a second ratio, and y>x>0.

6. The semiconductor power device according to claim 1, wherein the first compound comprises In.sub.xGa.sub.(1x)N, and the second compound comprises Al.sub.yIn.sub.xGa.sub.(1xy)N, wherein x represents a first ratio and y represents a second ratio, and y>0 and (x+y)<1.

7. The semiconductor power device according to claim 1, wherein the first compound comprises (Al.sub.xGa.sub.1x).sub.2O.sub.3, and the second compound comprises (Al.sub.yGa.sub.1y).sub.2O.sub.3, wherein x represents a first ratio and y represents a second ratio, and y>x>0.

8. The semiconductor power device of claim 1, wherein the barrier layer comprises indium, and an indium composition ratio of the first region is greater than an indium composition ratio of the second region.

9. The semiconductor power device according to claim 1, wherein the barrier layer has a notch in the first region, and the gate is filled in the notch.

10. The semiconductor power device according to claim 9, further comprising a dielectric layer located between the barrier layer and the gate.

11. The semiconductor power device according to claim 1, further comprising a buffer layer located between the substrate and the channel layer.

12. The semiconductor power device according to claim 1, wherein the substrate comprises SiC, Si, GaN, sapphire, Ga.sub.2O.sub.3, or polycrystalline aluminum nitride (poly-AlN).

13. A semiconductor power device, comprising: a substrate; a channel layer, located on the substrate; a barrier layer, located on the channel layer, and having an opening, wherein the barrier layer is an aluminum compound, the aluminum compound comprises an aluminum atom consisting of a ratio and a gallium atom consisting of another ratio, which represents that the gallium atom replaces a part of the aluminum atom; a gate, located on the barrier layer, and being filled in the opening; and an insulating layer, located between the gate and the channel layer, and being in direct contact with the channel layer; and a source and a drain, wherein the source and the drain are respectively located on the barrier layer on two sides of the gate.

14. The semiconductor power device according to claim 13, wherein the insulating layer is a high dielectric coefficient (high-k) material.

15. The semiconductor power device according to claim 13, wherein the channel layer is GaN, InGaN, or Ga.sub.2O.sub.3, and the aluminum compound is Al.sub.aGa.sub.(1a)N, Al.sub.aIn.sub.bGa.sub.(1ab)N, or (Al.sub.aGa.sub.1a).sub.2O.sub.3, wherein a<1 and (a+b)<1, a represents a ratio of aluminum, b represents a ratio of indium, and 1a and 1ab each represent different ratios of gallium.

16. The semiconductor power device according to claim 13, further comprising a buffer layer located between the substrate and the channel layer.

17. The semiconductor power device according to claim 13, wherein the gate, the source, and the drain each comprise Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, Pb, Ti/Al, Ti/Au, Ti/Pt, Al/Au, Ni/Au, or Au/Ni.

18. The semiconductor power device according to claim 13, wherein the substrate comprises SiC, Si, GaN, sapphire, Ga.sub.2O.sub.3, or polycrystalline aluminum nitride (poly-AlN).

19. A semiconductor power device, wherein the semiconductor power device has at least one original physical property before being doped with an aluminum ion, the aluminum ion improves the original physical property after the semiconductor power device is doped with the aluminum ion, and the semiconductor power device being doped with the aluminum ion comprises: a substrate, represented by a first chemical formula, wherein the first chemical formula comprises an element semiconductor or a compound semiconductor; a channel layer, located on the substrate, and represented by a second chemical formula, wherein the second chemical formula comprises another compound semiconductor; a barrier layer, located on the channel layer, wherein the barrier layer comprises at least one compound, the compound located in at least one region of the barrier layer is represented by a third chemical formula, and the compound comprises an aluminum atom consisting of a ratio; a source and a drain, wherein the source and the drain are compositions having a metal material, wherein the source and the drain are each independently located on the region; and a gate, wherein the gate is a metal composition, and the gate is located between the source and the drain and outside the region.

20. The semiconductor power device according to claim 19, wherein the barrier layer comprises a first region and a second region outside the first region, the compound comprises a first compound located in the first region and a second compound located in the second region, the first compound comprises an aluminum atom consisting of a first ratio, the second compound comprises another aluminum atom consisting of a second ratio, and the first ratio and the second ratio are different.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments and, together with the description, serve to explain the principles of the disclosure.

[0012] FIG. 1 is a schematic cross-sectional diagram of a semiconductor power device according to a first embodiment of the disclosure.

[0013] FIG. 2 shows a carrier concentration as a function of an aluminum composition ratio of a barrier layer.

[0014] FIG. 3 shows a sheet resistance changing according to an aluminum composition ratio of the barrier layer 104.

[0015] FIG. 4 is an I-V curve diagram (linear plot) of a semiconductor power device of a simulation experiment example.

[0016] FIG. 5 is an I-V curve diagram (logarithmic plot) of a semiconductor power device of a simulation experiment example.

[0017] FIG. 6 is a schematic cross-sectional diagram of a semiconductor power device according to a second embodiment of the disclosure.

[0018] FIG. 7 is a schematic cross-sectional diagram of a semiconductor power device according to a third embodiment of the disclosure.

[0019] FIG. 8 is a schematic cross-sectional diagram of a semiconductor power device according to a fourth embodiment of the disclosure.

DETAILED DESCRIPTION OF DISCLOSURED EMBODIMENTS

[0020] FIG. 1 is a schematic cross-sectional diagram of a semiconductor power device according to a first embodiment of the disclosure.

[0021] Referring to FIG. 1, a semiconductor power device 10a of the first embodiment basically includes a substrate 100, a channel layer 102, a barrier layer 104, a gate G, a source S, and a drain D. The substrate 100 is represented by a first chemical formula, which includes an element semiconductor or a compound semiconductor, such as, but not limited to, silicon carbide (SiC), silicon (Si), gallium nitride (GaN), sapphire, gallium oxide (Ga.sub.2O.sub.3), or polycrystalline aluminum nitride (poly-AlN). The channel layer 102 is located on the substrate 100. The channel layer 102 is represented by a second chemical formula. The second chemical formula includes another compound semiconductor. In an embodiment, the channel layer 102 can be GaN, indium gallium nitride (InGaN), or gallium oxide (Ga.sub.2O.sub.3, also referred to as -Ga.sub.2O.sub.3). A barrier layer 104 is located on the channel layer 102. A two-dimensional electron gas 2DEG generated in the first embodiment always exists at the interface of the channel layer 102 close to the barrier layer 104, so the semiconductor power device 10a belongs to a depletion mode (D-mode) transistor, which is turned on in a normal state. In addition, a buffer layer 106 or other functional film layers can be provided between the substrate 100 and the channel layer 102. For example, the buffer layer 106 can be AlN or aluminum gallium nitride (AlGaN)/GaN superlattice structure, or the like.

[0022] The barrier layer 104 includes at least one compound. The compound located in at least one region of the barrier layer 104 is represented by a third chemical formula. The compound includes an aluminum atom consisting of a ratio. For example, the barrier layer 104 in the first embodiment includes a first region 104a and a second region 104b outside the first region 104a. There is a first compound in the first region 104a and a second compound in the second region 104b. The first compound and the second compound each have an aluminum atom of a different ratio. The ratio consists of a plurality of different atoms in the first compound and the second compound. In other words, the first compound includes one aluminum atom consisting of a first ratio, the second compound includes another aluminum atom consisting of a second ratio, and the first ratio and the second ratio are different. In the first embodiment, the first ratio is less than the second ratio; that is, the aluminum composition ratio of the first compound is less than the aluminum composition ratio of the second compound.

[0023] In an embodiment, the first compound further includes one gallium atom, which replaces a part of the aluminum atom in the first compound. The second compound further includes another gallium atom, which replaces a part of the said aluminum atom in the second compound. For example, the first compound in the first region 104a of the barrier layer 104 is Al.sub.xGa.sub.(1x)N, and the second compound in the second region 104b of the barrier layer 104 is Al.sub.yGa.sub.(1y)N, where x represents the first ratio and y represents the second ratio, and y>x>0. The first compound in the first region 104a of the barrier layer 104 is In.sub.xGa.sub.(1x)N, and the second compound in the second region 104b of the barrier layer 104 is Al.sub.yIn.sub.xGa.sub.(1xy)N, where x represents the first ratio and y represents the second ratio, and y>0, (x+y)<1. The first compound in the first region 104a of the barrier layer 104 is (Al.sub.xGa.sub.1x).sub.2O.sub.3, and the second compound in the second region 104b of the barrier layer 104 is (Al.sub.yGa.sub.1y).sub.2O.sub.3, where x represents the first ratio and y represents the second ratio, and y>x>0; and so on.

[0024] The manufacturing method of the barrier layer 104 can be, for example, but not limited to: after epitaxially growing the buffer layer 106, the channel layer 102, and the barrier layer on the substrate 100 (for example, fully forming the first compound), firstly forming the gate G on the surface of the barrier layer, and then performing an aluminum (Al.sup.+) ion implantation process to dope the second region 104b outside the first region 104a with aluminum, so that at least one of the original physical properties (such as carrier concentration, etc.) that the semiconductor power device 10a has before being doped with an aluminum ion is improved due to being doped with the aluminum ion. After the aluminum ion implantation process, the first compound in the second region 104b becomes a second compound with a larger aluminum composition ratio. The aluminum composition ratio of the second compound in the second region 104b can be converted through material analysis (such as EDS analysis).

[0025] Continuing to refer to FIG. 1, each of the source S and the drain D is located on the second region 104b. The gate G is located between the source S and the drain D and on the first region 104a. The source S and the drain D are compositions having a metal material. The gate G is a metal composition. In an embodiment, the gate G, the source S, and the drain D each include gold (Au), aluminum (Al), titanium (Ti), tin (Sn), germanium (Ge), indium (In), nickel (Ni), cobalt (Co), platinum (Pt), tungsten (W), molybdenum (Mo), chromium (Cr), copper (Cu), lead (Pb), Ti/Al, Ti/Au, Ti/Pt, Al/Au, Ni/Au, or Au/Ni. The material of the gate G can be the same as or different from the source S and drain D. In FIG. 1, although a distance Lgs from the gate G to the source S is similar to a distance Lgd from the gate G to the drain D, from the perspective of increasing the breakdown voltage, the distance Lgd from the gate to the drain is much greater than the distance Lgs from the gate to the source.

[0026] The carrier concentration relationship of the first region 104a below the gate G (low Al composition ratio region) and the second region 104b outside the gate G (high Al composition ratio region) is as shown in FIG. 2. It can be seen from FIG. 2 that the higher the Al composition ratio (x), the greater the carrier concentration.

[0027] That is to say, in FIG. 1, the concentration of the two-dimensional electron gas 2DEG generated below the second region 104b outside the first region 104a is greater than the concentration of the two-dimensional electron gas 2DEG generated below the first region 104a. Since an on-resistance Ron of the semiconductor power device 10a consists of 2R.sub.c+R.sub.ch+R.sub.SG+R.sub.GD (R.sub.c refers to the contact resistance, R.sub.ch refers to the channel resistance below the gate G, R.sub.SG refers to the source-gate resistance, R.sub.GD refers to the gate-drain resistance), once the carrier concentration generated below the second region 104b increases, the source-gate resistance R.sub.SG and the gate-drain resistance R.sub.GD can decrease, thereby reducing the on-resistance Ron. The first region 104a which maintains a relatively low Al composition ratio can prevent the barrier layer 104 from increasing stress, thereby improving the reliability of the gate G without having too much impact on the on-resistance Ron.

[0028] Moreover, when the channel layer 102 is a gallium oxide (-Ga.sub.2O.sub.3) material, since -Ga.sub.2O.sub.3 has a high energy gap (Eg=4.9 eV) and a high dielectric collapse electric field (Ec=6.5 MV/cm) but an electron mobility of only about 200 cm.sup.2/V.Math.s, doping aluminum to increase the aluminum composition ratio of the second compound in the second region 104b can increase the electron mobility of -Ga.sub.2O.sub.3 and reduce the on-resistance Ron, which is critical to the development of gallium oxide power devices.

[0029] FIG. 3 shows a sheet resistance changing according to an aluminum composition of the barrier layer 104. As shown in FIG. 3, when the Al composition ratio (x) is less than 0.23, the sheet resistance is >100 /sq; when the Al composition ratio (x) is greater than 0.23, the sheet resistance is <100 /sq. Therefore, the Al composition ratio (x) can be set as 0.23 as the boundary, which defines that the Al composition ratio (x) of the first region 104a is less than 0.23 (i.e., low aluminum concentration), and the Al composition ratio (x) of the second region 104b is greater than or equal to 0.23 (i.e., high aluminum concentration). However, the disclosure is not limited thereto. Depending on the device design and requirements of the semiconductor power device 10a, the boundary of the Al composition ratio (x) can also be greater than 0.23 or less than 0.23.

[0030] Continuing to refer to FIG. 1, the aluminum concentration in the second region 104b is greater than the aluminum concentration in the first region 104a, which has the effect of reducing the on-resistance Ron. As for the upper limit of the aluminum concentration in the second region 104b, there is no limit. If low leakage is taken into consideration, the upper limit of the Al composition ratio (x) of the second region 104b is 0.8. For example, the aluminum composition ratio (x) in the material of the second region 104b can be 0<x<0.8 or 0.2<x<0.8 or 0.25<x<0.7. In addition, if the material of the barrier layer 104 contains indium, the indium composition ratio of the first region 104a can be greater than the indium composition ratio of the second region 104b, since if the indium composition ratio is low, the polarization effect can become stronger and the resistance can decrease. The indium composition ratio of the first region 104a is, for example, less than 0.8.

[0031] The following experiment examples are illustrated by simulation to describe the effect of the disclosure, but the disclosure is not limited to the following contents.

Simulation Experiment Example

[0032] The simulated semiconductor power device was shown in FIG. 1. The channel layer was GaN, a gate length Lg was set to 1.4 m, the distance Lgs from the gate to the source was set to 1 m, the distance Lgd from the gate to the drain was set to 6 m, the first compound in the first region was Al.sub.0.05Ga.sub.0.95N (the Al composition ratio (x) was fixed at 0.05), and the second compound in the second region was Al.sub.xGa.sub.1xN (the Al composition ratio was a variable (x=0.23, x=0.4, x=0.6, x=0.8)).

[0033] FIG. 4 is an I-V curve diagram (linear plot) of a semiconductor power device of a simulation experiment example. FIG. 5 is an I-V curve diagram (logarithmic plot) of a semiconductor power device of a simulation experiment example. It can be seen from FIG. 4 and FIG. 5 that the higher the Al composition ratio (x), the greater the drain current. Therefore, the increase in the Al composition ratio (x) did have the effect of reducing the device resistance.

[0034] FIG. 6 is a schematic cross-sectional diagram of a semiconductor power device according to a second embodiment of the disclosure. The same reference numerals as the reference numerals used in the first embodiment are used to represent the same or similar parts and components, and reference can be made to the related content of the first embodiment for the same or similar parts and components and are not be repeated.

[0035] Referring to FIG. 6, the difference between a semiconductor power device 10b of the second embodiment and the first embodiment is that a barrier layer 110 has a notch 112 in a first region 110a, and the gate G is filled in the notch 112. The barrier layer 110 in the second embodiment also includes a first region 110a and a second region 110b outside the first region 110a. The source S and the drain D are respectively located on the second region 110b, and the gate G is located between the source S and the drain D and on the first region 110a. There is a first compound in the first region 110a and a second compound in the second region 110b. For the first compound and the second compound, reference can be made to the description of the first embodiment and the details are not be repeated. Due to the design of the notch 112, the distance between the gate G and the channel layer 102 is shorter, thereby reducing the channel resistance here, so that the two-dimensional electron gas 2DEG below the first region 110a is increased, and the on-resistance Ron is reduced. The semiconductor power device 10b of the second embodiment also belongs to the D-mode transistor.

[0036] FIG. 7 is a schematic cross-sectional diagram of a semiconductor power device according to a third embodiment of the disclosure. The same reference numerals as the reference numerals used in the second embodiment are used to represent the same or similar parts and components, and reference can be made to the related content of the second embodiment for the same or similar parts and components and are not be repeated.

[0037] Referring to FIG. 7, the difference between a semiconductor power device 10c of the third embodiment and the second embodiment is that a notch 114 is slightly larger than the notch (112) of the second embodiment, and there is a dielectric layer 116 between the barrier layer 110 and the gate G. The dielectric layer 116 can be a general dielectric layer, such as SiO.sub.2, SiON, or SiN; the dielectric layer 116 can also be a high dielectric coefficient (high-k) material, such as Al.sub.2O.sub.3, HfO.sub.2, ZrO.sub.2, or other suitable high-k materials. Due to the existence of the dielectric layer 116, the two-dimensional electron gas 2DEG is not generated below the first region 110a, so the semiconductor power device 10c belongs to an enhancement mode (E-mode) transistor, which is turned off in a normal state.

[0038] In the third embodiment, the manufacturing method of the semiconductor power device 10c includes, but is not limited to, after epitaxially growing the buffer layer 106, the channel layer 102, and the barrier layer on the substrate 100 (for example, fully forming the first compound), firstly forming a first patterned mask (not shown) on the surface of the barrier layer to cover the first region 110a, and then performing an aluminum (Al.sup.+) ion implantation process to dope the second region 110b outside the first region 110a with aluminum, so that the first compound in the second region 110b becomes a second compound with a larger aluminum composition ratio. Next, after removing the first patterned mask, a second patterned mask (not shown) is used to cover the second region 110b, and then etching is performed to form a notch 114. Then, after removing the second patterned mask, the dielectric layer 116 is formed on the surface of the barrier layer 110 (including the first region 110a and the second region 110b), and then the gate G is formed to fill the notch 114. Finally, the source S and the drain D are formed through the dielectric layer 116 to be in contact with the second region 110b.

[0039] FIG. 8 is a schematic cross-sectional diagram of a semiconductor power device according to a fourth embodiment of the disclosure.

[0040] Referring to FIG. 8, a semiconductor power device 20 of the fourth embodiment basically includes a substrate 200, a channel layer 202, a barrier layer 204, a gate G, an insulating layer 210, a source S, and a drain D. The substrate 200 can include, but is not limited to, SiC, Si, GaN, sapphire, Ga.sub.2O.sub.3, or polycrystalline aluminum nitride (poly-AlN). The channel layer 202 is located on substrate 200. In an embodiment, the channel layer 202 is, for example, GaN, InGaN, or Ga.sub.2O.sub.3 (or referred to as -Ga.sub.2O.sub.3). The barrier layer 204 is located on the channel layer 202 and has an opening 208. The barrier layer 204 is an aluminum compound. The aluminum compound includes an aluminum atom consisting of a first ratio and a gallium atom consisting of a second ratio. The second ratio represents that the gallium atom replaces a part of the aluminum atom, such as Al.sub.aGa.sub.(1a)N, Al.sub.aIn.sub.bGa.sub.(1ab)N, or (Al.sub.aGa.sub.1a).sub.2O.sub.3, where a<1 and (a+b)<1, and a represents the ratio of aluminum, b represents the ratio of indium, and each of 1a and 1ab represents different ratios of gallium. In addition, there is a buffer layer 206 or other functional film layers provided between the substrate 200 and the channel layer 202. For example, the buffer layer 206 can be AlN or AlGaN/GaN superlattice structure, or the like. The gate G is located on the barrier layer 204 and is filled in the opening 208. The insulating layer 210 is located between the gate G and the channel layer 202 and is in direct contact with the channel layer 202. The insulating layer 210 includes SiO.sub.2, SiON, SiN, or high dielectric coefficient (high-k) materials, such as Al.sub.2O.sub.3, HfO.sub.2, ZrO.sub.2, or other suitable high-k materials.

[0041] Continuing to refer to FIG. 8, each of the source S and the drain D is located on the barrier layer 204 on two sides of the gate G. The gate G, source S, and drain D each include Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, Pb, Ti/Al, Ti/Au, Ti/Pt, Al/Au, Ni/Au, or Au/Ni. In an embodiment, the material of the gate G is the same as the source S and the drain D; in another embodiment, the material of the gate G is different from the source S and the drain D. In addition, if the distance from the gate G to the drain D is greater than the distance from the gate G to the source S, the performance of the semiconductor power device 20 can be improved.

[0042] In summary, the disclosure increases the aluminum composition ratio of the compound in the region outside the gate through ion implantation, thereby increasing the electron concentration of the two-dimensional electron gas (2DEG) of the region and reducing the on-resistance (Ron) of the overall device. Whether it is a GaN-based semiconductor power device or a semiconductor power device using Ga.sub.2O.sub.3, doping with an aluminum ion can effectively reduce the on-resistance of the device, and especially improving the electron mobility of -Ga.sub.2O.sub.3 and solving the problem of heat accumulation. In other words, doping the aluminum ion to form a ratio of aluminum compounds in semiconductor power devices is critical to the development of gallium oxide power devices. In addition, the disclosure can appropriately reduce the aluminum composition ratio of the compound in the region below the gate to avoid an increase in barrier layer stress, thereby improving the reliability of the gate. In addition, the semiconductor power device of the disclosure can be a depletion mode (D-mode) transistor or an enhancement mode (E-mode) transistor, and so has wider applicability.

[0043] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In diagram of the forwarding, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.