GIANT FERROELECTRIC AND OPTOELECTRONIC RESPONSES OF FIELD EFFECT TRANSISTORS BASED ON MONOLAYER SEMICONDUCTING TRANSITION METAL DICHALCOGENIDES
20250072159 ยท 2025-02-27
Assignee
- California Institute Of Technology (Pasadena, CA)
- National Taiwan Normal University (Taipei City, TW)
Inventors
- Nai-Chang Yeh (Pasadena, CA, US)
- Duxing Hao (Pasadena, CA, US)
- Yann-Wen Lan (Taipei, TW)
- Ting-Hua Lu (Taipei, TW)
Cpc classification
G01R33/1284
PHYSICS
International classification
H01L31/0352
ELECTRICITY
H01L31/032
ELECTRICITY
Abstract
A field effect transistor including a substrate; a monolayer of a single crystal semiconducting transition metal dichalcogenide (TMD) on the substrate; a source contact and a drain contact to the strained monolayer; and a gate contact on the substrate; wherein the a gate voltage applied to the gate contact with respect to the source contact modulates a ferroelectric response of the monolayer when strained and a current through the monolayer between the source contact and the drain contact; and wherein the substrate is rigid and the monolayer experiences asymmetric lattice expansion when strained against the rigid substrate in response to an external magnetic field or the substrate is a strain engineered substrate inducing asymmetric lattice expansion of the monolayer.
Claims
1. A device, comprising: a field effect transistor, comprising a substrate; a monolayer of a single crystal semiconducting transition metal dichalcogenide (TMD) on the substrate; a source contact and a drain contact to the strained monolayer; and a gate contact on the substrate; wherein the a gate voltage applied to the gate contact with respect to the source contact modulates a ferroelectric response of the monolayer when strained and a current through the monolayer between the source contact and the drain contact; and wherein: the substrate is rigid and the monolayer experiences asymmetric lattice expansion when strained against the rigid substrate in response to an external magnetic field perpendicular to a surface of the monolayer and when cooled below 20 degrees Kelvin, or the substrate is a strain engineered substrate inducing asymmetric lattice expansion of the monolayer.
2. A system further comprising the device of claim 1, the system further comprising a controller; a magnetic field source for outputting a magnetic field across a thickness of the monolayer; and a cryogenic cooling system for cooling the field effect transistor to a temperature below 20 Kelvin (or below the Curie temperature), wherein the controller controls the magnetic field and the temperature to tune the ferroelectric response.
3. The system of claim 1, further comprising a source of twisted electromagnetic radiation coupled to the field effect transistor, further comprising controller controls at least one of a wavelength, polarization, spin, or orbital angular momentum of the electromagnetic radiation to tune or modulate the ferroelectric response and/or a photocurrent generated between the drain the source in response to the twisted electromagnetic radiation.
4. A detector of twisted electromagnetic radiation, comprising the device of claim 1 coupled to a circuit for measuring the ferroelectric response (shape or size or magnitude of the hysteresis loop) and determining, from the ferroelectric response, a spin or orbital angular momentum state (e.g., which s or l state) of the twisted electromagnetic radiation incident on the monolayer.
5. An optoelectronic transducer or modulator comprising the device of claim 1, wherein the current is modulated with a spin or orbital angular momentum state of twisted electromagnetic radiation incident on the monolayer.
6. The device of claim 1, wherein the gate voltage is in a range of 0.1 Vup to a maximum voltage limited by dielectric leakage of layer in the substrate, the magnetic field is in a range of 0.1 T to 12-T, and the temperature is in a range of 1-20 Kelvin.
7. The device of claim 1, wherein the ferroelectric response is characterized by a hysteresis in the current between the drain and source as a function of the gate voltage, wherein the hysteresis onset is at lower voltages for higher magnetic fields and lower temperatures.
8. The device of claim 1, wherein the TMD comprises MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2 or an alloy thereof.
9. The device of claim 1, wherein the monolayer comprises a top chalcogenide layer, a bottom chalcogenide layer, and a transition metal between the chalcogenide layers, and the monolayer is under strain as characterized by measuring a different (larger) lattice expansion in the top chalcogenide layer as compared to the bottom chalcogenide layer.
10. The device of claim 9, wherein the strain engineered substrate comprises an array of nanostructures protruding on the substrate, wherein the monolayer in direct contact with the nanostructures conforms to a contour of the nanostructures to form the strain.
11. The device of claim 10, wherein the nanostructures each comprise a tetrahedron with a rounded top.
12. The device of claim 10, wherein the strain engineered substrate comprises a transition metal dichalcogenide.
13. The device of claim 1, wherein the substrate comprises a dielectric layer and the gate contact is on a backside of the substrate to apply the gate voltage across the dielectric layer.
14. The device of claim 13, wherein the dielectric comprises a silicon dioxide layer on the doped silicon substrate.
15. An optical detector, a memory, or magnetic sensor comprising the device of claim 1.
16. A method of making a device, comprising: growing a monolayer of a single crystal semiconducting transition metal dichalcogenide (TMD) on a first substrate; transferring the monolayer to a second substrate; depositing a source contact; a drain contact; and a gate contact to the monolayer; coupling a first circuit to apply a gate voltage to the gate contact with respect to the source contact and a source-drain voltage between the source contact and the drain contact; and coupling a second circuit to measure a ferroelectric response of the monolayer when strained.
17. A method of using a device, comprising: straining a monolayer of TMD as an active region of a field effect transistor; and measuring a ferroelectric response of the monolayer.
Description
BRIEF DESCRIPTION OF DRAWINGS
[0013] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.
[0014] Referring now to the drawings in which like reference numbers represent corresponding parts throughout:
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DETAILED DESCRIPTION OF THE INVENTION
[0039] In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized, and structural changes may be made without departing from the scope of the present invention.
Technical Description
First Embodiment: Ferroelectric Response Using Rigid Substrates and Applied Magnetic Field
1. Device Structure
[0040] In one embodiment, giant ferroelectric-like hysteresis is induced by out-of-plane magnetic field (B) applied to a field-effect transistors (FETs) comprising a monolayer (ML) MoS.sub.2 single crystals on SiO.sub.2/Si substrates at temperatures (T) below 20 K.
[0041]
[0042] The source-drain voltage (V.sub.DS) was applied between a pair of bismuth (Bi)/gold (Au) contacts, and the gate voltage (V.sub.GS) was applied between the source contact and a heavily p-doped Si substrate with a 30 nm-thick SiO.sub.2 insulating layer. The 1HMoS.sub.2 single crystals (a.k.a. ML-MoS.sub.2 with the 2H-phase) grown by chemical vapor deposition (CVD).sup.22-24 exhibited high degrees of homogeneity after fabrication, as verified by their optical spectroscopic characterizations exemplified in
[0043] Additionally, nearly ohmic source-drain current (I.sub.DS) versus gate voltage (V.sub.GS) transfer curves were observed down to 1.8 K (
[0044] The counterclockwise hysteresis of the source-drain current (I.sub.DS) as a function of the back-gate voltage (V.sub.GS) can be enhanced by increasing the maximum V.sub.GS value, increasing |B|, and lowering T. These findings differ drastically from previous reports of high-temperature and zero-B hysteretic behavior in ML-MoS.sub.2 FETs, which have been attributed to mechanisms such as thermally-activated trapped states.sup.18-20, absorbates.sup.4,5, and ordinary gate voltage-induced stress effects.sup.21, where clockwise hysteresis loops were observed near room temperatures without magnetic field dependences.
[0045] The hysteresis in the source drain current is associated with the ferroelectric response of the device after confirmation that the monolayer is indeed ferroelectric by measuring hysteresis in the polarization as a function of applied electric field (e.g., generated by applying the gate voltage across the monolayer). More specifically, piezo-response force microscopy was used to measure ferroelectric response by observing a polarization loop under the same magnetic field conditions (see
[0046] Scanning Tunneling Microscopy (STM) measurements of the monolayer on a conducting substrate (consisting of a piece of highly oriented pyrolytic graphite, HOPG) confirmed the ferroelectric response is associated with lattice expansion induced by the magnetic field (in all directions and in plane and out of plane), which was also corroborated using Raman spectroscopy. This expansion becomes asymmetric when the monolayer MoS.sub.2 is placed on a rigid substrate like SiO.sub.2/Si so that the top and bottom layers of dichalcogenide expanding differently, which is in contrast to the situation of placing monolayer MoS.sub.2 on another van der Waals material like HOPG or hexagonal boron nitride (h-BN) that would accommodate the lattice expansion of monolayer MoS.sub.2, as schematically illustrated in
[0047] Further information on the characterization is discussed in the following sections.
2. Characterization of Emerging Electric Hysteretic in MoS.SUB.2.-FETs
[0048] Under an out-of-plane magnetic field (B), counterclockwise |I.sub.DS|-vs.-V.sub.GS hysteretic loops emerged from measurements of the FET devices at 1.8 K, as exemplified in
[0049] When sweeping up V.sub.GS, the system was initially in the high-resistance state (HRS).sup.26, showing |I.sub.DS|>0 for V.sub.GS>V.sub.th,H, where V.sub.th,H denoted the threshold voltage for the forward branch defined in Methods. In contrast, when V.sub.GS was reduced from a finite |I.sub.DS| state, the lattice returned from a highly polarized low-resistance state (LRS).sup.7,26 so that |I.sub.DS| remained finite until V.sub.GS reached V.sub.th,L (<V.sub.th,H), where V.sub.th,L represented the threshold voltage for |I.sub.DS|>0 in the returned branch. Within the applicable range of V.sub.GS up to 36 V in all devices (Dev. #1-#5), none of the hysteresis loops became fully closed within our experimental parameters due to limited gating range and the necessity of keeping the leakage current small (Methods). We found that |I.sub.DS| continued to increase upon reversing V.sub.GS from 20 V to 16 V (
[0050] Overall, the following key findings were consistently observed across five different devices (
[0051] In addition to magnetic field, gate voltage and temperature may be used to modulate this hysteresis, although less significant than the magnetic field.
3. Characterization of Magnetic Field Induced MoS.SUB.2 .Lattice Expansion
[0052] To elucidate the physical origin for magnetic field-induced hysteresis in these ML-MoS.sub.2 FETs, we carried out cryo-temperature Raman spectroscopic studies of ML-MoS.sub.2 on silicon substrates, as shown in
[0053] Further evidence for magnetic field-induced lattice expansion was manifested by scanning tunneling microscopic (STM) studies of a ML-MoS.sub.2 sample grown in situ on highly ordered pyrolytic graphite (HOPG). The filtered ML-MoS.sub.2/HOPG topographic images (Methods,
[0054] A plausible explanation for our observation of magnetic field-induced giant hysteretic behavior is due to a bistable ferroelectric-like spontaneous out-of-plane polarization, which emerges under anisotropic lattice expansion-induced flexoelectric effect.sup.35 due to the TEC mismatch between ML-MoS.sub.2 and the underlying rigid SiO.sub.2/Si substrate.sup.27,3536, as shown in
[0055] Overall, our experimental findings from five distinct FET devices of ML-MoS.sub.2 on SiO.sub.2/Si suggested that the out-of-plane magnetic field-induced ferroelectric-like counterclockwise hysteresis was robust at low temperature and reversible upon removing the magnetic field, and the absence of such phenomena in two buffered FET devices of ML-MoS.sub.2 on h-BN/SiO.sub.2/Si further accentuated the important role of substrates in inducing the anisotropic magnetic field-induced lattice expansion, which was essential for the out-of-plane electric polarization. The magnetic field-induced lattice expansion in ML-MoS.sub.2 at low temperatures is likely associated with the occurrence of a magnetic field-induced structural phase transformation, although the microscopic mechanism and the nature of this phase transformation remain unclear. A possibility may be related to lifting the valley degeneracy in ML-MoS.sub.2 by magnetic field due to strong spin-valley coupling, thereby resulting in a real-space structural transformation. Additionally, the correlation between the size of hysteresis (V.sub.HW) and the magnitude of out-of-plane magnetic field (|B|) is suggestive of multiferroic-like behavior. Overall, a careful ab initio calculation that takes into consideration of the effects of magnetic field, temperature, sulfur vacancies, and substrate will be necessary to fully account for our observation and to unravel the underlying physical mechanism, which is beyond the current scope of our work. Regardless of the microscopic physical origin, the giant magnetic-field induced ferroelectric-like responses in the ML-MoS.sub.2 FET devices exhibited strong stability and reproducibility, thus promising for such technological applications as cryo-temperature ultracompact non-volatile memories, memtransistors, and ultrasensitive magnetic field sensors.
4. Supplementary Information on Device Fabrication Methods
[0056] Monolayer (ML) MoS.sub.2 samples were synthesized on sapphire substrates by chemical vapor deposition (CVD).sup.22-24. Standard PMMA-assisted wet transfer technique was used to transfer MoS.sub.2 single crystals from sapphire substrates to standard Si/SiO.sub.2 (90 nm oxide thickness) substrates using ammonia solution. PMMA residue and surface contamination was then removed by acetone/isopropanol, which was followed by N-methyl-2-pyrrolidone (NMP) solution. Electrical contacts consisting of 20 nm Bi and 50 nm Au were made by e-beam lithography and thermal evaporation.
5. Supplementary Information on Device Characterization
a. Methods
[0057] The electrical transport characterization of the devices was carried out using Physical Property Measurement System (PPMS) by Quantum Design in a vacuum (<10 mTorr) cryostat, which allowed a tunable temperature ranging from 1.8 K to 400 K and a maximum tunable magnetic field of 14 T. The device was annealed at 400 K under vacuum overnight to remove possible water and oxygen adsorbates.sup.20,40. All electrical transport measurements were conducted under the DC condition with the source-measuring units Keithley 2636B/2450. The gate voltage V.sub.GS was kept below 24 V to ensure the leakage current staying below 0.1 nA, and the V.sub.GS sweep rate of 0.044 V/s or slower was found to produce consistent hysteresis loops, hence the sweep rate of 0.044 V/s or slower was used for all hysteresis measurements unless otherwise specified.
[0058] The optical characterization of the MoS.sub.2 devices was carried out under T=4.5 K 300 K temperature control with an out-of-plane magnetic field B up to 0.5 T. A 532 nm continuous-wave laser was used as an excitation source, which was focused on the sample for optical characterization with a 50 objective lens (NA=0.5). The temperature-dependent and magnetic field-dependent Raman (1200 lines/mm) and PL (150 lines/mm) spectra were measured by a ANDOR Kymera 328i spectrometer.
[0059] The scanning tunneling microscopy (STM) studies were carried out on ML-MoS.sub.2 samples, grown in situ by CVD on cleaved HOPG substrate, at a vacuum base pressure of 210.sup.10 Torr (See Note 8). The topography measurements of the moir superlattice patterns were obtained with a bias voltage of 0.7 V and a constant current of 2 nA.
b. Note 1: Basic Characterization of Devices
[0060]
[0061] Most FET devices studied in this work exhibited an ohmic-like low contact barrier behavior.sup.3,4 in the I.sub.DS-vs.-V.sub.DS curves from 300 K to 1.8 K under different V.sub.GS values, as exemplified in
c. Note 2: Ohmic-Like Low Contact-Barrier MoS.sub.2 FET Device Characterization
[0062] Bi/Au contact is known for having low contact barrier and ohmic behavior down to 77 K.sup.4. Our study followed the same methodology and showed that our devices had an ohmic-like behavior at 300 K and a near-ohmic behavior at 1.8 K, as exemplified in
[0063] where A.sub.2D*=q(8k.sub.B.sup.3m*/h.sup.2) is the Richardson constant for a 2D system, E.sub.A=q.sub.B is the Schottky barrier height under the flat-band condition (
[0064] where C.sub.g=.sub.0.sub.r/d is the capacitance per unit area, .sub.r and d are the relative dielectric constant and the thickness of the SiO.sub.2 layer, respectively. For a single-crystal device, the length to width ratio (L/W) was estimated to be 1.38 for Device #1 based on optical measurements. The mobility for Device #1 thus estimated 2 cm.sup.2V.sup.1S.sup.1 at 300 K and 7 cm.sup.2V.sup.1S.sup.1 at 1.8 K. This value is within range of previously reported mobility range between 0.1-10 cm.sup.2V.sup.1S.sup.1 over exfoliated ML-MoS.sub.2 devices on typical Si/SiO.sub.2 substrates.sup.5-7.
d. Supplementary Information on Extracting the Hysteresis Window V.sub.HW
[0065] The threshold voltages V.sub.th, H and V.sub.th, L were extracted by first fitting the linear region of the HRS (forward branch) and LRS (backward branch) of the |I.sub.DS|-vs.-V.sub.GS transfer curves respectively, then finding their corresponding x-axis intercepts. The hysteresis window V.sub.HW was then given by V.sub.HWV.sub.th, HV.sub.th, L and was largely independent of V.sub.DS, as shown in
e. Note 3: Discussion on Various Known Hysteresis-Inducing Mechanisms
[0066] We reviewed possible mechanisms that were previously identified in the literature and were fundamentally different from the hysteresis behavior that we observed in the |I.sub.DS|-vs.-V.sub.GS transfer curves reported in this work.
[0067] Firstly, our findings differ drastically from previous reports of high-temperature and zero-B hysteretic behavior in monolayer MoS.sub.2-FETs, which have been attributed to mechanisms such as thermally-activated extrinsic or intrinsic trapped states.sup.8-10, absorbates.sup.11,12, and gate voltage-induced stress effects.sup.13, where clockwise hysteresis loops were observed near room temperatures without magnetic field dependences. We have also observed similar gate voltage stress type of clockwise hysteresis at higher temperature above T.sub.C, as detailed in Note 7.
[0068] At temperature below 4.2K, the presence of Schottky barrier between Cr/Au contact and MoS.sub.2 can induce counterclockwise hysteresis in |I.sub.DS|-vs.-V.sub.GS transfer curves.sup.14. However, this type of hysteresis bears signature of a sharp rise in I.sub.DS upon uncertain onset V.sub.GS and the V.sub.HW is larger with increasing V.sub.GS sweep rates, contrary to our observations shown in
[0069] Sulfur vacancies that exist in all MoS.sub.2 FETs, as we discussed in the manuscript, could induce shallow donor-like trap states.sup.16, deep trap states above the valence band maximum.sup.16,17, or charge trapping at the oxide interfaces.sup.10,12. However, all of which would have led to magnetic field-independent clockwise hysteresis at relatively high temperatures, which contradicted to our magnetic field-dependent counterclockwise hysteresis at cryo-temperatures. In-plane motion of sulfur vacancies has been shown to introduce in-plane ferroelectricity with counterclockwise hysteresis loops.sup.18. However, this scenario differs from our findings of negligible in-plane electric-field driven hysteresis and requires artificial creation of sulfur vacancies via focused ion beam. Finally, interlayer motion of sulfur vacancies would have been energetically too costly to occur at low temperatures. Thus, we may rule out vacancy-induced trap states as well as in-plane ferroelectricity as the cause of this magnetic-field induced hysteresis at cryo-temperatures.
[0070] Flexoelectric effect could also manifest themselves as counterclockwise hysteresis as a result of strain gradient.sup.19. However, such polarization relies on the strain gradient that is non-switchable, thus incompatible with our PFM results.
[0071] As for piezoelectric effect, it has been reported that the in-plane piezoelectric coefficient are much larger than the out-of-plane one.sup.19,20, thus less likely being the cause for our findings of V.sub.HW being mostly due to out-of-plane electric field and almost independent of the in-plane electric field.
[0072] In summary, we have ruled out all known mechanisms reported in the literature and thus demonstrated the novelty of our findings of magnetic field-induced hysteresis.
f. Note 4: Further Characterization of Hysteresis Window
[0073] As shown in
[0074] The frequency response of the hysteresis window is also studied and shown in
g. Note 5: Low-Temperature Magnetic Field-Dependent Electronic Transport Data on Additional Devices
[0075]
[0076] Magnetoresistance measurements of Device #5 are shown in
[0077]
h. Note 6: Magnetic Field-Independent Clockwise Hysteresis Above T.sub.C
[0078] Above T.sub.C, thermally activated and magnetic field-independent negative V.sub.HW (clockwise hysteresis) was observed due to gate voltage.sup.13 stress and SiO.sub.2MoS.sub.2 interfacial trapping states.sup.8,9, as exemplified in
i. Note 7|Additional Temperature-Dependent Measurements
[0079]
J. Note 8|Temperature Dependent Raman Spectroscopy
[0080] Temperature dependent Raman spectroscopy result is shown in
k. Note 9|Notes on Scanning Tunneling Microscopy Studies
Scanning Tunneling Microscopy on HOPG/MoS.SUB.2 .Moir Superlattice
[0081] The ML-MoS.sub.2 sample for STM measurements was synthesized by CVD on an in situ cleaved HOPG substrate. The as-grown sample was then outgassed in situ at a temperature of 800 K and a vacuum of 210.sup.10 Torr for an hour before measurements. The ML-MoS.sub.2/HOPG sample was then transferred to an STM chamber and measured at 4.5 K under various magnetic fields using an electrochemical-etched tungsten tip, whose quality was verified by test measurements on Au (111) surface states. Further STM calibration was done by scanning on pure HOPG areas of the sample at 4.5 K prior to the study of sample area covered by a ML-MoS.sub.2. Due to the lattice constant mismatch as well as a small twist angle between HOPG and the as-grown ML-MoS.sub.2, moir superlattice patterns were observed in the STM topography. As shown in
Extracting the ML-MoS.sub.2 Lattice Expansion from Moir Patterns
[0082] Moir patterns are very sensitive to the lattice mismatch between ML-MoS.sub.2 and the underlying HOPG, hence served as an excellent tool to accurately determined the MoS.sub.2 lattice expansion by studying the STM topography of the same sample area under various constant magnetic fields. As exemplified in
Theoretical Modeling for Deriving the MoS.sub.2 Lattice Expansion from Varying Moir Patterns
[0083] Since the lattice constant of HOPG remains constant under magnetic field.sup.25, the lattice match () caused by magnetic field may be solely attributed to the changes in the ML-MoS.sub.2 lattice constant so that =(a.sub.G+a.sub.M+a)/a.sub.G, where a.sub.G=0.246 nm and a.sub.M=0.318 nm are the lattice constant of HOPG and ML-MoS.sub.2 under zero magnetic field, respectively, and a is the ML-MoS.sub.2 lattice expansion under a finite magnetic field.sup.26. Given the twist angle () between HOPG and MoS.sub.2, the expected moir pattern periodicity () becomes
1. Note 10|Low Temperature Piezo-Response Force Microscopy (PFM) Measurements
[0084] To study the hysteresis behavior of ML-MoS.sub.2 flakes on SiO.sub.2/Si substrate under magnetic fields, piezo-response force microscopy (PFM) measurements were carried out at magnetic field strengths of B=0 and B=3 T at a temperature of 1.6 K, as shown in
[0085] The hysteresis measurements using piezo-response force microscopy (PFM) were conducted utilizing a commercial cryogenic scanning probe microscope system (attoAFM I, Attocube) equipped with a closed-cycle cryostat (attoDRY 2100 with 9 T magnet, Attocube) operating at 1.6 K. A commercial platinum silicide (PtSi) coated tips with a spring constant of 2.8 N/m (NANOSENSORS PtSi-FM) was used to assess hysteresis, driven by a V.sub.RMS=1.5 V ac voltage at a contact-resonance frequency of about 300 kHz. Off-field hysteresis loops were obtained by switching spectroscopic techniques under pulse sequences generated by an arbitrary waveform generator (G5100A, Picotest).
m. Note 11|Characterizing the Sulfur Vacancy Concentration
[0086] The sulfur vacancies in ML-MoS.sub.2 may play an important role in our devices.
[0087] Therefore, a typical FET device (Dev. #5), which we believed to possess representative sulfur vacancy concentrations, was studied using Kelvin probe force microscopy (KPFM), as shown in
[0088] The work function of the ML-MoS.sub.2 was measured by the Peak Force Kelvin Probe Force Microscopy (PF-KPFM) calibrated with respect to the work function of gold at 4.82 eV.sup.4. The contact potential difference (CPD) between the tip and the sample is given by V.sub.CPD=.sub.sample.sub.tip, where is the work function. Therefore, the work function of the ML-MoS.sub.2 sample becomes:
[0089] where V.sub.CPD.sup.MoS.sup.
[0090] where k.sub.B is Boltzmann constant, T is the temperature, n.sub.i, are the intrinsic electron concentration of MoS.sub.2. With n.sub.i10.sup.6 cm.sup.2 at room temperature.sup.27 and measured E.sub.FE.sub.i=0.4 eV, the corresponding electron concentration of the MoS.sub.2 sample was estimated as n 4.810.sup.12 cm.sup.2. Assuming those electrons were induced by sulfur vacancies, the order of magnitude of sulfur vacancy population density can be estimated as na.sup.2{square root over (3)}/40.2%, where a=0.318 nm is the lattice constant of MoS.sub.2.
n. Note 12|Transport Studies on h-BN Buffered MoS.sub.2 FETs
[0091] To investigate the role of substrate and strain induced by the mismatching thermal expansion coefficient between SiO.sub.2 substrate and MoS.sub.2, we fabricated ML-MoS.sub.2 FETs with a buffer layer of 5 nm h-BN. The electrical transport results, as exemplified in
Second Embodiment: FET on Strain Engineered Substrate
[0092] The measured correlation between asymmetric lattice expansion of the monolayer MoS.sub.2 and the resulting ferroelectric response suggests that a strain engineered substrate can also be used to generate the ferroelectric response in the absence of magnetic field.
[0093] Thus, in another embodiment illustrated in
Third Embodiment: FET as a Detector or Modulator/Transducer
[0094] In yet another embodiment, a detector of twisted electromagnetic radiation (e.g., righthanded/lefthanded circularly polarized light, RCP/LCP light, and linearly polarized light, LP light) can be fabricated by coupling the FET to a circuit or other means for measuring the ferroelectric response and determining, from the ferroelectric response, a spin or orbital angular momentum state (e.g., which s or l state) of the twisted electromagnetic radiation incident on the monolayer.
[0095] An optoelectronic transducer or modulator, e.g., useful in a communications system, for example, can also be fabricated by coupling a source of twisted electromagnetic radiation to the FET so that the twisted electromagnetic radiation incident on the monolayer modulates the current with a spin or orbital angular momentum state of twisted electromagnetic radiation (e.g., such that spin or OAM state is transferred to the electrical current carrying the spin or orbital momentum state of the electromagnetic radiation).
[0096] These devices can be used to decode information carried by light, or in light controlled/gated electronics applications, for example.
Process Steps
[0097]
[0098] Block 2300 represents growing a monolayer (ML) of TMD on a appropriate (e.g., sapphire) substrate, e.g., by chemical vapor deposition.
[0099] Block 2302 represents transferring the monolayer to a doped substrate suitable for gating the device In one or more examples, standard PMMA-assisted wet transfer technique can be used.
[0100] Block 2302 represents depositing source, drain, and gate contacts.
[0101] Block 2304 represents the end result, a device according to one or more embodiments.
[0102] The device can be embodied in many ways including, but not limited to, the following (referring to
[0103] 1. A device 100, 2100 comprising: [0104] a field effect transistor, comprising [0105] a substrate 102; [0106] a monolayer of a single crystal semiconducting transition metal dichalcogenide (TMD) 104 on the substrate; [0107] a source contact 106 and a drain contact 108 to the strained monolayer; and [0108] a gate contact 110 on the substrate; wherein the a gate voltage V.sub.GS applied to the gate contact with respect to the source contact (or drain contact, or the channel) modulates a ferroelectric response of the monolayer when strained and a current through the monolayer between the source contact and the drain contact; and wherein: [0109] the substrate is rigid and the monolayer experiences asymmetric lattice expansion when strained against the rigid substrate in response to an external magnetic field perpendicular to a surface of the monolayer and when cooled below 20 degrees Kelvin, or [0110] the substrate is a strain engineered substrate 2108 inducing asymmetric lattice expansion 2112 of the monolayer.
[0111] 2. A system 200 further comprising the device of embodiment 1, the system further comprising a controller 202; a magnetic field source 204 (e.g., magnet, electromagnet) for outputting a magnetic field across a thickness of the monolayer; and a cryogenic cooling system 206 (e.g., cryostat) for cooling the field effect transistor to a temperature below 20 Kelvin (or below the Curie temperature), wherein the controller controls the magnetic field and the temperature to tune the ferroelectric response.
[0112] 3. The system of embodiment 1 or 2, further comprising a source 208 (e.g., a laser, light emitting device/diode) of twisted electromagnetic radiation coupled to the field effect transistor, further comprising controller controls at least one of a wavelength, polarization, or spin (e.g., s=+1 or 1) and orbital angular momentum (l=+2, +1, 0, 1, 2) of the electromagnetic radiation to tune or modulate the ferroelectric response and/or a photocurrent generated between the drain the source.
[0113] 4. A detector of twisted electromagnetic radiation, comprising the device of any of the embodiments 1-3 coupled to a circuit 202 for measuring the ferroelectric response (shape or size or magnitude of the hysteresis loop) and determining, from the ferroelectric response, a spin or orbital angular momentum state (e.g., which s or l state) of the twisted electromagnetic radiation incident on the monolayer.
[0114] 5. An optoelectronic transducer or modulator comprising the device of any of the embodiments 1-4, wherein the current is modulated with a spin or orbital angular momentum state of twisted electromagnetic radiation incident on the monolayer (e.g., as may be useful in a communication system).
[0115] 6. The device of any of the embodiments 1-5, wherein the gate voltage is in a range of 0.1 Vup to a maximum voltage limited by dielectric leakage of the substrate, the magnetic field is in a range of 0.1 T to 12-T, and the temperature is in a range of 1-20 K.
[0116] 7. The device of any of the embodiments 1-6, wherein the ferroelectric response is indirectly inferred by a hysteresis 210 in the current between the drain contact and source contact as a function of the gate voltage, wherein the hysteresis onset is at lower voltages for higher magnetic fields and lower temperatures. Polarization (force response to polarization measured using atomic force microscopy) as a function of applied gate voltage is a direct measurement of the polarization hysteresis associated with ferroelectricity, which has also been carried out as shown in
[0117] 8. The device of any of the embodiments 1-7, wherein the TMD comprises MoS.sub.2, MoSe.sub.2, WS.sub.2, WSe.sub.2 or an alloy thereof. Example alloys include, but not limited to, these compounds with S partially substituted with Se, Mo partially substituted with W, or S partially substituted with Te, so long as the monolayer remains in a semiconductor phase (not semimetal).
[0118] 9. The device of any of the embodiments 1-8, wherein the monolayer comprises a top chalcogenide layer 2102, a bottom chalcogenide layer 2104; a transition metal layer 2106 between the chalcogenide layers, wherein the monolayer is under strain as characterized by measuring a different (e.g., greater) lattice expansion 2112 (using STM or Raman spectroscopy for example) induced by magnetic field or other straining mechanism, for the top layer as compared to the top layer. The expansion can comprise a ripple 2114 or undulation of the layers, wherein the top layer experiences larger amplitude ripples than the bottom layer.
[0119] 10. The device of any of the embodiments 1-9, comprising low doping (e.g., less than 1%, e.g., 0.2% sulfur vacancies). In some embodiments, random doping with lots of vacancies impairs or weakens the mechanical response/elastic modulus, thereby inhibiting appearance of the ferroelectric response. In some embodiments, hysteresis disappears for more than 1% vacancies.
[0120] 11. The device of any of the embodiments 1-10, wherein the strain engineered substrate 2108 further comprises an array of nanostructures or protrusions 2110 (e.g., nanodots, e.g., having a height and width in a range of 1-1000 nanometers) protruding on the substrate, wherein the monolayer in direct contact with the nanostructures conforms to a contour of the nanostructures so as to cause the asymmetric lattice expansion of the top and bottom layers (as evidenced by simulation). The height of each nanostructure may range from 1 nm to 10 nm, and the lateral dimension of each nanostructure may range from 5 nm to 50 n
[0121] 12. The device of embodiment 11, wherein the array comprises a periodic array of the nanostructures or protrusions across an entire surface area of the monolayer, so as to contribute uniform asymmetric strain across the monolayer. The nanostructures or protrusions are spaced not too far apart (so that the strain is not too weak) nor so densely that the monolayer would crack.
[0122] 13. The device of embodiment 11 or 12, wherein the nanostructures or protrusions each may comprise a tetrahedron (as an example) with a rounded top (to prevent cracking) and with one of its edges along the zig zag (x-axis) of the monolayer. However, any protrusion that doesn't cause breaking and provides enough strain can be used.
[0123] 14. The device of any of the embodiments 1-13, wherein the substrate comprises a dielectric layer and the gate contact is on a backside of the substrate to apply the gate voltage across the dielectric layer.
[0124] 15. The device of any of the embodiments 1-14 wherein the rigid substrate is silicon dioxide on silicon or other substrate that is rigid as compared to the monolayer, so that it does not move with the monolayer, or such that lattice expansion or contraction of the substrate is much less than the monolayer under application of the magnetic field. In some embodiments, the rigid substrate has a mechanical modulus much stronger (e.g., at least 10 times larger) than the monolayer.
[0125] 16. The device of any of the embodiments 1-15, wherein the dielectric comprises a silicon dioxide layer on the doped silicon substrate or other material allowing application of a gate voltage across its thickness.
[0126] 17. The device of any of the embodiments 1-16, wherein the strain engineered substrate comprises a monolayer of semiconducting TMD (e.g., as described herein) with the protrusions.
[0127] 18. An optical detector, a memory, or sensitive magnetic sensor (at low temperatures below 20K) comprising the device of any of the embodiments 1-17.
[0128] 19. The device of any of the embodiments 1-18, wherein other rigid semiconducting substrates potentially usable for the ML-TMD ferroelectric FETs may be based on III-V semiconductors such as GaAs and InGaAs, which may be doped with Al, and may use Al.sub.2O.sub.3 as the dielectric layer. Generally GaAs and related III-V compounds are excellent substrates for optical devices and may also be used for strain engineering.
[0129] 20. The device of any of the embodiments 1-19 wherein the monolayer comprises a top chalcogenide layer 2102, a bottom chalcogenide layer 2104; a transition metal layer 2106 between the chalcogenide layers.
[0130]
[0131] Block 2400 represents interacting the monolayer TMD of the FET with a magnetic field or electromagnetic field.
[0132] Block 2402 represents measuring a (an out of plane) ferroelectric response of the monolayer in the FET in response to the magnetic field or electromagnetic field. The ferroelectric response can be measured from a hysteresis in the source drain current as a function of applied gate voltage, after confirmation of the ferroelectricity by measuring polarization as a function of applied electric field.
[0133] The method of
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CONCLUSION
[0203] This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.