INFRARED LED ELEMENT

Abstract

An infrared LED element includes: a conductive support substrate; and a semiconductor laminate and includes a material that can be lattice-matched with InP, in which the semiconductor laminate includes: a first semiconductor layer indicating a first conductivity type; an active layer disposed on an upper layer of the first semiconductor layer; a second semiconductor layer disposed on an upper layer of the active layer and indicating a second conductivity type; and a third semiconductor layer disposed on an upper layer of the second semiconductor layer and contains Al.sub.aGa.sub.bIn.sub.cAs indicating the second conductivity type, the third semiconductor layer has an uneven part on a surface opposite to a side on which the second semiconductor layer is positioned, and the third semiconductor layer has band gap energy lower than band gap energy of the second semiconductor layer and higher than band gap energy of the active layer.

Claims

1. An infrared light-emitting diode (LED) element that can emit infrared light having a peak wavelength of 1,000 nm to 2,000 nm, the infrared LED element comprising: a support substrate having conductivity; and a semiconductor laminate disposed on an upper layer of the support substrate and includes a material that can be lattice-matched with indium phosphide (InP), wherein the semiconductor laminate includes: a first semiconductor layer disposed on a side closest to the support substrate and indicating a first conductivity type; an active layer disposed on an upper layer of the first semiconductor layer; a second semiconductor layer disposed on an upper layer of the active layer and indicating a second conductivity type different from the first conductivity type; and a third semiconductor layer disposed on an upper layer of the second semiconductor layer and including Al.sub.aGa.sub.bIn.sub.cAs (0a<1, 0<b<1, 0<c<1, a+b+c=1) indicating the second conductivity type, the third semiconductor layer has an uneven part on a surface opposite to a side on which the second semiconductor layer is positioned, and the third semiconductor layer has band gap energy lower than band gap energy of the second semiconductor layer and higher than band gap energy of the active layer.

2. The infrared LED element according to claim 1, wherein the second semiconductor layer includes indium phosphide (InP).

3. The infrared LED element according to claim 1, wherein the third semiconductor layer has a thickness of 1 m to 5 m.

4. The infrared LED element according to claim 1, further comprising a first electrode disposed in contact with a part of an upper surface of the third semiconductor layer, wherein the third semiconductor layer has a dopant concentration higher than a dopant concentration of the second semiconductor layer and is 510.sup.17/cm.sup.3 or more.

5. The infrared LED element according to claim 4, wherein the second semiconductor layer has a dopant concentration of 510.sup.17/cm.sup.3 or more, and the third semiconductor layer has a dopant concentration of 110.sup.18/cm.sup.3 or more.

6. The infrared LED element according to claim 4, further comprising: a second electrode disposed on a surface of the support substrate, the surface being opposite to a surface on which the semiconductor laminate is disposed; and a reflection layer including a conductive material and disposed between the support substrate and the semiconductor laminate.

7. The infrared LED element according to claim 1, wherein the second semiconductor layer has band gap energy of 1.1 times or more band gap energy of the active layer.

8. The infrared LED element according to claim 1, wherein the uneven part formed on a surface of the third semiconductor layer has a surface roughness (Ra) of 0.25 to 1.00.

9. The infrared LED element according to claim 2, wherein the third semiconductor layer has a thickness of 1 m to 5 m.

10. The infrared LED element according to claim 2, further comprising a first electrode disposed in contact with a part of an upper surface of the third semiconductor layer, wherein the third semiconductor layer has a dopant concentration higher than a dopant concentration of the second semiconductor layer and is 510.sup.17/cm.sup.3 or more.

11. The infrared LED element according to claim 10, wherein the second semiconductor layer has a dopant concentration of 510.sup.17/cm.sup.3 or more, and the third semiconductor layer has a dopant concentration of 110.sup.18/cm.sup.3 or more.

12. The infrared LED element according to claim 10, further comprising: a second electrode disposed on a surface of the support substrate, the surface being opposite to a surface on which the semiconductor laminate is disposed; and a reflection layer including a conductive material and disposed between the support substrate and the semiconductor laminate.

13. The infrared LED element according to claim 2, wherein the second semiconductor layer has band gap energy of 1.1 times or more band gap energy of the active layer.

14. The infrared LED element according to claim 2, wherein the uneven part formed on a surface of the third semiconductor layer has a surface roughness (Ra) of 0.25 to 1.00.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0052] FIG. 1 is a correlation diagram regarding band gap energy of a semiconductor material;

[0053] FIG. 2 is a cross-sectional view schematically illustrating a structure of an infrared LED element according to a first embodiment;

[0054] FIG. 3A is a cross-sectional view for describing one step in a manufacturing method of the infrared LED element illustrated in FIG. 2;

[0055] FIG. 3B is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2;

[0056] FIG. 3C is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2;

[0057] FIG. 3D is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2;

[0058] FIG. 3E is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2;

[0059] FIG. 3F is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2;

[0060] FIG. 3G is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2;

[0061] FIG. 3H is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2;

[0062] FIG. 3I is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2;

[0063] FIG. 3J is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2;

[0064] FIG. 3K is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2; and

[0065] FIG. 3L is a cross-sectional view for describing one step in the manufacturing method of the infrared LED element illustrated in FIG. 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0066] Hereinafter, an infrared LED element according to the present invention will be described with reference to the drawings. Note that each of the following drawings concerning the infrared LED element is schematically illustrated, and the dimensional ratio and the number in the drawings do not necessarily coincide with the actual dimensional ratio and the actual number.

[0067] In the present specification, the expression a layer B is formed on an upper layer of a layer A is intended to include a case in which the layer B is formed on a surface of the layer A with a thin film interposed therebetween, as well as a case in which the layer B is formed directly on the surface of the layer A. Note that the thin film referred to herein may indicate a layer having a film thickness of 50 nm or less and preferably a layer having a film thickness of 10 nm or less.

[0068] FIG. 2 is a cross-sectional view schematically illustrating a structure of the infrared LED element according to the present embodiment. An infrared LED element 1 illustrated in FIG. 2 includes a semiconductor laminate 20 disposed on the upper layer (+Y side) of a support substrate 11. The infrared LED element 1 illustrated in FIG. 2 corresponds to a schematic cross-sectional view taken along the XY plane at a predetermined position. In the description given hereinafter, reference is made as appropriate to an XYZ coordinate system added to FIG. 2.

[0069] In the following description, positive and negative orientations distinguished from each other for directional expression will be described as a +X direction and a X direction by adding positive and negative signs. In addition, a direction expressed without distinction between positive and negative orientations will be described simply as the X direction. Namely, in the present specification, in a case where the direction is simply described as the X direction, both the +X direction and the X direction are included. The same applies to the Y direction and the Z direction.

[0070] In the infrared LED element 1, infrared light L is generated in the semiconductor laminate 20 (more specifically, in an active layer 25 described later). More specifically, as illustrated in FIG. 2, the infrared light L (L1, L2) is extracted in the +Y direction with respect to the active layer 25. The infrared light L has a peak wavelength of 1,000 nm to 2,000 nm.

[Element Structure]

[0071] Hereinafter, the structure of the infrared LED element 1 will be described in detail.

(Support Substrate 11)

[0072] The support substrate 11 includes, for example, a semiconductor such as silicon (Si) or germanium (Ge), or a metal material such as copper (Cu) or copper-tungsten (CuW). In a case where the support substrate 11 is constituted of a semiconductor, the support substrate may be doped with a dopant at high concentration so as to have electrical conductivity. As an example, the support substrate 11 is a Si substrate doped with boron (B) at a dopant concentration of 110.sup.19/cm.sup.3 or more and having a resistivity of 10 m.Math.cm or less. As the dopant, for example, phosphorus (P), arsenic (As), antimony (Sb), or the like can be used in addition to B. From the viewpoint of achieving both high heat dissipation and low manufacturing cost, the support substrate 11 is preferably an Si substrate.

[0073] The thickness (length in the Y direction) of the support substrate 11 is not particularly limited, but is, for example, 50 m to 500 m, and preferably 100 m to 300 m.

(Metal Bonding Layer 13)

[0074] The infrared LED element 1 includes a metal bonding layer 13 disposed on the upper layer of the support substrate 11. The metal bonding layer 13 includes a low-melting solder material such as gold (Au), gold-zinc (AuZn), gold-tin (AuSn), gold-indium (AuIn), AuCuSn, CuSn, palladium-tin (PdSn), or Sn. As will be described later with reference to FIG. 3G, the metal bonding layer 13 is used for bonding a growth substrate 3 on the upper surface of which the semiconductor laminate 20 is formed and the support substrate 11. The thickness of the metal bonding layer 13 is not particularly limited, but is, for example, 0.5 m to 5.0 m, and preferably 1.0 m to 3.0 m.

[0075] Note that barrier layers may be formed on the upper and lower layers of the metal bonding layer 13. The barrier layer is provided in some cases for the purpose of suppressing diffusion of a solder material constituting the metal bonding layer 13. The material is not limited as long as such a function is realized, but the barrier layer can be realized by, for example, a material containing titanium (Ti), platinum (Pt), tungsten (W), molybdenum (Mo), nickel (Ni), or the like. A more specific example is a Ti/Pt/Au laminate.

(Reflection Layer 15)

[0076] The infrared LED element 1 according to the present embodiment includes a reflection layer 15 disposed on the upper layer of the metal bonding layer 13.

[0077] The reflection layer 15 has a function of reflecting infrared light L2 traveling toward the support substrate 11 side (Y direction) among the infrared light L generated in the active layer 25 and guiding the infrared light L2 in the +Y direction. The reflection layer 15 includes a conductive material and a material exhibiting high reflectance to the infrared light L. The reflectance of the reflection layer 15 with respect to the infrared light L is 50% or more, preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

[0078] In a case where the peak wavelength of the infrared light L is 1,000 nm to 2,000 nm, silver (Ag), an Ag alloy, Au, Al, Cu, or the like can be used as the material of the reflection layer 15. This material can be appropriately selected according to the wavelength of the infrared light L.

[0079] The thickness of the reflection layer 15 is not particularly limited, but is, for example, 0.1 m to 2.0 m inclusive, and preferably 0.3 m to 1.0 m inclusive.

[0080] Note that, in a case where the barrier layer as described above is formed between the reflection layer 15 and the metal bonding layer 13, a decrease in reflectance of the reflection layer 15 due to diffusion of the material constituting the metal bonding layer 13 toward the reflection layer 15 can be suppressed.

[0081] From the viewpoint of improving the light extraction efficiency, it is preferable that the infrared LED element 1 includes the reflection layer 15 as illustrated in FIG. 2, but in the present invention, whether or not the infrared LED element 1 includes the reflection layer 15 is optional.

[0082] Furthermore, although not illustrated, from the viewpoint of improving the light extraction efficiency, the infrared LED element 1 preferably includes an antireflection film that covers the upper surface, the side surface, or both of the upper and side surfaces of the semiconductor laminate 20. However, whether or not the infrared LED element 1 includes the antireflection film is optional. Note that, for example, using silicon dioxide (SiO.sub.2), silicon nitride (SiN), or the like as a material, the film thickness of the antireflection film is appropriately determined so as to have an optical film thickness such that the reflectance decreases from the refractive index and the emission wavelength, and the antireflection film is formed on the upper surface, the side surface, or both of the upper and side surfaces of the semiconductor laminate 20 by a plasma chemical vapor deposition (CVD) method.

(Insulating Layer 17)

[0083] The infrared LED element 1 illustrated in FIG. 2 includes an insulating layer 17 disposed on the upper layer of the reflection layer 15. The insulating layer 17 includes a material that exhibits electrical insulation and has high transparency to the infrared light L. Transmittance of the insulating layer 17 to the infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

[0084] In a case where the peak wavelength of the infrared light L is 1,000 nm to 2,000 nm, SiO.sub.2, SiN, aluminum oxide (Al.sub.2O.sub.3), zirconia oxide (ZrO), hydrofluoroolefin (HfO), magnesium oxide (MgO), or the like can be used as the material of the insulating layer 17. This material can be appropriately selected according to the wavelength of light generated in the active layer 25.

(Semiconductor Laminate 20)

[0085] The infrared LED element 1 illustrated in FIG. 2 includes a semiconductor laminate 20 disposed on the upper layer of the insulating layer 17. The semiconductor laminate 20 is a laminate of a plurality of semiconductor layers, and includes, for example, a first contact layer 21, a first cladding layer 23, an active layer 25, and a second cladding layer 27. Each of the semiconductor layers (21,23,25, and 27) constituting the semiconductor laminate 20 includes a material that can be epitaxially grown while being lattice-matched with the growth substrate 3 to be described later.

[0086] The entire thickness of the semiconductor laminate 20 is 30 m (30,000 nm) or less, and preferably 5 m to 20 m.

<<First Contact Layer 21 and First Cladding Layer 23>>

[0087] In the present embodiment, the first contact layer 21 includes, for example, p-type GaInAsP. The thickness of the first contact layer 21 is not limited, and is, for example, 10 nm to 1,000 nm, and preferably 50 nm to 500 nm. Further, the concentration of a p-type dopant in the first contact layer 21 is preferably 510.sup.17/cm.sup.3 to 310.sup.19/cm.sup.3, more preferably 110.sup.18/cm.sup.3 to 210.sup.19/cm.sup.3.

[0088] In the present embodiment, the first cladding layer 23 is disposed on the upper layer of the first contact layer 21 and includes p-type InP. The thickness of the first cladding layer 23 is not limited, but is, for example, 1,000 nm to 10,000 nm, and preferably 2,000 nm to 5,000 nm. The concentration of a p-type dopant in the first cladding layer 23, at a position apart from the active layer 25, preferably ranges from 110.sup.17/cm.sup.3 to 310.sup.18/cm.sup.3 inclusive, and more preferably ranges from 510.sup.17/cm.sup.3 to 310.sup.18/cm.sup.3 inclusive.

[0089] As the p-type dopant contained in the first contact layer 21 and the first cladding layer 23, a material such as Zn, Mg, or beryllium (Be), preferably Zn or Mg, and particularly preferably Zn can be used. In the present embodiment, the first contact layer 21 and the first cladding layer 23 correspond to a first semiconductor layer.

<<Active Layer 25>>

[0090] In the present embodiment, the active layer 25 is a semiconductor layer formed on the upper layer of the first cladding layer 23. A material of the active layer 25 is appropriately selected from material that can generate light of a target wavelength and can be epitaxially grown while being lattice-matched with the growth substrate 3 as described later with reference to FIG. 3B and the like.

[0091] In manufacturing the infrared LED element 1 that emits the infrared light L having a peak wavelength of 1,000 nm to 2,000 nm, the active layer 25 may have a single-layer structure including GaInAsP, AlGaInAs, or InGaAs, or may have a multiple quantum well (MQW) structure that includes a well layer including GaInAsP, AlGaInAs, or InGaAs and a barrier layer including GaInAsP, AlGaInAs, InGaAs, or InP that is greater in band gap energy than the well layer.

[0092] In a case where the active layer 25 has the single-layer structure, the active layer 25 has a film thickness of 50 nm to 2,000 nm, and preferably 100 nm to 300 nm. Furthermore, in a case of the MQW structure, the active layer 25 is formed by laminating the well layer and the barrier layer, each having a film thickness of 5 nm to 20 nm, in a range of 2 cycles to 50 cycles.

[0093] The active layer 25 may be doped with an n-type or p-type dopant or may be undoped. In a case where the active layer 25 is doped with the n-type dopant, the dopant may be, for example, Si.

<<Second Cladding Layer 27>>

[0094] In the present embodiment, the second cladding layer 27 is disposed on the upper layer of the active layer 25 and is constituted of n-type InP. The second cladding layer 27 needs to have a certain film thickness and impurity concentration for the purpose of current dispersion. The thickness of the second cladding layer 27 is not limited, and is, for example, 2,000 nm to 15,000 nm, and preferably 5,000 nm to 10,000 nm. The concentration of the n-type dopant in the second cladding layer 27 is preferably 510.sup.17/cm.sup.3 or more, more preferably 110.sup.18/cm.sup.3. Note that, in a case where the current dispersion and the like is also taken into consideration, a range of the concentration of the n-type dopant in the second cladding layer 27 is preferably 510.sup.17/cm.sup.3 to 110.sup.19/cm.sup.3, more preferably 110.sup.18/cm.sup.3 to 510.sup.18/cm.sup.3.

[0095] Materials for the first and the second cladding layers 23 and 27 are selected appropriately from ones that do not absorb the infrared light L generated in the active layer 25 and that can be epitaxially grown by being lattice-matched to the growth substrate 3 (see FIG. 3B). In a case where an InP substrate is adopted as the growth substrate 3, InP, GaInAsP, AlGaInAs, or the like can be used as a material of the first cladding layer 23 and the second cladding layer 27, but InP is preferable.

[0096] In addition, although optional, from the viewpoint of suppressing a decrease in efficiency, the band gap energy of the second cladding layer 27 is preferably 1.1 times or more the band gap energy of the active layer 25.

<<Second Contact Layer 28>>

[0097] In the present embodiment, the material of the second contact layer 28 is disposed on the upper layer of the second cladding layer 27 and is appropriately selected from materials satisfying Al.sub.aGa.sub.bIn.sub.cAs (0a<1, 0<b<1, 0<c<1, a+b+c=1). More specifically, for example, AlGaInAs, InGaAs, or the like can be used.

[0098] For the second contact layer 28, a material having band gap energy lower than that of the second cladding layer 27 and higher than that of the active layer 25 is selected.

[0099] In the present embodiment, the second contact layer 28 includes, for example, n-type AlGaInAs. The thickness of the second contact layer 28 is not limited, but is preferably 1 m to 5 m, and more preferably 2 m to 4 m. The concentration of the n-type dopant in the second contact layer 28 is preferably 510.sup.17/cm.sup.3 or more, and more preferably 110.sup.18/cm.sup.3 or more.

[0100] Note that, in a case where the current dispersion and the like is also taken into consideration, a range of the concentration of the n-type dopant in the second contact layer 28 is preferably 510.sup.17/cm.sup.3 to 310.sup.19/cm.sup.3, and more preferably 110.sup.18/cm.sup.3 to 210.sup.19/cm.sup.3. In addition, although optional, from the viewpoint of relatively reducing the electric resistance value, the dopant concentration of the second contact layer 28 is preferably configured to be higher than the dopant concentration of the second cladding layer.

[0101] As the n-type impurity material doped in the second cladding layer 27 and the second contact layer 28, Sn, Si, sulfur(S), Ge, selenium (Se), or the like can be used, and Si is particularly preferable. The second cladding layer 27 corresponds to a second semiconductor layer, and the second contact layer 28 corresponds to a third semiconductor layer.

[0102] As illustrated in FIG. 2, in the infrared LED element 1 according to the present embodiment, an uneven part 40 is formed on the +Y side surface (hereinafter, referred to as a first surface 28a) of the second contact layer 28. The uneven part 40 is schematically illustrated in a periodic shape in FIG. 2, but actually has a random uneven shape formed by dip treatment using an etching solution. Here, although optional, from the viewpoint of enhancing the light extraction efficiency, the viewpoint of ease of formation, and the like, a surface roughness (Ra) of the uneven part 40 is preferably 0.25 to 1.00.

(Internal Electrode 31)

[0103] The infrared LED element 1 illustrated in FIG. 2 has an internal electrode 31 formed penetrating in the Y direction at a plurality of locations in the insulating layer 17. The internal electrode 31 electrically connects the first semiconductor layer (21, 23) and the support substrate 11. The internal electrodes 31 are preferably provided at a plurality of positions dispersed in a direction parallel to the XZ plane (that is, a direction parallel to the main surface of the support substrate 11).

[0104] The internal electrode 31 includes a material that can form an ohmic connection with the first contact layer 21. As an example, the internal electrode 31 includes AuZn, AuBe, or a laminated structure (for example, Au/Zn/Au or the like) containing at least Au and Zn. Note that these materials have lower reflectance for the infrared light L than the materials constituting the reflection layer 15.

[0105] A shape of the pattern of the internal electrodes 31 when viewed in the Y direction is optional. However, from the viewpoint of allowing a flow of the electric current across a wide range in the active layer 25 in a direction parallel to the main surface (XZ plane) of the support substrate 11 (hereinafter, referred to as a plane direction), the internal electrodes 31 are preferably disposed at a plurality of places that are dispersed in the plane direction.

[0106] The total area of all the internal electrodes 31 when viewed in the Y direction is preferably 30% or less, more preferably 20% or less, and particularly preferably 15% or less with respect to the area in the plane direction of the semiconductor laminate 20 (for example, the active layer 25). If the total area of the internal electrodes 31 becomes relatively large, the amount of infrared light L2 traveling from the active layer 25 to the support substrate 11 side (Y direction) and absorbed by the internal electrodes 31 increases, leading to deterioration of the light extraction efficiency. On the other hand, if the total area of the internal electrodes 31 becomes too small, the resistance value increases, leading to an increase in the forward voltage.

(Upper-Surface Electrode 32)

[0107] The infrared LED element 1 illustrated in FIG. 2 includes an upper-surface electrode 32 disposed on the upper surface of the semiconductor laminate 20. Typically, the plural pieces of the upper-surface electrodes 32 are formed to extend in a predetermined direction. As an example, the plurality of upper-surface electrodes 32 extends in the X direction and the Z direction along the side of the semiconductor laminate 20 and has a comb shape. However, the shape of the arrangement pattern of the upper-surface electrode 32 is optional, and may be, for example, a lattice shape or a spiral shape.

[0108] The upper-surface electrodes 32 are formed over a wide range on the XZ plane while exposing the surface of the second contact layer 28 located in the lower layer (Y side) (directly or except for a part of the dielectric layer formed on the same surface). This enables the electric current flowing in the active layer 25 to expand in a direction parallel to the XZ plane direction and thus enables light emission in a wide range in the active layer 25.

[0109] The upper-surface electrode 32 includes, for example, a material such as AuGe/Ni/Au or AuGe, and may include a plurality of these materials. Note that the upper-surface electrode 32 corresponds to a first electrode.

(Pad Electrode 34)

[0110] As illustrated in FIG. 2, the infrared LED element 1 includes a pad electrode 34 disposed on the upper surface of a part of the upper-surface electrode 32. Note that, in FIG. 2, the pad electrode 34 is illustrated as being formed on the entire surface of the upper-surface electrode 32, but this is for convenience of illustration. In practice, the pad electrode 34 may be formed on a part of the surface of the upper-surface electrode 32 extending in the plane direction.

[0111] The pad electrode 34 includes, for example, Ti/Au, Ti/Pt/Au, or the like. This pad electrode 34 is provided for the purpose of securing a region to be brought into contact with a bonding wire for power supply, but it is optional whether or not the pad electrode 34 is provided in the present invention.

(Back-Surface Electrode 33)

[0112] The infrared LED element 1 illustrated in FIG. 2 includes a back-surface electrode 33 formed on a surface (the Y side) of the support substrate 11 opposite the semiconductor laminate 20. The back-surface electrode 33 is brought into ohmic contact with the support substrate 11. The back-surface electrode 33 includes, for example, a material such as Ti/Au or Ti/Pt/Au, and may contain two or more of these materials. Note that the back-surface electrode 33 corresponds to a second electrode.

[Manufacturing Method]

[0113] An example of a manufacturing method of the above-described infrared LED element 1 will be described with reference to each of FIGS. 3A to 3L. FIGS. 3A to 3L are each a cross-sectional view illustrating a step in a manufacturing process. Note that the order of the following procedures may be appropriately changed as long as the procedures do not affect the manufacture of the infrared LED element 1.

(Step S1)

[0114] As illustrated in FIG. 3A, the growth substrate 3 is prepared. In the present embodiment, an InP substrate having a (001) plane as one main surface is suitably used as the growth substrate 3. An example of the thickness of the substrate is 370 m, and the diameter of the main surface thereof is 2 inches. However, the thickness and size of the growth substrate 3 are appropriately set.

(Step S2)

[0115] The growth substrate 3 is conveyed into, for example, a metal organic chemical vapor deposition (MOCVD) apparatus, and a buffer layer 22, an etching stop layer (ES layer) 24, the second contact layer 28, the second cladding layer 27, the active layer 25, the first cladding layer 23, and the first contact layer 21 are sequentially epitaxially grown on the growth substrate 3 to form the semiconductor laminate 20 (see FIG. 3B). In this step S2, the type and the flow rate of the raw material gas, the treatment time, the environmental temperature, and the like are appropriately adjusted according to the material of the layer to be grown or the film thickness.

[0116] A formation example of the semiconductor laminate 20 is as follows. First, n-type InP doped with Si is laminated on the growth substrate 3 with a predetermined film thickness (for example, about 500 nm) to obtain the buffer layer 22. Next, a layer (here, an InGaAs layer) of a material different from that of the buffer layer 22 is laminated with a predetermined film thickness (for example, about 200 nm) to obtain an ES layer 24a. Next, a layer (here, an InP layer) of a material different from that of the ES layer 24a is laminated with a predetermined film thickness (for example, about 300 nm) to obtain an ES layer 24b. Thereafter, the second contact layer 28, the second cladding layer 27, the active layer 25, the first cladding layer 23, and the first contact layer 21 are sequentially formed in a state where growth conditions are set so as to have the film thickness and the composition described above. Note that, in a case where the second semiconductor layer has a function of the ES layer, the ES layer 24 may not be formed.

[0117] As a detailed example, AlGaInAs is laminated with a film thickness of 5,000 nm to obtain the second contact layer 28. Next, n-type InP using Si as a dopant is laminated with a film thickness of 3,000 nm to obtain the second cladding layer 27. Next, InGaAsP is laminated with a film thickness of 900 nm to obtain the active layer 25. Here, the condition is such that the peak wavelength of the infrared light L emitted from the infrared LED element 1 is 1,300 nm. However, as described above, the peak wavelength of the infrared light L can be adjusted within a range of 1,000 nm to 2,000 nm by adjusting the composition ratio of the materials constituting the active layer 25 or adopting the MQW structure.

[0118] Thereafter, p-type InP using Zn as a dopant is laminated with a film thickness of 3,000 nm to form the first cladding layer 23, and successively, p-type InGaAsP using Zn as a dopant is laminated with a film thickness of 200 nm to form the first contact layer 21.

(Step S3)

[0119] After a wafer on which the semiconductor laminate 20 is formed on the growth substrate 3 is taken out from the MOCVD apparatus, the insulating layer 17 including, for example, SiO2 is formed by the plasma CVD method (see FIG. 3C). An example of the film thickness of the insulating layer is 200 nm. Next, a resist mask patterned by a photolithography method is formed on the surface of the insulating layer 17. After the insulating layer 17 formed in the resist opening is removed by an etching method using a predetermined chemical such as buffered hydrofluoric acid, a material film of the internal electrode 31 including, for example, Au/Zn/Au is formed by using an electron beam (EB) vapor deposition apparatus. An example of the film thickness of the material film of the internal electrode 31 is Au/Zn/Au=25 nm/25 nm/150 nm.

[0120] Next, after the resist mask is removed, the material film formed in the unnecessary region is lifted off to form the internal electrode 31 (see FIG. 3C). Thereafter, an annealing treatment is performed through heat treatment, for example, at 450 C. for 10 minutes to form an ohmic contact between the first contact layer 21 and the internal electrode 31.

(Step S4)

[0121] As shown in FIG. 3D, the reflection layer 15 and a metal bonding layer 13a are sequentially formed on the upper surface of the insulating layer 17. For example, Al/Au is deposited with a predetermined film thickness by the EB vapor deposition apparatus to form the reflection layer 15, and successively, Ti/Au is deposited with a predetermined film thickness to form the metal bonding layer 13a. The metal bonding layer 13a may be the same material as the metal bonding layer 13 described above.

[0122] An example of the film thickness of the reflection layer 15 is Al/Au=5 nm/200 nm. An example of the film thickness of the metal bonding layer 13a is Ti/Au=150 nm/1,500 nm. Note that, as described above, a barrier layer may be formed between the reflection layer 15 and the metal bonding layer 13a. An example of the film thickness of the barrier layer is Ti/Pt/Au=150 nm/300 nm/200 nm.

(Step S5)

[0123] As illustrated in FIG. 3E, the support substrate 11 different from the growth substrate 3 is prepared. In the present embodiment, a conductive Si substrate having a (001) plane as one main surface and highly doped with B is used. The electric resistivity of the support substrate 11 is preferably less than 10 m.Math.cm (=0.1 m.Math.m). Note that, as described above, a barrier layer may be formed between the support substrate 11 and a metal bonding layer 13b.

(Step S6)

[0124] As illustrated in FIG. 3F, the metal bonding layer 13b is formed on the main surface of the support substrate 11. The metal bonding layer 13b can be formed by the same method as the metal bonding layer 13a described above in step S4.

(Step S7)

[0125] As illustrated in FIG. 3G, the growth substrate 3 and the support substrate 11 are bonded to each other with the metal bonding layer 13 (13a, 13b) interposed therebetween while being pressurized by using, for example, a wafer bonding device. Preferably, the surfaces of the respective metal bonding layers 13 (13a, 13b) are stacked together in a cleaned state. This bonding treatment is performed, for example, at 300 C. and 1 MPa. By this treatment, the metal bonding layer 13a on the growth substrate 3 and the metal bonding layer 13b on the support substrate 11 are melted and integrated (metal bonding layer 13).

(Step S8)

[0126] As illustrated in FIG. 3H, the growth substrate 3 is removed. As an example, the growth substrate 3 is removed by immersing the bonded wafer in a hydrochloric acid-based etchant. At this time, because the ES layer 24 formed of a material different from the growth substrate 3 and the buffer layer 22 is insoluble in a hydrochloric acid-based etchant, the etching treatment is stopped when the ES layer 24a is exposed.

(Step S9)

[0127] As illustrated in FIG. 3I, the ES layer 24a and the ES layer 24b are removed to expose the second contact layer 28. For example, after cleaning with pure water as necessary, the ES layer 24a is removed by being immersed in a predetermined chemical solution that melts the ES layer 24a but does not melt the ES layer 24b. As a chemical solution for removing the ES layer 24a, for example, a mixed solution of sulfuric acid and hydrogen peroxide water (SPM) can be used. Thereafter, the ES layer 24b is removed by being immersed in a predetermined chemical solution that melts in the ES layer 24b but does not melt the second contact layer 28. As a chemical solution for removing the ES layer 24b, for example, a hydrochloric acid-based etchant can be used.

(Step S10)

[0128] As shown in FIG. 3J, the upper-surface electrode 32 is formed on the exposed surface of the second contact layer 28. Specifically, the following procedure is performed.

[0129] A resist mask patterned by the photolithography method is formed on the surface of the second contact layer 28. Next, after a material for forming the upper-surface electrode 32 (for example, Au/Ge/Au) is deposited by the EB vapor deposition apparatus, the lift-off is performed to form the upper-surface electrode 32. An example of the film thickness of the upper-surface electrode 32 is Au/Ge/Au=10 nm/30 nm/150 nm.

[0130] Thereafter, in order to realize the ohmic properties of the upper-surface electrode 32, annealing treatment is performed by heat treatment at, for example, 450 C. for 10 minutes.

[0131] Next, the pad electrode 34 is formed on the upper surface of the upper-surface electrode 32 at a predetermined position. Similarly to the case of the upper-surface electrode 32, the formation in this case can also be realized by the film forming step and the lift-off step by the EB vapor deposition apparatus. As the pad electrode 34, for example, Ti/Pt/Au is deposited, and an example of the thickness thereof is Ti/Pt/Au=150 nm/300 nm/1,500 nm.

(Step S11)

[0132] As shown in FIG. 3K, the uneven part 40 is formed on the first surface 28a of the second contact layer 28.

[0133] As an example of a specific method, first, a resist patterned on the first surface 28a of the second contact layer 28 on the basis of the photolithography method is formed. This resist is formed so as to cover the upper portion of the region where the upper-surface electrode 32 is formed.

[0134] Through this patterned resist, etching is performed on the first surface 28a of the second contact layer 28 by using an etchant such as a sulfuric acid-nitric acid mixed solution. In this manner, the uneven part 40 having a random uneven shape is formed on the first surface 28a of the second contact layer 28. As the etchant, for example, a nitric acid-water mixed solution is used.

[0135] Thereafter, the resist is removed with a cleaning liquid such as acetone. As an example of the etchant, for example, resist stripping solutions sold by various resist manufacturers are used.

(Step S12)

[0136] As illustrated in FIG. 3L, mesa etching for separating into each element is performed. Specifically, wet etching is performed by using a predetermined etchant while a non-etched region of the surface of the second contact layer 28 is masked by a resist patterned by the photolithography method. As a result, a part of the semiconductor laminate 20 located in the unmasked region is removed.

[0137] As an example of a specific method, first, the second contact layer 28 and the second cladding layer 27 are removed by etching using a hydrochloric acid-phosphoric acid mixed solution. This reaction is stopped when the active layer 25 is exposed. Next, the active layer 25 is removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide water (SPM). This reaction is stopped in the first cladding layer 23. Next, the first cladding layer 23 is partially removed by etching using the hydrochloric acid-phosphoric acid mixed solution. Thereafter, the resist is removed by a cleaning liquid such as acetone. The first cladding layer 23 and the first contact layer 21 may be removed to expose the insulating layer 17.

(Step S13)

[0138] After the thickness on the back surface side of the support substrate 11 is adjusted, the back-surface electrode 33 is formed on the back surface side of the support substrate 11 (see FIG. 2). As a specific method of forming the back-surface electrode 33, similarly to the upper-surface electrode 32, the back-surface electrode 33 can be formed by depositing a material for forming (for example, Ti/Pt/Au) the back-surface electrode 33 by a vacuum vapor deposition apparatus. An example of the film thickness of the back-surface electrode 33 is Ti/Pt/Au=150 nm/300 nm/1,500 nm.

[0139] A method of adjusting the thickness of the support substrate 11 is optional, but as an example, a method of grinding with a back grinder in a state where the semiconductor laminate 20 side is attached to a back grind tape can be adopted. The thickness after the grinding is adjusted, for example, within a range within 50 m to 250 m, and is appropriately selected according to the application of the infrared LED element 1 and the subsequent process. As a specific example, the thickness of the support substrate 11 after the grinding is 150 m. After the grinding processing is completed, the tape is peeled off and the substrate is cleaned.

[0140] Note that the adjustment of the thickness on the back surface side of the support substrate 11 may be performed as necessary, and is not necessarily an essential step.

(Step S14)

[0141] Next, the support substrate 11 is diced together to form chips. For example, in a state where the back-surface electrode 33 side is attached with a dicing tape, dicing is performed together with the support substrate 11 from the upper-surface electrode 32 side along a dicing line formed by the mesa etching in step S13, by using a diamond blade or the like.

[0142] Thereafter, the chipped infrared LED element 1 is mounted on a stem or the like by using a conductive adhesive such as an Ag paste. The pad electrode 34 is connected to a post portion of the stem by wire bonding.

[0143] In the infrared LED element 1 having the above configuration, similarly to the conventional configuration, because the second cladding layer 27 corresponding to the second semiconductor layer is formed on the upper layer of the active layer 25, the bandgap energy difference between the active layer and the second semiconductor layer is maintained to the same extent as in the conventional configuration. Furthermore, in the second contact layer 28 constituting the light exit surface (first surface 28a), the uneven part 40 for improving the light extraction efficiency is easily formed as compared with InP. Therefore, in the infrared LED element 1, an uneven shape can be efficiently formed on the light exit surface (first surface 28a) and the luminous efficiency does not easily decrease even in a case of being driven with a large current.

[0144] In the above embodiment, the first semiconductor layer (first contact layer 21 and first cladding layer 23) is a p-type semiconductor, and the second semiconductor layer (second contact layer 28 and second cladding layer 27) is an n-type semiconductor. However, the conductivity types of the first semiconductor layer and the second semiconductor layer may be reversed.