Planar SiC MOSFET with retrograde implanted channel

Abstract

A silicon carbide (SiC) planar transistor device includes a SiC semiconductor substrate of a first charge type, a SiC epitaxial layer of the first charge type formed at a top surface of the SiC semiconductor substrate, a source structure of the first charge type formed at a top surface of the SiC epitaxial layer, a drain structure of the first charge type formed at a bottom surface of the SiC semiconductor substrate, a gate structure comprising a gate runner and a gate dielectric that covers at least part of the source structure and the gate runner, and a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure. The channel can be formed by performing a plurality of implantation steps so that the channel region comprises a first region and a second region.

Claims

1. A silicon carbide (SiC) planar transistor device comprising: a SiC semiconductor substrate of a first charge type having a top surface and a bottom surface; a SiC epitaxial layer of the first charge type formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface; a source structure of the first charge type formed in the top surface of the SiC epitaxial layer, the source structure having a top surface; a drain structure of the first charge type formed on the bottom surface of the SiC semiconductor substrate; a gate structure comprising a gate dielectric and a gate runner, wherein the gate dielectric covers at least part of the source structure and the gate runner; a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure, wherein a doping profile of the second charge type of the channel region comprises a first region and a second region; wherein the first region has a constant doping concentration in a range of 210.sup.17 cm-3 to 310.sup.18 cm.sup.3 and is located in a vertical direction below to the gate dielectric with a depth between 50 nm to 250 nm from the top surface of the SiC epitaxial layer; wherein the second region has a Pearson-Type-IV-like distributed doping concentration with a peak doping concentration in a range of 1.510.sup.8 cm.sup.3 to 810.sup.18 cm.sup.3 and is located in a vertical direction below and adjacent to the first region with the peak position of the Pearson-Type-IV-like distribution in a range of 300 nm to 500 nm from the top surface of the SiC epitaxial layer; and wherein the channel has a length in a range of 50 nm to 250 nm.

2. The silicon carbide planar transistor device according to claim 1, wherein the planar transistor is a metal-oxide-semiconductor field-effect transistor.

3. The silicon carbide planar transistor device according to claim 2, wherein the transistor device has threshold voltage in a range of 2V to 3.5V.

4. The silicon carbide planar transistor device according to claim 1, wherein the planar transistor is an insulated-gate bipolar transistor.

5. The silicon carbide planar transistor device according to claim 4, wherein the transistor device has threshold voltage in a range of 2V to 3.5V.

6. The silicon carbide planar transistor device according to claim 1, wherein the transistor device has threshold voltage in a range of 2V to 3.5V.

7. The silicon carbide planar transistor device according to claim 1, wherein the gate dielectric comprises a gate oxide.

8. The silicon carbide planar transistor device according to claim 1, wherein an oxide capacitance and interface trap concentration allow for a maximum variation of 2%-5% from a constant value.

9. The silicon carbide planar transistor device according to claim 1, wherein the first region is doped with Al, N, B or P.

10. A silicon carbide (SiC) planar transistor device comprising: a SiC semiconductor substrate of a first charge type having a top surface and a bottom surface; a SiC epitaxial layer of the first charge type formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface; a source structure of the first charge type formed in the top surface of the SiC epitaxial layer, the source structure having a top surface; a drain structure of the first charge type formed on the bottom surface of the SiC semiconductor substrate; a gate structure comprising a gate dielectric and a gate runner, wherein the gate dielectric covers at least part of the source structure and the gate runner; a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure, wherein a doping profile of the second charge type of the channel region comprises a first region and a second region; wherein the first region has a constant concentration of dopants in a range of 210.sup.17 cm.sup.3 to 310.sup.18 cm.sup.3 and is located in a vertical direction below to the gate dielectric with a depth between 50 nm to 250 nm from the top surface of the SiC epitaxial layer, the dopants comprising Al, N, B or P; wherein the second region has a Pearson-Type-IV-like distributed doping concentration with a peak doping concentration in a range of 1.510.sup.18 cm.sup.3 to 810.sup.18 cm.sup.3 and is located in a vertical direction below and adjacent to the first region with the peak position of the Pearson-Type-IV-like distribution in a range of 300 nm to 500 nm from the top surface of the SiC epitaxial layer; wherein the channel has a length in a range of 50 nm to 250 nm; and wherein the transistor device has threshold voltage in a range of 2V to 3.5V.

11. The silicon carbide planar transistor device according to claim 10, wherein the planar transistor is a metal-oxide-semiconductor field-effect transistor.

12. The silicon carbide planar transistor device according to claim 10, wherein the planar transistor is an insulated-gate bipolar transistor.

13. The silicon carbide planar transistor device according to claim 1, wherein the gate dielectric comprises a gate oxide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

(2) FIG. 1 shows an example of a cross-section of a planar MOSFET structure.

(3) FIG. 2 shows a channel doping profile of a MOSFET structure.

(4) FIG. 3 shows a channel doping profile according to an embodiment of the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(5) Examples of embodiments will now be described more fully with reference to the accompanying drawings.

(6) Example embodiments are provided so that this disclosure will be thorough, and willfully convey the scope to those who are skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods, to provide a thorough under-standing of embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In some example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.

(7) The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms a, an, and the may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms comprises, comprising, including, and having, are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance.

(8) It is also to be understood that additional or alternative steps may be employed.

(9) When an element or layer is referred to as being on, engaged to, connected to, or coupled to another element or layer, it may be directly on, engaged, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being directly on, directly engaged to, directly connected to, or directly coupled to another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., between versus directly between, adjacent versus directly adjacent, etc.). As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

(10) Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as first, second, and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

(11) Spatially relative terms, such as inner, outer, beneath, below, lower, above, upper, and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as below or beneath other elements or features would then be oriented above the other elements or features. Thus, the example term below may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

(12) The embodiments refer to MOS-based SiC planar devices such as, e.g., metal-oxide-semiconductor field-effect transistors (MOSFET) or an insulated-gate bipolar transistors (IGBT) as shown in FIG. 1, for example.

(13) In FIG. 1. An example of a cross-section of a typical planar SiC MOSFET structure is shown. The silicon carbide (SiC) planar transistor device in FIG. 1 comprises a SiC semiconductor substrate 1 of a first charge type, e.g., p-type, having a top surface and a bottom surface. A SiC epitaxial layer 2 of the first charge type is formed on the top surface of the SiC semiconductor substrate 1, the SiC epitaxial layer 2 having a top surface. A source structure 3 of the first charge type is formed in the top surface of the SiC epitaxial layer 2, the source structure 3 having a top surface. A drain structure 4 of the first charge type is formed on the bottom surface of the SiC semiconductor substrate 1 and a gate structure 6, 7 comprising a gate oxide 7 and a gate runner 6, wherein the gate oxide 7 covers at least part of the source structure 3 and the gate runner 6. A channel region 5 of a second charge type, e.g., n-type is located in vertical direction below the gate structure 6, 7 and adjacent to the source structure 3.

(14) An example of a channel profile used in planar MOSFET devices is shown FIG. 2.

(15) Despite from the fact that the devices with a channel profile shown in FIG. 2 are working, the following deficiencies may arise:

(16) Even when implanted through the nominal oxide thickness, a variation of the doping concentration in the first 200 nm is quite high. V.sub.TH may shift significantly depending on how much SiC is removed by the oxidation process. For example, removing 10 nm of SiC causes a reduction of 13% in the surface channel concentration.

(17) The thickness of the screening oxide significantly affects the surface channel concentration and therefore V.sub.TH. The channel profiles are quite similar if 20 nm of SiC are removed by the growth of a thermal oxide. But in case of a deposited gate oxide, the surface concentration drops significantly and therefore V.sub.TH decreases. This could be compensating adjusting the dose in the case of deposited oxides, but then any very small variation in the consumed SiC leads to a great change in surface concentration.

(18) The channel length L.sub.CH in planar devices is in theory determined by gate spacers but due to the scattering during implantation, different channel profiles result in different lateral shapes which also may affect the constancy of L.sub.CH. For example, the channel length of a planar MOSFET device with channel doping increases as more SiC thickness is consumed during gate oxidation.

(19) To overcome the above mentioned deficiencies and to provide an improved planar SiC device, a tailored doping profile for the channel region of the planar SiC device in the vertical and horizontal direction has been designed by mathematical optimization. FIG. 3 shows the combination of several implantations (in dashed lines) with doses chosen through a mathematical optimization procedure yielding in the new designed profile (in continuous line). The proposed profile is not only flat in the vertical direction but also in the lateral direction, ensuring that L.sub.CH is stable with respect to process variation. It is evident from FIG. 3 that this new designed profile has negligible variation of the dopant concentration in the first 200 nm.

(20) The profile consists in a first flat region (I) of a depth between 50 nm and 250 nm of constant doping between 2e.sup.17 and 3e.sup.18 cm.sup.3, depending on the choice of the threshold V.sub.TH, the oxide capacitance and the interface trap concentration allowing for a maximum variation of 8-10% from the constant value. Examples of dopants are Al, N, B, P.

(21) The peak part of the profile may be obtained with one of more implantations, reaching a peak position in section II in FIG. 3 between 300 nm and 500 nm and a peak concentration between 1.5e.sup.18 cm.sup.3 and 8e.sup.18 cm.sup.3.

(22) The Silicon carbide (SiC) planar transistor device improved by the above mentioned tailored channel profile, therefore comprises a SiC semiconductor substrate of a first charge type having a top surface and a bottom surface, a SiC epitaxial layer of a first charge type formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface, a source structure of a first charge type formed in the top surface of the SiC epitaxial layer, the source structure having a top surface, a drain structure of a first charge type formed on the bottom surface of the SiC semiconductor substrate, a gate structure comprising a gate oxide and a gate runner, wherein the gate oxide covers at least part of the source structure and the gate runner, a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure, wherein a doping profile of the second charge type of the channel region comprises a first region and a second region, wherein the first region has a constant doping concentration in a range of 2*e.sup.17 cm.sup.3 to 3*e.sup.18 cm.sup.3 and is located in a vertical direction below to the gate oxide with a depth between 50 nm to 250 nm from the top surface of the SiC epitaxial layer and the second region has a Pearson-Type-IV-like distributed doping concentration with a peak doping concentration in a range of 1.5*e.sup.18 cm.sup.3 to 8*e.sup.18 cm.sup.3 and is located in a vertical direction below and adjacent to the first region with the peak position of the Pearson-Type-IV-like distribution in a range of 300 nm to 500 nm from the top surface of the SiC epitaxial layer. In one embodiment, the flat first region is located in a vertical direction below to the gate oxide with a depth between 75 nm to 150 nm. In another embodiment, the oxide capacitance and the interface trap concentration allowing for a maximum variation of 2%-5% from the constant value.

(23) The improved channel profile insures that a constant L.sub.CH is maintained irrespective of process variations. Furthermore the optimized channel profile for a planar SiC device enables an accurate and robust control of threshold voltage V.sub.TH and channel length L.sub.CH with respect to process variation (i.e., variation and non-uniformity of thickness of the implantation screening oxide or variation in the consumed SiC thickness during gate formation depending on, e.g., the oxidation conditions etc.) and pinning of the peak electric field away from the gate oxide/SiC interface to increase the reliability of the device.

(24) Moreover, the improved channel profile ensures that these values of V.sub.TH and L.sub.CH are maintained irrespective of the variability of processing (screening oxide thickness and consumed SiC thickness are not uniform over the wafer surface). In this respect, constant values of V.sub.TH and L.sub.CH achieve a smaller variation in the device characteristics and a better yield.

(25) The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and may be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.