RECEIVER

Abstract

A differential transceiver circuit coupled to a single antenna interface, the transceiver circuit comprising: a differential pair of signal paths, comprising a first signal path and a second signal path; differential amplifier, having an input arranged to receive a receive signal from the antenna interface; a differential transmitter arranged to generate a differential pair comprising a first transmit signal connected to the first signal path and a second transmit signal connected to the second signal path; a switching network arranged to divert the amplifier output on the second signal path to a signal ground node. The receive signal on one signal path is diverted to ground. The transmit signal corresponding to the other differential signal path is inserted so that the same transmit signal is present on both differential signal paths. When processed by differential downstream components with high common-mode rejection, the transmit signals cancel out.

Claims

1. A differential transceiver circuit for transmitting and receiving via a single antenna interface, the transceiver circuit comprising: a differential pair of signal paths, comprising a first signal path and a second signal path; a differential amplifier, having an input and an output, the input arranged to receive a receive signal from the antenna interface; a differential transmitter arranged to generate a differential pair of transmit signals for transmission to the antenna interface, the differential pair of transmit signals comprising a first transmit signal connected to the first signal path between the antenna and the receiver input and a second transmit signal connected to the second signal path between the antenna and the receiver input; a switching network on the second signal path arranged on the output side of the differential amplifier and arranged to divert the amplifier output on the second signal path to a signal ground node; and an injection circuit arranged to inject a copy of the first transmit signal onto the second signal path downstream of the switching network.

2. A differential transceiver circuit as claimed in claim 1, wherein the switching network comprises a first switch arranged to selectively connect the second signal path to a transceiver circuit output, and a second switch arranged to selectively connect the second signal path to the signal ground node.

3. A differential transceiver circuit as claimed in claim 1, wherein the injection circuit comprises an injection switch arranged to selectively connect the injection circuit to the second signal path.

4. A differential transceiver circuit as claimed in claim 1, wherein the injection circuit obtains the copy of the first transmit signal directly from the differential transmitter.

5. A differential transceiver circuit as claimed in claim 1, wherein the injection circuit comprises a dummy transmitter circuit substantially identical to one differential half of the differential transmitter, and which is arranged to generate the copy of the first transmit signal.

6. A differential transceiver circuit as claimed in claim 1, wherein the injection path comprises a dummy amplifier.

7. A differential transceiver circuit as claimed in claim 6, wherein the dummy amplifier is substantially identical to one differential half of the differential amplifier.

8. A differential transceiver circuit as claimed in claim 1, wherein the injection path comprises an impedance matching network arranged to match the impedance seen by the copy of the first transmit signal on the injection path to the impedance seen by the first transmit signal on the first signal path.

9. A differential transceiver circuit as claimed in claim 8, wherein the impedance matching network is trimmable.

10. A differential transceiver circuit as claimed in claim 8, wherein the impedance matching network is a resistive-capacitive network.

11. A differential transceiver circuit as claimed in claim 8, wherein the impedance matching network is a resistive-capacitive-inductive network.

12. A differential transceiver circuit as claimed in claim 1, further comprising a controller, the controller arranged such that, during a transmit pulse, it: controls the switching network to divert the amplifier output on the second signal path to the signal ground node; and controls the injection circuit to inject the copy of the first transmit signal onto the second signal path.

13. A transceiver circuit as claimed in claim 2, wherein the switching network comprises a first circuit branch which comprises a first buffer element in series with the first switch.

14. A transceiver circuit as claimed in claim 13, wherein the first buffer element is connected between the first switch and the transceiver circuit output.

15. A transceiver circuit as claimed in any of claims 13, wherein the first switch and the first buffer element each comprise transistors in a common-gate arrangement.

16. A transceiver circuit as claimed in claim 2, wherein the switching network comprises a second circuit branch which comprises a second buffer element in series with the second switch.

17. A transceiver circuit as claimed in claim 16, wherein the second buffer element is connected between the second switch and the signal ground node.

18. A transceiver circuit as claimed in any of claim 16, wherein the second switch and the second buffer element each comprise transistors in a common-gate arrangement.

19. A transceiver circuit as claimed in claim 13, wherein the second switch is identical to the first switch.

20. A transceiver circuit as claimed in claim 16, wherein the second buffer element is identical to the first buffer element.

21. A transceiver circuit as claimed in claim 1, further comprising a controller; wherein the controller is arranged to operate in at least a transmit mode and a receive mode; wherein in the transmit mode, the controller controls the switching network to divert the amplifier output on the second signal path to the signal ground node and controls the injection circuit to inject the copy of the first transmit signal onto the second signal path; and wherein in the receive mode, the controller controls the switching network not to divert the amplifier output on the second signal path to the signal ground node and controls the injection circuit not to inject the copy of the first transmit signal onto the second signal path.

22. A transceiver circuit as claimed in claim 1, wherein the differential amplifier is an impedance matching amplifier arranged to receive the receive signal from the antenna interface and arranged to output an amplified differential signal on the first and second signal paths.

23. A transceiver circuit as claimed in claim 22, wherein the impedance matching amplifier has two differential halves, and each differential half comprises a transistor or multiple transistors arranged in a common-gate and/or a common-source arrangement.

24. A transceiver circuit as claimed in claim 23, wherein the transistor of each differential half comprises a field effect transistor and wherein each differential half of the impedance matching amplifier further comprises a transformer coupling the signal between the gate and the source of the field effect transistor.

25. A transceiver circuit as claimed in claim 24, wherein each field effect transistor is in common-source arrangement and each differential half of the impedance matching amplifier comprises a transformer arranged to amplify the signal at the gate of the field effect transistor.

26. A transceiver circuit as claimed in claim 24, wherein the transformer on each differential signal path is a trifilar transformer with a primary winding connected to the source, a secondary winding connected between the gate and signal ground and a tertiary winding connected between the secondary winding and the gate, wherein the primary winding and the secondary winding are coupled in inverting relationship, wherein the secondary winding and the tertiary winding are coupled to increase voltage at the gate, and wherein there is substantially no coupling between the primary winding and the tertiary winding.

27. A transceiver circuit as claimed in claim 24, wherein the field effect transistor is in common-gate arrangement and each differential half of the impedance matching amplifier comprises a transformer coupling the signal between the source and the drain of the field effect transistor.

28. A transceiver circuit as claimed in claim 27, wherein the transformer on each differential signal path is a trifilar transformer with a primary winding connected to the source, a secondary winding connected to the gate and a tertiary winding connected to the drain, wherein the primary winding and the secondary winding are coupled in an inverting relationship and wherein the primary winding and the tertiary winding are coupled in non-inverting relationship, and wherein there is substantially no coupling between the secondary winding and the tertiary winding.

29. A transceiver comprising: a transmitter circuit, an antenna, a transceiver circuit as claimed in claim 1.

30. A transceiver as claimed in claim 29, wherein the transmitter circuit comprises an impulse or pulse generator.

31. A pulsed radar comprising a transceiver as claimed in claim 30.

32. A method of duplex operation of a differential transceiver circuit via a single antenna interface, wherein the transceiver circuit comprises: a differential pair of signal paths, comprising a first signal path and a second signal path; and a differential amplifier, having an input and an output, the input arranged to receive a differential receive signal from the antenna interface; the method comprising: transmitting a differential signal to the antenna interface, comprising a first transmit signal on the first signal path and a second transmit signal on the second signal path; receiving a differential receive signal on the differential pair of signal paths via the antenna interface; diverting the receive signal on the second signal path from the output side of the differential amplifier to a signal ground node; and injecting a copy of the first transmit signal onto the second signal path in place of the diverted receive signal.

Description

[0050] Certain preferred embodiments of the invention will now be described, by way of example only, and with reference to the accompanying drawings in which:

[0051] FIGS. 1a and 1b show two direct-RF front-end topologies;

[0052] FIG. 2 shows a prior art common-source low-noise amplifier arrangement for half-duplex operation;

[0053] FIG. 3 schematically shows a transceiver circuit according to an embodiment of the invention;

[0054] FIG. 4 shows one embodiment of the invention;

[0055] FIG. 5 shows another embodiment of the invention;

[0056] FIG. 6 is a graph showing the level of transmit cancellation with varying impedances;

[0057] FIG. 7 shows schematically the components of a pulsed radar module.

[0058] FIGS. 1a and 1b show two different general arrangements for a direct-RF radio frequency (RF) transceiver front-end 100. Both of these arrangements are single-port devices, i.e., they have a single antenna 10 that is used for both transmission and reception. Each front-end 100 has an antenna 10, a filter 20, a low-noise amplifier (LNA) 40, an analog-to-digital converter (ADC) 50 and a transmitter 30. As these are direct-RF front ends there are no mixers for up/down conversion. In FIG. 1a, the transmitter 30 is connected to a node between the filter 20 and the LNA 40 while in FIG. 1b it is connected between the antenna 10 and the filter 20. The difference between these arrangements is in whether the output from the transmitter 30 gets filtered by the filter 20. Both of these arrangements are viable for the embodiments described below. Each has advantages. The advantage of the arrangement in FIG. 1a is that the transmitter 30 signal is filtered by the filter 20. This helps to ensure that the transceiver output meets frequency transmission requirements. For example, for an UWB (ultra-wide band) transmitter, there is a spectrum mask that must be adhered to. Applying the filter 20 to the output of the transmitter 30 helps to filter out frequencies that would violate the spectrum mask. However, the filter 20 also results in a certain degree of attenuation. Ideally the filter 20 is transparent to the signals of interest (both outgoing and incoming), but in reality, there is always an insertion loss associated with any passive filter 20. Therefore, placement of the filter 20 as in FIG. 1a means that the transmitter 30 must be higher powered in order to make optimum use of the available spectrum mask (or alternatively, for a given power, the range of the device is compromised by the insertion loss in the filter 20). The full power of the transmitter 30 is also then seen by the receiver parts of the circuit, i.e., the LNA 40 and ADC 50. A higher-powered transmitter 30 can risk damaging these components and therefore placement of the transmitter 30 as in FIG. 1a requires either limiting the power of the transmitter 30 or taking greater precautions to protect the LNA 40 and ADC 50. With the arrangement of FIG. 1b the full power of the transmitter 30 is available to the antenna 10 without loss, but it is unfiltered, hence potentially compromising the spectrum efficiency of the transmitter 30 or requiring additional filtering to be built into the transmitter 30 and/or antenna 10 at extra cost and complexity. However, with this arrangement the output of the transmitter 30 that is seen by the LNA 40, and the ADC 50 is first filtered and thus attenuated by the filter 20, thereby protecting those components somewhat from the high power of the transmitter 30. Such protection is still not generally enough to prevent damage to the LNA 40 and/or ADC 50 from the high signal swing of the transmitter 30, so additional protective measures are still normally required.

[0059] FIG. 2 shows the basic construction of a common-source amplifier 200 with a trifilar transformer for high gain and impedance matching. For maximum gain, the primary winding T.sub.1,p is coupled to the secondary winding T.sub.1,s and the secondary winding T.sub.1,s is coupled to the tertiary winding T.sub.1,t. However, the tertiary winding T.sub.1,t is not coupled to the primary winding T.sub.1,p so as to ensure maximum gain of the amplifier. The turns ratios of T.sub.1,p to T.sub.1,s and T.sub.1,s to T.sub.1,t also affect the impedance matching of the amplifier and therefore both the gain and the impedance matching can be set as desired. The three windings T.sub.1,p, T.sub.1,s and T.sub.1,t, together with the field effect transistor M.sub.1 in common-source arrangement form the impedance matching amplifier. Stacked on top of that amplifier are two common-gate stages each comprising a field effect transistor M.sub.2 or M.sub.3 to increase the output impedance. The topmost common-gate stage transistor M.sub.3 improves reverse isolation by providing a high output impedance and thereby isolating the load (represented by inductor L and capacitor C) from the common-source amplifier stage M.sub.1. Note that both common-gate stages M.sub.2 and M.sub.3 are always-ON. These are not arranged to be switchable. The output RF.sub.o of the amplifier 400 is taken from above the tertiary winding T.sub.1,t such that the tertiary winding T.sub.1,t lies between the output RF.sub.o and the drain of M.sub.1.

[0060] FIG. 3a shows a schematic block diagram of a transceiver circuit 300 according to an embodiment of the invention. A differential antenna 310 is arranged to transmit signals generated by the transceiver circuit 300 as well as to receive signals to be processed by the transceiver circuit 300. The transceiver circuit 300 is differential, comprising a first differential path 351 and a second differential path 352. It will be appreciated that these are normally considered to be a positive path and a negative path. In FIG. 3a the first differential path 351 is the positive path and the second differential path 352 is the negative path. However, the paths could be the other way round without affecting operation. The signal polarity is shown with + and signs in the filter 320 and the LNA 340. Note that there is a signal inversion through the LNA 340 in this particular embodiment.

[0061] A differential filter 320 is connected to the differential antenna 310. The differential filter 320 is bidirectional such that it filters the incoming receive signal from the antenna 310 and also filters the transmit signal from transmitter 330 before passing it to the antenna 310. The type of filter and frequency response will depend on the field of operation of the circuit, but in most cases the filter 320 will be a high pass filter or a band pass filter, optionally with one or more notches to exclude undesired interferers. In the case of UWB applications such as UWB pulsed radars, the filter 320 may be designed to ensure that the transmitted signal conforms to the regulatory frequency mask (e.g., 3.1-10.6 GHz in the USA).

[0062] Receive signal that passes through the filter 320 then passes to a differential low-noise amplifier (LNA) 340 which amplifies the signal for improved processing by downstream components. In this document the term downstream is used with respect to the receive signal such that the LNA 340 is downstream from the filter 320 which is in turn downstream from the antenna 310.

[0063] A differential transmitter 330 is connected between the differential filter 320 and the differential LNA 340 such that it can provide signals 331, 332 onto the first differential signal path 351 and the second differential signal path 352 which then pass through the differential filter 320 and are transmitted from the antenna 310. It will be appreciated that this filter connection arrangement corresponds to that shown in FIG. 1a, but the invention applies equally to other embodiments in which the differential transmitter 330 is connected between the differential antenna 310 and the differential filter 320 as is shown in FIG. 1b.

[0064] Downstream of the differential LNA 340, FIG. 3a shows an ADC 350, although this could be any general differential output which could be any suitable processing components which have high common-mode rejection. The exact form of the output will vary from one application to another, but by way of example, in this embodiment it comprises an ADC 350 which may be connected to a digital signal processor to process the received signals.

[0065] Alongside the main differential signal paths 351, 352, FIG. 3a shows an injection circuit 390. Injection circuit 390 provides a path to connect a copy 333 of the first transmit signal 331 to the second differential signal path 352 downstream of the LNA 340 and downstream of a switching network 380. The copy 333 of the first transmit signal 331 is, in this example, generated by the same transmitter 330 as generates the first transmit signal 331 that is connected to the first differential signal path 351. Thus, the two signals 331, 333 can be generated to be identical (or very nearly identical). This is important as the idea is to use these two signals to cancel each other out later in the processing. The injection circuit 390 comprises a dummy amplifier 360 and an impedance matching network 370. The purpose of these is to make sure that the path of the copy signal 333 through the injection circuit 390 mimics the path of the first transmit signal 331 through the first differential signal path 351. Thus, at the point where the injection circuit 390 injects the amplified copy signal 333 onto the second differential signal path 352, it is identical (or very nearly identical) to the amplified first transmit signal on the first differential signal path 351. To achieve this, the dummy amplifier 360 is designed to amplify the copy signal 333 in exactly the same way as the LNA 340 amplifies the first differential signal path 351, e.g., it has the same gain and the same frequency response. One way to do this is for the dummy amplifier 360 to be an identical design to one differential half of the differential LNA 340. Thus, the dummy amplifier 360 can have the same type and size of transistors as one differential half of the differential LNA 340. The two amplifiers 360, 340 have the same biasing conditions. The impedance matching network 370 simulates the input impedance of one differential half of the LNA 340. The impedance matching network 370 may be a resistive-capacitive network or a resistive-inductive network or a resistive-capacitive-inductive network. The impedance matching network 370 is ideally trimmable so that it can be adjusted to match the impedance as exactly as possible and thereby ensure correspondence of the transmit signals on the two differential paths 351, 352 at the output 350. The impedance matching network 370 should ideally match both real and imaginary parts of the impedance on the first differential signal path 351 at the input to the LNA 340.

[0066] The switching network 380 is provided on the second differential signal path 352 downstream of the LNA 340 and is capable of diverting the signal on the second differential signal path 352 to ground (note that this only needs to be a signal ground rather than a DC ground, so it can be a connection to a power rail such as V.sub.dd). More generally, signal ground can be any ground to which the signal can be dissipated. This may be a positive or negative voltage rail, an AC ground, or any other ground connection of the circuit. This leaves the second differential signal path 352 downstream of the switching network 380 disconnected from the rest of the receive architecture (i.e., disconnected from the antenna 310, filter 320 and LNA 340. Diverting the second differential signal path 352 to ground therefore also changes the receiver from differential to single-ended (as receive signal is now only present on the first differential signal path 351). In place of the diverted signal on the second differential signal path 352, the injection circuit provides the amplified copy signal 333 which should match exactly the first transmit signal 331 from the differential transmitter 330 that has passed through the LNA 340. Therefore, at this point in the transceiver circuit 300 (i.e., at the input to the differential output block (e.g., ADC 350), both the first differential signal path 351 and the second differential signal path 352 have identical (or very nearly identical) copies of the amplified first transmit signal 331. Any downstream processing that has high common-mode rejection will eliminate these identical signals and all that is left will be any receive signal present on the first differential signal path 351.

[0067] Although this process results in the loss of half the differential receive signal that is received by the differential antenna 310 (i.e., the loss of the half that is diverted to ground by the switching network 380), the big advantage of this transceiver circuit is that it can continue to receive even while transmitting. Thus, the transceiver circuit 300 can operate in a pseudo-full-duplex mode. We refer to this as pseudo-full-duplex rather than full-duplex as the circuit 300 needs to throw away half the received signal during the transmit pulse. Notably, this pseudo-full-duplex operation is all possible with a single differential antenna 310 rather than the two separate antennae that are normally used for full duplex operation.

[0068] When the transceiver 300 is not transmitting (which may be most of the time in a pulsed system such as a pulsed radar), the switching network 380 can be switched to not divert the signal to ground, e.g., to connect the second differential signal path 352 to the output (e.g., output block 350). In this mode of operation, the receive signal is received and processed fully-differentially throughout the path from antenna 310 to output 350 and therefore preserves the full signal swing of the received signal for optimal processing. In this mode the injection circuit has no effect as no copy signal 333 is produced by the transmitter 330.

[0069] FIG. 3b is identical in most respects to FIG. 3a and most of its description is therefore omitted here. The difference is that instead of the transmitter 330 generating the copy signal 333, a separate dummy transmitter 335 is provided as part of the injection circuit 390. The dummy transmitter 335 is a copy of the one half of the differential transmitter 330, i.e., it may be identical to one differential half of the differential transmitter 330 and thus the dummy transmitter 335 generates an identical signal to the first transmit signal 331, i.e., it generates the copy 333 of the first transmit signal 331.

[0070] FIG. 4 shows a first implementation of the LNA 340 and injection circuit 390 of the transceiver circuit 300 at transistor level. The antenna 310, filter 320 and transmitter 330 are not shown here for simplicity, but for reference, the first differential signal path 351 from the output of the filter 320 and the transmitter 330 is provided at Port 1. The second differential signal path 352 from the output of the filter 320 and the transmitter 330 is provided at Port 0. The copy signal 333 of the first transmit signal 331 is provided at Port 3.

[0071] The inputs at Port 0 and Port 1 are the differential input to the differential LNA 340. In FIG. 4, each differential half of the differential LNA 340 is implemented by a field effect transistor M.sub.1, M.sub.2 arranged in common-source configuration and with a trifilar transformer connected to its terminals for enhancing the gain and impedance matching. The trifilar transformer on M.sub.1 comprises a primary winding T.sub.1,p connected to the source of M.sub.1, a secondary winding T.sub.1,s connected between the gate of M.sub.1 and ground (signal ground, in this case a DC bias voltage V.sub.1) and a tertiary winding T.sub.1,t connected between the secondary winding and the gate of M.sub.1. Mutual coupling between the primary winding and the secondary winding with inverting relationship enhances the gate-source voltage, thereby enhancing the gain of M.sub.1. Mutual coupling between the secondary winding T.sub.1,s and the tertiary winding T.sub.1,t further enhances the gate voltage of M.sub.1 and thereby further enhances the gain. The coupling between the primary winding T.sub.1,p and the tertiary winding T.sub.1,t is ideally kept as low as possible, and with the right trifilar set up can be largely eliminated for maximum gain. As the input impedance of the amplifier depends on the transconductance g.sub.m of M.sub.1 as well as the turns ratios of the trifilar windings, the gain can be optimized while also ensuring correct impedance matching. It will be appreciated that the arrangement of M.sub.2 on the first signal path 351 is exactly the same.

[0072] At the output of the amplifier 340 (i.e., at the drain of M.sub.1), a switching network 380 is provided which has a first circuit branch 381 connecting the output of the amplifier to the load (represented here by inductors L, i.e., the transceiver circuit output) and a second circuit branch 382 which diverts the output of the amplifier to a signal ground (in this case the supply rail V.sub.dd). The first circuit branch 381 comprises a first switch 383 in series with a first buffer element 384. The second circuit branch 382 comprises a second switch 385 in series with a second buffer element 396. Each of the buffer elements 384, 386 is arranged in common-gate arrangement such that they are always-ON. The first buffer element 384 provide a high output impedance and good reverse isolation such that the load does not affect the biasing (and thus impedance matching) of the amplifier 340. The first switch 383 and the second switch 385 provide the means by which to select whether to divert or not divert the amplifier output to the signal ground node. When the first switch 383 is ON and the second switch 385 is OFF, the amplifier output (and thus the second differential signal path 352) is connected to the load (transceiver circuit output). When the first switch 383 is OFF and the second switch 385 is ON, the amplifier output (and thus the second differential signal path 352) is connected to the signal ground node (e.g., V.sub.dd). The first switch 383 is identical to the second switch 385 and the second buffer element 386 is identical to the first buffer element 384. Identical here means the same characteristics such as size and strength. The two circuit branches 381, 382 are identical so that the amplifier 340 always sees an identical load regardless of which path is connected. This ensures that the biasing of the amplifier 340 (and thus its impedance matching) is not affected by switches between the transmit mode and the receive mode, i.e., when the switching network 380 changes state.

[0073] While the main function of the switching network is to select one path to connect the amplifier output to (i.e., so that one switch is ON and the other is OFF), it will be appreciated that it is also possible to switch both the first switch 383 and the second switch 385 ON so as to divide the signal with half going to ground and half going to the transceiver circuit output. Such operation may be useful in receive mode if a particularly strong signal is amplified too much by the amplifier 340. Connecting both circuit branches 381, 382 in parallel provides a degree of gain control to reduce the signal amplitude at the transceiver circuit output.

[0074] It will be appreciated that the structure at the output of transistor M.sub.2 on the first differential signal path is identical to that described above and is therefore not described further here, except to note that the switching network on this path is generally not used for diverting the signal unless it is desired to switch the whole receiver side off (e.g., for half-duplex operation). The switching network here still has functionality though as it provides symmetry with the switching network on the second differential signal path.

[0075] The injection circuit 390 is shown from the input at Port 3 (which takes the copy 333 of the first transmit signal 331 from the transmitter) to the connection at the node on first circuit branch 381 between the first switch 383 and the first buffer element 384 where the injection signal is injected onto the second differential signal path 352 downstream of the first switch 383. The injection circuit 390 has components identical to those on the second differential signal path 352 as described above. Thus, the injection circuit 390 includes an amplifier which comprises a field effect transistor M.sub.3 in common-source arrangement with a trifilar transformer X.sub.1 connected to its terminals. The transistor M.sub.3 is identical to transistor M.sub.1 and the windings of the trifilar transformer X.sub.1 are identical to those of transformer T.sub.1, i.e., T.sub.1,p=X.sub.1,p, T.sub.1,s=X.sub.1,s, T.sub.1,t=X.sub.1,t. As the amplifier components are identical on the injection circuit 390 to those on the second differential signal path 352, the outputs should be identical. Notably, the amplifier M.sub.2 and the trifilar windings connected to it are also identical to those of M.sub.1 and M.sub.3 so that a transmit signal sent along any of these three routes should be processed (e.g., amplified) identically.

[0076] As indicated in FIG. 4, when the injection circuit 390 is in operation, the receive signal at Port 1 on the first signal path 351 includes both the positive receive signal +Rx from the positive arm of the antenna and the positive transmit signal 331, +Tx from the positive arm of the transmitter 330. The receive signal at Port 0 on the second signal path 352 includes the negative receive signal Rx from the negative arm of the antenna and the negative transmit signal 332, Tx from the negative arm of the transmitter 330. Port 3 of the injection circuit 390 receives the copy signal 333 from the transmitter 330 or the dummy transmitter 335. The first switch 383 is OFF so as to block the output at the drain of M.sub.1 from progressing to the load. Instead, the second switch 385 is ON thereby diverting the output at the drain of M.sub.1 to signal ground (the supply rail V.sub.dd) through the buffer element 386. The injection circuit injects its output onto the node on first circuit branch 381 between the first switch 383 and the first buffer element 384. Now, as shown at the top of FIG. 4 between the inductors, the differential output is the difference between the output at the drain of buffer element 384 and the output at the drain of third buffer element 387 on the opposite signal path. The output at the drain of first buffer element 384 is A(Tx). A( ) represents the amplification factor of the LNA 340 (or the dummy LNA 360) and the negative sign is because the amplifier in this example causes signal inversion (+Tx at the input becomes Tx at the output). The output at the drain of third buffer element 387 is A(TxRx). A( ) is the same amplification factor (because the amplifier in the injection circuit 390 is designed to be identical to the amplifier on the first differential signal path 351) and the negative signs are again because the amplifier in this example causes signal inversion (+Tx+Rx at the input becomes TxRx at the output). Therefore, the differential output is A(Tx)A(TxRx)=A(Rx). Therefore, the transmit signal has been fully cancelled and the remaining signal is just the single-ended receive signal from the first differential signal path 351 which can be processed even during the transmit operation, thereby effecting a pseudo-full-duplex operation.

[0077] The switches 383 and 385 on the second signal path 352 are controlled by control signals .sub.2 and .sub.1 respectively. The corresponding switches on the first signal path are controlled by control signals .sub.4 and .sub.5 respectively. The switch 388 on the injection circuit 390 is controlled by control signal .sub.3. All of these control signals may be generated by controller 395.

[0078] For normal receive mode operation, the injection circuit is not required, so .sub.3 is low (OFF). The signals on both differential signal arms 351, 352 are connected to the output to pass receive signal, so .sub.2 and .sub.4 are high (ON). No signal is to be diverted to ground, so .sub.1 and .sub.5 are low (OFF).

[0079] For full-duplex or pseudo-full-duplex mode operation, the first differential signal path passes the signal as normal, with no diversion to ground, so control signal .sub.5 is low (OFF) and control signal .sub.4 is high (ON). The second differential signal path 352 diverts the received signal to signal ground, so control signal .sub.2 is low (OFF), while control signal .sub.1 is high (ON). The injection circuit 390 is active to inject the copy signal 333 onto the second signal path 352 so control signal .sub.3 is high (ON). The circuit can also be operated in half-duplex mode if desired. For half-duplex mode operation, the injection circuit 390 is not used and so control signal .sub.3 is low (OFF). During receive mode, the control signals .sub.2 and .sub.4 are high (ON) so as to pass the receive signal, while control signals .sub.1 and .sub.5 can be either low (OFF) for full receive mode or high (ON) for gain control mode. During transmit mode, the receiver is simply blocked and so signals .sub.2 and .sub.4 are low (OFF), and signals .sub.1 and .sub.5 can be either low (OFF) or high (ON). Only for the latter is the amplifier impedance matched (i.e., it sees proper biasing conditions) and therefore this option is preferred in some embodiments.

[0080] FIG. 5 shows a second implementation of the LNA 340 and injection circuit 390 of the transceiver circuit 300 at transistor level. FIG. 5 is very similar to FIG. 4 and therefore much of the description is omitted here and only the different arrangement of the injection circuit 390 is described.

[0081] In FIG. 5, the transmit signal (the first transmit signal 331 and the second transmit signal 332 as well as the copy transmit signal 333) can be applied directly to the gates of M.sub.1, M.sub.2, and M.sub.3. This reduces complexity and area as trifilar transformer X.sub.1 is not required. For near perfect transmit signal cancellation, the impedance at the gate of M.sub.3 must be equal to the impedance at the gate of M.sub.1 (or M.sub.2). This is achieved via an impedance matching network as shown in FIG. 3a and FIG. 3b (but not shown in FIG. 5 for simplicity). In addition, with the transmit signal applied directly at the gates of M.sub.1, M.sub.2, and M.sub.3, the off-capacitance of the transmitter, Tx, becomes a greater concern due to its effect being amplified through the secondary and tertiary windings T.sub.1,s, T.sub.1,t. Effectively the off-capacitance of the transmitter that is seen at the antenna is multiplied up by a factor that depends on the turns ratios. Therefore, this arrangement is particularly beneficial when the off-capacitance of the transmitter is low, i.e., low enough that this effect does not e.g., degrade the impedance match or increase insertion loss.

[0082] FIG. 6 is a graph showing the level of transmit signal cancellation (on the vertical axis) that can be achieved by embodiments of the invention. The horizontal axis shows imaginary load in Femtofarads (fF), and the two curves show how the cancellation varies for two different resistances (one shows 44 Ohms, the other 50 Ohms). Both curves show a good level of cancellation. For example, a 20 dB cancellation is considered a realistic target level of cancellation to achieve (a factor of 10 reduction) and both curves achieve this across nearly the full range of imaginary impedances shown on the graph. However, there is a clear benefit when the real part of the impedance is matched more effectively. In this case, the 44 Ohm real impedance has a pronounced peak around 3 fF where a cancellation of 50 dB can be achieved. With this real impedance, an imaginary impedance of anywhere between 0 and 5 fF achieves greater than 40 dB of cancellation.

[0083] FIG. 7 shows a pulsed (or impulse) radar 700 which comprises a module 760 on which is mounted an antenna 710 and a semiconductor chip 750. The antenna 710 connects to the semiconductor chip 750 via an antenna interface 715. The semiconductor chip 750 contains a filter 720, a transmitter 730 and an amplifier 740 which may be circuits as described above and shown in the preceding figures. In this embodiment the antenna 710, antenna interface 715, filter 720, transmitter 730 and amplifier 740 are all differential.

[0084] It will be appreciated that variations and modifications of the above circuits may be made without departing from the scope of the appended claims.