AN ELECTRONIC RECTIFIER CIRCUIT FOR ADAPTIVE GATE VOLTAGE REGULATION OF A SYNCHRONOUS RECTIFIER FIELD-EFFECT TRANSISTOR

Abstract

An electronic rectifier circuit for adaptive gate voltage regulation of a synchronous rectifier field-effect transistor is provided, the electronic rectifier circuit is configured to clamp a drain-source voltage of the SR FET to a first regulation voltage while the SR FET is switched on for less than a threshold time in a current switching cycle, and the electronic rectifier circuit is configured to clamp the Vds of the SR FET to a second regulation voltage while the SR FET is switched on for more than the threshold time in the current switching cycle, the threshold time is configured as a portion of time that the SR FET was switched on in one or more previous switching cycles, and Vreg2 is smaller than Vreg1.

Claims

1. An electronic rectifier circuit comprising: a synchronous rectifier field-effect transistor (SR FET); wherein the electronic rectifier circuit is configured for adaptive gate voltage (Vg) regulation of the SR FET; wherein the electronic rectifier circuit is configured to clamp a drain-source voltage (Vds), of the SR FET to a first regulation voltage (Vreg1), while the SR FET is switched on for less than a threshold time in a current switching cycle; wherein the electronic rectifier circuit is configured to clamp the Vds of the SR FET to a second regulation voltage (Vreg2), while the SR FET is switched on for more than the threshold time in the current switching cycle; wherein the threshold time is configured as a portion of time that the SR FET was switched on in one or more previous switching cycles; and wherein Vreg2 is smaller than Vreg1.

2. The electronic rectifier circuit according to claim 1, comprising: a first Vg detection part configured to measure an amount of time that the SR FET is switched on and store a first signal representative of the amount of time in a sample holder; a second Vg detection part configured to measure a further amount of time that the SR FET is switched on to obtain a second signal; a comparator having as inputs, the first signal obtained from the sample holder and the second signal, and having as an output a selection signal; a multiplexer configured to output Vreg1 or Vreg2 depending on the selection signal.

3. The electronic rectifier circuit according to claim 2, wherein the first Vg detection part comprises a first capacitor, and wherein the second Vg detection part comprises a second capacitor, wherein the first capacitor and the second capacitor are dimensioned in a ratio defining the threshold time.

4. The electronic rectifier circuit according to claim 3, wherein the second capacitor is dimensioned at 90% of the value of the first capacitor.

5. A fast-charging power supply comprising a transformer, a primary side field-effect transistor (Pri FET), a synchronous rectifier field-effect transistor (SR FET), and an electronic rectifier circuit according to claim 1.

6. A method of adaptive gate voltage (Vg), regulation of a synchronous rectifier field-effect transistor (SR FET), the method comprising: turning on the SR FET by setting the Vg of the SR FET to high; starting a timer for counting an on-time of the SR FET in a current switching cycle; determining whether the on-time of the SR FET exceeds at least a portion of a previous on-time of the SR FET in one or more previous switching cycles; clamping a drain-source voltage (Vds), to a first regulation voltage (Vreg1), if the on-time does not exceed the portion of the previous on-time; and clamping Vds to a second regulation voltage (Vreg2), if the on-time exceeds the portion of the previous on-time.

7. The method according to claim 6, further comprising: turning on the SR FET after detecting that the Vds of the SR FET is below a turn on threshold value (Von_th).

8. The method according to claim 6, further comprising: after clamping the Vds to the Vreg2, determining if the Vds of the SR FET exceeds a turn off threshold value (Voff_th); and if the Vds of the SR FET exceeds the Voff_th, turning off the SR FET by setting the Vg to low.

9. The method according to claim 6, further comprising: after the SR FET has been turned off, stopping the timer and storing the on-time of the SR FET obtained by the timer for use as the previous on-time in a next switching cycle.

10. The method according to claim 7, further comprising: after clamping the Vds to the Vreg2, determining if the Vds of the SR FET exceeds a turn off threshold value (Voff_th); and if the Vds of the SR FET exceeds the Voff_th, turning off the SR FET by setting the Vg to low.

11. The method according to claim 7, further comprising: after the SR FET has been turned off, stopping the timer and storing the on-time of the SR FET obtained by the timer for use as the previous on-time in a next switching cycle.

12. The method according to claim 8, further comprising: after the SR FET has been turned off, stopping the timer and storing the on-time of the SR FET obtained by the timer for use as the previous on-time in a next switching cycle.

13. A fast-charging power supply comprising a transformer, a primary side field-effect transistor (Pri FET), a synchronous rectifier field-effect transistor (SR FET), and an electronic rectifier circuit according to claim 2.

14. A fast-charging power supply comprising a transformer, a primary side field-effect transistor (Pri FET), a synchronous rectifier field-effect transistor (SR FET), and an electronic rectifier circuit according to claim 3.

15. A fast-charging power supply comprising a transformer, a primary side field-effect transistor (Pri FET), a synchronous rectifier field-effect transistor (SR FET), and an electronic rectifier circuit according to claim 4.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0023] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbol indicate corresponding parts, in which:

[0024] FIG. 1 shows a high-power fast-charging power supply with flyback circuit architecture.

[0025] FIG. 2 shows a graph of currents, voltages and time delays of a prior art fast-charging power supply during light CCM.

[0026] FIG. 3 shows a graph of currents, voltages and time delays of a prior art fast-charging power supply during deep CCM or when a high Rdson FET is used.

[0027] FIG. 4 shows an electronic rectifier circuit for adaptive gate Vg regulation of a SR FET, according to an example embodiment of the present disclosure.

[0028] FIG. 5 shows a graph of currents, voltages and time delays of an electronic rectifier circuit for adaptive gate Vg regulation of a SR FET in a DCM or a light CCM mode, according to an example embodiment of the present disclosure.

[0029] FIG. 6 shows a graph of currents, voltages and time delays of an electronic rectifier circuit for adaptive gate Vg regulation of a SR FET in a deep CCM mode, according to an example embodiment of the present disclosure.

[0030] FIG. 7 shows a graph of currents, voltages and time delays of an electronic rectifier circuit for adaptive gate Vg regulation of a SR FET in a resonant mode converter, according to an example embodiment of the present disclosure.

[0031] FIG. 8 shows a flow chart of a method of adaptive gate Vg regulation of a SR FET, according to an example embodiment of the present disclosure.

[0032] The figures are intended for illustrative purposes only, and do not serve as restriction of the scope of the protection as laid down by the claims.

DETAILED DESCRIPTION

[0033] It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0034] The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the present disclosure is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0035] Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present disclosure should be or are in any single example of the present disclosure. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same example.

[0036] Furthermore, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the present disclosure can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. Reference throughout this specification to one embodiment, an embodiment, or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases in one embodiment, in an embodiment, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0037] FIG. 4 shows a circuit block diagram of a circuit 400 for adaptive Vg regulation according to an example embodiment. The circuit 400 may replace the driver circuit 108 of FIG. 1. Circuit 400 enables a pre-regulation gate voltage (Vpre_gate) of a gate 402 to be adaptively regulated to a regulated gate voltage (Vreg_gate). The Vreg_gate may be provided to the SR FET, depicted by block 404.

[0038] The circuit 400 may include a first Vg detection part 410 for detecting and storing an on-time duration of the SR in one or more previous switching cycles. For example, a signal representative of the on-time duration of the SR of two previous switching cycles may be measured and stored in a sample holder 430. The circuit 400 may further include a second Vg detection part 420 for detecting an on-time duration of the SR in a current switching cycle.

[0039] A selector 440 may determine if the conduction time (i.e., on-time) of the SR FET in the current switching cycle is within a predefined portion of an on-time duration of the previous switching cycles. For example, if the on-time duration of the current switching cycle is to be within 90% of the on-time duration of the previous switching cycles, second capacitor 422 may be dimensioned at 90% of first capacitor 412, as depicted in the example of FIG. 4 for capacitors 422 and 412 as 0.9 C and C, respectively.

[0040] A comparator 442 may compare the on-time of the current switching cycle with the on-time of the previous switching cycles, which result may be output as a selection signal to a multiplexer 444 for selecting a Vreg2 446 or a Vreg1 448, depending on whether the conduction time of the SR FET in the current switching cycle is below or above the threshold time.

[0041] The selected regulation voltage level may then be provided to an operational transconductance amplifier (OTA) 450 for generating Vreg_gate. Thus, adaptive Vg regulation may be achieved by adapting Vreg_gate using Vreg2 and Vreg1.

[0042] For example, if the conduction time (i.e., on-time) of the SR FET in the current switching cycle is within a threshold time, e.g., 90% of the on-time duration of the two previous cycles, the selector 440 may selects a channel 0 of the multiplexer 444 for a regulation voltage of Vreg1 448. Until the threshold time, the regulation voltage of the OTA 450 is Vreg1 448, which may be input to the non-inverting input terminal of the OTA 450. Vds sampling voltage may be input to the inverting input terminal of the OTA 450, so to adjust the gate driver voltage Vg after amplification by the OTA 450. The lower the Vg, the higher the Rdson of the SR FET, which results in lower Vds voltage (the current flows from the source(S) pin to the drain (D) pin of the SR FET). If the Vds voltage is too low, the OTA 450 increases the Vg to increase the Vds voltage, so to keep it equal to the regulation voltage.

[0043] For example, if the conduction time (i.e., on-time) of the SR FET in the current switching cycle reaches the threshold time, e.g., of 90% of the on-time duration of the two previous cycles, the selector 440 may select a channel 1 of the multiplexer 444 for a regulation voltage of Vreg2 446. Vds may then be stabilized at Vreg2 by further reducing Vg. Vg may drop sharply and quickly reach the turn on threshold voltage of the SR FET when the Pri FET on signal arrives, so to quickly turn off the SR FET.

[0044] FIG. 5 shows a first example graph 500 of currents, voltages and time delays for the circuit 400 in a DCM or a light CCM mode. Lines are shown for the SR current 502, the SR voltage 504 and Vg. In the Y-axis direction, voltage levels are indicated for a Vg_th, a Von_th, a Voff_th, Vreg2 and Vreg1. The X-axis represents time. In the X-axis direction, the time on delay 510, the time off delay 512 and 90% 506 of the on-time (Ton) are indicated.

[0045] In light CCM mode the inductor current in a converter typically remains in continuous conduction throughout most of the switching cycle, but for a short duration it may drop to zero or near zero. As can be seen in the graph 500, the Vds voltage (i.e., SR voltage 504) may be increased to the first regulation level Vreg1 and clamped to Vreg1 before 90% (506) of the last Ton cycle is reached. The gate driver voltage may be decreased when Vds voltage is regulated at Vreg1. The Vds voltage (i.e., SR voltage 504) may be pulled down from the Vref2 clamping level to the second regulation level Vreg2 and clamped to Vreg2 when 90% (506) of the on-time duration Ton is reached. Since Vreg2 is typically much lower than Vreg1, Vg may drop at a faster slope and close to the turn-off threshold of the SR FET. As a result, the SR FET may be quickly turned off within a short time 512 when the turn on signal of the Pri FET arrives.

[0046] FIG. 6 shows a second example graph 600 of currents, voltages and time delays for the circuit 400 in deep CCM mode. Lines are shown for the SR current 602, the SR voltage 604 and Vg. In the Y-axis direction, voltage levels are indicated for a Vg_th, Vreg2 and Vreg1. The X-axis represents time. In the X-axis direction, the time on delay 610 and the time off delay 612 are indicated.

[0047] In deep CCM mode the inductor current in a converter typically remains in continuous conduction for the whole cycle and the current change amplitude is typically relatively small compared to the peak current. As can be seen in the graph 600, the Vds voltage may not trigger the second clamping level at the first regulation voltage Vreg1. When the time reaches 90% of the on-time duration, the circuit may directly pull the clamping level to the first clamping level at the second regulation voltage Vreg2. At this moment, Vg may drop at a fast slope and close to the turn-off threshold of the SR FET. As a result, the SR FET may be quickly turned off within a short time, i.e., short Toff delay 612, when the turn on signal of the Pri FET arrives.

[0048] FIG. 7 shows a third example graph 700 of currents, voltages and time delays for the circuit 400 in a resonant mode converter. Lines are shown for the SR current 702, the SR voltage 704 and Vg. In the Y-axis direction, voltage levels are indicated for a Vg_th, Vreg2 and Vreg1. The X-axis represents time. In the X-axis direction, the time on delay 710 and the time off delay 712 are indicated.

[0049] In resonant mode, also known as resonant switching or resonant operation, power converters may utilize resonant components (inductors and capacitors) to achieve efficient power conversion. As can be seen in the graph 700, Vds of the same SR FET may pass through the first and second stages of clamping under control of the first regulation voltage Vreg1 and the second regulation voltage Vreg2, respectively. The SR FET may be quickly turned off within a short time, i.e., Toff delay 712, when the turn on signal of the Pri FET arrives.

[0050] Comparing FIGS. 2-3 to FIGS. 5-7, it is clear that the circuit 400 advantageously enables a much shorter Toff delay 512, 612, 712 with adaptive Vg regulation. As a result, the switch device, such as the SR FET, will experience less stress, less cross conduction loss and have better reliability.

[0051] FIG. 8 shows an example control flow 800 of a SR FET of an example embodiment of the present disclosure. The control flow 800 starts at step 802. Reference A indicates a continuous loop, i.e., the flow ends and starts with A.

[0052] In step 804 an SR control integrated circuit (IC) may detect Vds.

[0053] In step 806 it may be determined whether the detected Vds is smaller than the turn on level: Vds<Von_th? If this is not the case, the control flow 800 may return to step 804. Otherwise, if this is the case, the control flow 800 may continue at step 808.

[0054] In step 808 Vg may be set to high to turn on the SR FET, and in step 810 a timer for measuring the on-time of the SR FET may be started.

[0055] In step 812 it may be determined whether the present on-time duration of the SR FET exceeds a percentage of the on-time duration of one or more previous switching cycles of the SR FET. Hereto, the on-time duration of the one or more previous switching cycles is, e.g., obtained from sample holder 420. For example, it may be determined: Ton_present_cycle>90% of Ton_previous_two_cycles? If this is not the case, the control flow 800 may continue at step 814. Otherwise, if this is the case, the control flow 800 may continue at step 820.

[0056] In step 814 it may be determined whether Vds exceeds the first regulation voltage Vreg1: Vds>Vreg1? If this is the case, the control flow 800 may continue at step 816. Otherwise, if this is not the case, the control flow 800 may return to step 812.

[0057] In step 816 Vg may be regulated to keep (i.e., clamp) Vds at the first regulation voltage Vreg1: Vds=Vreg1. The control flow 800 may then return to step 812.

[0058] In step 820 Vg may be regulated to keep (i.e., clamp) Vds at the second regulation voltage Vreg2: Vds=Vreg2.

[0059] In step 822 it may be determined whether Vds exceeds the turn off level: Vds>Voff_th? If this is not the case, then the control flow 800 may return to step 820. Otherwise, if this is the case, the control flow 800 may continue at step 824.

[0060] In step 824 Vg may be set to low to turn off the SR FET, and in step 826 the total on-time duration of the present switching cycle (i.e., Ton) may be stored, e.g., in sample holder 420.

[0061] In step 828 the timer for measuring the on-time of the SR FET may be stopped, e.g., reset to zero, and the control flow 800 may run again for a next switching cycle, as depicted by the reference A.