CLOCK AND DATA RECOVERY

Abstract

A method and a circuitry to perform clock and data recovery, CDR is provided. The method includes the steps of obtaining an analogue communication signal characterized by a symbol frequency F.sub.symbol; and performing an analogue-to-digital conversion of the analogue communication signal according to a sampling rate F.sub.sample targeting F.sub.symbol*(M/L) thereby obtaining a digital signal. The method includes up-sampling the digital signal by L; filtering the up-sampled digital signal with filter coefficients of a finite impulse response, FIR, filter to perform a fractionally-spaced equalisation; and down-sampling the filtered digital signal by M resulting in a recovered digital signal. Intermediate filter coefficients are obtained for the FIR filter and a phase error is determined based on the recovered digital signal. The intermediate filter coefficients are interpolated based on the phase error to compensate for the phase error, resulting in interpolated filter coefficients; and the filter coefficients of the FIR filter are updated with the interpolated filter coefficients.

Claims

1. A method for performing clock and data recovery, CDR, the method comprising the steps of: obtaining an analogue communication signal characterized by a symbol frequency F.sub.symbol; performing an analogue-to-digital conversion of the analogue communication signal according to a sampling rate F.sub.sample targeting F.sub.symbol*(M/L) thereby obtaining a digital signal, wherein M and L are natural numbers larger than zero; up-sampling the digital signal by L; filtering the up-sampled digital signal with filter coefficients of a finite impulse response, FIR, filter to perform a fractionally-spaced equalisation; down-sampling the filtered digital signal by M resulting in a recovered digital signal; obtaining intermediate filter coefficients for the FIR filter; determining a phase error based on the recovered digital signal; interpolating the intermediate filter coefficients based on the phase error to compensate for the phase error, resulting in interpolated filter coefficients; and updating the filter coefficients of the FIR filter with the interpolated filter coefficients.

2. The method according to claim 1, wherein the obtaining of the intermediate filter coefficients comprises calculating the intermediate filter coefficients according to an adaptive filter algorithm based on the digital signal and the recovered digital signal.

3. The method according to claim 1, wherein the intermediate filter coefficients characterize an underlying filter impulse response, and wherein the interpolating comprises shifting the underlying filter impulse response based on the phase error.

4. The method according to claim 1, further comprising shifting the intermediate filter coefficients when the phase error is at least half of an equivalent time between the intermediate filter coefficients in absolute value, to further compensate for the phase error.

5. The method according to claim 1, wherein the FIR filter is a polyphase FIR filter with L phases.

6. The method according to claim 1, further comprising equalising the recovered digital signal according to an additional equalisation scheme.

7. The method according to claim 1, wherein the determining of the phase error comprises applying a low-pass filtering operation on the phase error.

8. The method according to claim 1, further comprising calculating a frequency correction based on the phase error and applying the frequency correction to the sampling rate F.sub.sample thereby compensating for frequency deviations from the symbol frequency F.sub.symbol.

9. The method according to claim 1, further comprising, before the up-sampling, demultiplexing the digital signal as N parallel digital signals, and performing subsequent steps in parallel.

10. The method according to claim 1, further comprising buffering the digital signal through an elastic buffering scheme, and further comprising shifting the digital signal in the buffering scheme when the phase error exceeds a sampling period associated with the sampling rate F.sub.sample, to further compensate for the phase error.

11. A circuitry for clock and data recovery, CDR, the circuitry comprising: an analogue-to-digital converter, ADC, configured to perform an analogue-to-digital conversion of an analogue communication signal according to a sampling rate F.sub.sample targeting F.sub.symbol*(M/L) thereby obtaining a digital signal, wherein M and L are natural numbers larger than zero; an up-sampler, configured to up-sample the digital signal by L; a filter, configured to filter the up-sampled digital signal with filter coefficients of a finite impulse response, FIR, filter to perform a fractionally-spaced equalisation; a down-sampler, configured to down-sample the filtered digital signal by M resulting in a recovered digital signal; a sub-circuitry configured to obtain intermediate filter coefficients for the FIR filter; a phase error calculation circuitry configured to determine a phase error based on the recovered digital signal; and an interpolator configured to interpolate the intermediate filter coefficients based on the phase error to compensate for the phase error, resulting in interpolated filter coefficients, and configured to update the filter coefficients of the FIR filter with the interpolated filter coefficients.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Some example embodiments will now be described with reference to the accompanying drawings.

[0043] FIG. 1 shows an example embodiment of a circuitry for performing clock and data recovery, CDR;

[0044] FIG. 2 illustrates a phase error;

[0045] FIG. 3 illustrates an analogue-to-digital conversion in a CDR circuitry according to an example embodiment;

[0046] FIG. 4 illustrates an up-sampling in a CDR circuitry according to an example embodiment;

[0047] FIG. 5 illustrates a filtering and a down-sampling in a CDR circuitry according to an example embodiment;

[0048] FIG. 6 shows a plot representing intermediate filter coefficients;

[0049] FIG. 7 shows an example embodiment of interpolating intermediate filter coefficients;

[0050] FIG. 8 shows an example embodiment of shifting intermediate filter coefficients; and

[0051] FIG. 9 shows an example embodiment of a circuitry for performing clock and data recovery, CDR.

DETAILED DESCRIPTION

[0052] Example embodiments relate to a circuitry and a method for performing CDR. Such a circuitry may, for example, be used in passive optical networks, PONs, and example embodiments will be further explained in the context of PONs, merely for illustrative purposes. In PONs, data is generally exchanged between a terminal and a collection of users units. In a downstream mode, data is sent continuously through the PON in the form of consecutive frames from the terminal to the collection of user units. Therein, user units only analyse those frames which are identified as intended for them. The identifying is done by examining a header of the frame. In an upstream mode, user units are coordinated to alternately send data bursts over the PON to the terminal, i.e. according to a time division multiple access, TDMA, scheme. The downstream mode and upstream mode alternate each other according to network requirements. The CDR circuitry can handle receiving analogue communication signals at the terminal as well as at the user units. The figures depict the functional parts of a circuitry according to example embodiments. When a circuitry component is described by its function, it may also be considered as performing a step of a method according to its use.

[0053] FIG. 1 shows an example embodiment of a circuitry (100) and corresponding method for performing clock and data recovery, CDR, at a receiving end. The method (100) comprises obtaining (101) an analogue communication signal (10) characterized by a symbol frequency F.sub.symbol. An incoming analogue communication signal (10) has been created at a transmitting end targeting the symbol frequency. The symbol frequency is typically determined beforehand according to a technology standard such as the NG-EPON standard for a PON. The actual symbol frequency of the analogue communication signal (10) is usually generated by use of a clock circuitry that targets the symbol frequency. By targeting by use of a clock circuitry, the symbol frequency can be very closely approximated.

[0054] Next, the analogue communication signal (10) is converted to a digital signal (20) by an S-bit analogue-to-digital converter, ADC, with S, for example, equal to 8. The ADC transforms a continuous analogue signal to a discrete series of quantized values, i.e. 2.sup.S digital values, thereby quantizing the analogue communication signal (10). The resolution of the ADC is limited by the high data rates in PONs. A clock at a frequency targeting F.sub.symbol*(M/L) is used for sampling during the analogue-to-digital conversion, wherein M/L represents an oversampling rate of the ADC. M/L is chosen to be larger than 1, but preferably smaller than 2 in order to limit the oversampling frequency and therewith associated power consumption. M/L may, for example, be chosen to be 4/3, with M equal to 4 and L equal to 3. These example parameter values of M=4 and L=3 will be used during the remainder of this detailed description for illustrative purposes, but other values may be selected. The analogue communication signal (10) is then sampled approximately every (3/4)*T symbol seconds. A suitable type of ADC for dealing with high PON data rates may e.g. be a time-interleaved successive approximation-register, TI-SAR, ADC.

[0055] FIG. 3 illustrates an analogue-to-digital conversion of the analogue communication signal (10) resulting in the digital signal (20), wherein an oversampling factor of 4/3 is applied, and wherein the ADC is a 3-bit ADC. FIG. 3 shows a first subplot (301), showing the analogue communication signal (10) and showing the targeted symbol period T.sub.symbol (29). A second subplot (302) illustrates how the sampling is performed. At regular intervals of (3/4)*T.sub.symbol at times (33, 34, 35, 36, 37), corresponding samples (38, 39, 41, 42, 43) are taken. When a sample is taken, the value of the analogue communication signal (10) is quantised onto one of the levels (31) provided by the ADC. Because a 3-bit ADC is used in this example, there are 23 or 8 such levels. The result of the quantisation, i.e. the digital signal (20) comprising quantized samples (338, 339, 441, 442, 443), is shown in subplot (303). Because of the oversampling, more than one sample is taken during a symbol period. As the sampling is performed blindly, samples are taken at various positions within the corresponding eye diagram. Blind sampling is understood as not being phase corrected such that the sampling does not target a centre of the eye diagram.

[0056] Returning to FIG. 1, after the analogue-to-digital conversion, the digital signal (20) is processed by a fractionally-spaced equaliser, resulting in a recovered digital signal (30). The fractionally-spaced equaliser comprises an up-sampler with over-sampling factor 3, a FIR filter characterized by a number of filter coefficients, e.g. 8, and, a down-sampler with down-sampling factor 4. After the up-sampling (103) by 3 and the down-sampling (105) by 4, the recovered digital signal (30) is characterized by a frequency approximating F.sub.symbol.

[0057] The up-sampling (103) by a factor 3 is illustrated in FIG. 4. As in FIG. 3, a first subplot (401) shows the analogue communication signal (10) along with the targeted symbol period (29). A second subplot (402) shows again the digital signal (20) constructed by the ADC. The up-sampled result is shown in a third subplot (403), wherein the sample period of the digital signal (20) is divided by 3, resulting in a new sample period. For every period of the digital signal (20), the value of the digital signal (20) is kept for a duration of the new sample period, whereafter two periods of zeros, i.e. samples (44, 45, 46, 47, 48, 49, 51, 52) with a value of zero, are introduced. As such, the frequency is multiplied with the factor 3 and zeros are introduced accordingly.

[0058] FIG. 5 illustrates the down-sampling (105) after filtering (104), which is executed on an up-sampled and filtered digital signal, shown in subplot (502). The filtered digital signal has only been represented illustratively and has the same period length as the up-sampled digital signal, yet with different values. Subplot (501) again shows the analogue communication signal (10) and the targeted symbol period (29). The recovered digital signal is illustrated in subplot (503). By down-sampling (105) by 4, values are kept for 4 periods, resulting in a reduction of the oversampling factor 4/3 and achieving a data rate at a frequency of approximately the symbol frequency. The sample duration of the recovered digital signal (30) again targets the symbol period (29).

[0059] Turning to FIG. 2, an incoming analogue communication signal (10) comprises phase shifts, resulting in varying lengths or, in other words, varying time durations, of incoming symbols. In this example, the analogue communication signal (10) is a non-return to zero, NRZ, signal with consecutive symbols 1, 0, 1, 0. Note that only half of the first symbol 1 is shown. The analogue communication signal (10) is shown as a simplified version of a realistic analogue communication signal (10). For example, the symbol shape may be different and/or distorted, or the signal may comprise a more complex signal, such as a PAM-4 signal. A symbol period (27, 28) of the analogue communication signal (10) is not constant and deviates from the predetermined, targeted symbol period T.sub.symbol (29). This is caused by non-idealities of the clock circuitry at the transmitting end, e.g. jitter and drift, as well as other non-idealities of the circuitry at the transmitting end and of the PON channel. As a result, symbols might arrive slightly later than expected according to F.sub.symbol, i.e. with a positive time delay, e.g. time delay 18A or time delay 18B. Symbols may also arrive slightly earlier, i.e. with a negative time delay, e.g. time delay 18C. The phase error (8) may be defined as a collection (18) of time delay errors of the analogue communication signal (10), e.g. 18A, 18B and 18C.

[0060] Returning to FIG. 1, the circuitry (100) comprises a phase error calculation circuitry configured to determine (107) the phase error (8) based on the recovered digital signal (30). Contrary to explicit clock recovery or, in other words, active clock compensation techniques, the phase error (8) is not compensated for directly by adjusting the sampling moment. In such schemes, no blind sampling is applied, yet sampling is actively attempted to be performed in the middle of the corresponding eye diagram based on delay information. However, those approaches suffer from a costly loop delay by explicitly feeding back clock information. These delays are intolerable for applications operating at increasingly high speeds such as PONs. After the blind sampling is performed by the ADC, the digital signal (20) can take any of the quantisation level values (31) provided by the ADC, as shown in FIG. 3. Outputted by the fractionally-spaced equaliser, the recovered digital signal (30) can also take any of the quantisation level values (31) provided by the same ADC, see FIG. 5, or may comprise more quantization level values if provided by the circuitry (100). However, the analogue communication signal represents NRZ signals in this example, thus only with extreme values 0 and 1. The recovered digital signal (30) has a higher resolution than the information contained within the analogue communication signal (10), e.g. a resolution of 1 bit for NRZ signals. This surplus of resolution can be exploited to determine (107) the phase error (8), because the value of the recovered digital signal (30) inherently carries information about the phase error (8). For example, phase error detection may be done using a baud-rate phase detector, e.g. a Mueller-Muller phase detector. Further, note that timing variations of the recovered digital signal (30) comprise an accumulation of a frequency error or frequency offset, resulting in a deviation from F.sub.symbol, and a phase error (8), which may be different for each symbol within the recovered digital signal (30). Note that the frequency error may also be regarded as part of the phase error when the phase error is described with respect to an ideal clock at the symbol frequency F.sub.symbol.

[0061] Further, the circuitry (100) comprises a sub-circuitry to obtain (106) intermediate filter coefficients (40) for the FIR filtering (104). According to example embodiments, the obtaining (106) of the intermediate filter coefficients (40) is done by reusing intermediate filter coefficients from a past iteration. This is particularly advantageous when the channel is expected to change relatively slowly, e.g. in downstream mode at the user units and in upstream within a data burst at the terminal. During a burst, the channel will generally not vary greatly as bursts occur during relatively short periods of time. According to further example embodiments, the obtaining (106) comprises pre-loading of previously calculated intermediate filter coefficients from another CDR process, e.g. applied on the same or a similar PON. This may be useful for initialization of the intermediate filter coefficients (40), e.g. when the CDR circuitry is initiated. Any combination of the abovementioned approaches for obtaining (106) of the intermediate filter coefficients (40) is also possible.

[0062] The circuitry (100) further comprises an interpolator, configured to interpolate (108) the intermediate filter coefficients (40) based on the phase error (8), resulting in interpolated filter coefficients (50). Providing the phase error (8) to the interpolator introduces feedback in the circuitry (100). As such, a phase error loop (5) is passed through during CDR, as indicated in FIG. 1. The phase error loop (5) comprises the feeding back of the phase error (8), after calculation thereof based on the recovered digital signal (30), to the interpolator, wherein interpolated filter coefficients (50) are used to filter (104) the up-sampled digital signal resulting in the recovered digital signal (30).

[0063] Referring to FIG. 6, the intermediate filter coefficients (40) may characterize an underlying filter impulse response (60). Each intermediate filter coefficient is assigned an index number or, in other words, a coefficient index, e.g. starting from 0 as illustrated in FIG. 6.

[0064] Referring to FIG. 7, the interpolating (108) may comprise shifting (111) of the underlying filter impulse response (60) in the time domain based on the phase error (8) by a certain delay or shift (80). In FIG. 7, the intermediate filter coefficients (40) are represented by filled diamond shapes. The interpolated filter coefficients (50) are represented by circle shapes. By interpolating (108), intermediate values on the underlying filter impulse response (60) are found. Taking these intermediate values as the new filter coefficients shifts the underlying filter impulse response (60) by a shift (80) to a new underlying filter impulse response (61), as illustrated in FIG. 7. This is done by assigning the coefficient indices to the interpolated filter coefficients (50). According to example embodiments, the interpolating (108) comprises shifting (111) of the underlying filter impulse response (60) by the phase error (8), i.e. the shift (80) equals the phase error (8). The shift (80) can be either positive or negative to compensate for a positive or negative phase error (8) respectively. Since the impulse response is shifted, extrapolation may be required of the first or last filter coefficient. For example, in FIG. 7, the first filter coefficient is found by extrapolation.

[0065] Referring to FIG. 8, alternatively or additionally, the method (100) may further comprise shifting (112) the intermediate filter coefficients (40) when the phase error (8) in absolute value is at least half of an equivalent time (70) between the intermediate filter coefficients (40). The interpolated filter coefficients (50) are again represented by circle shapes. FIG. 6 shows the equivalent time (70) as a distance, expressed in a time unit, between subsequent intermediate filter coefficients (40), i.e. between coefficient indices of the intermediate filter coefficients. In the circuitry (100), the filtering (104) is applied to the by the factor L up-sampled digital signal. The spacing between incoming samples, which in this case is the equivalent time, may be T.sub.symbol/M, wherein T.sub.symbol is 1/F.sub.symbol and M is the down-sampling factor. In FIG. 8, extrapolation is applied for calculating the interpolated filter coefficient having an index of 0.

[0066] Thus, to compensate for the phase error (8), the method may comprise a combination of shifting 112 the underlying filter impulse response and subsequently shifting 111 the underlying filter impulse response (60) to compensate for the phase error (8) remaining after the shifting 112. According to example embodiments, the shift 112 is equal to the equivalent time (70). The remaining phase error then comprises the phase error minus the equivalent time. By choosing half of the equivalent time in absolute value as threshold value for the shifting 112, the amount of interpolating performed by the absolute value of the shifting 111 is minimized to as far as half of an equivalent time, as such preserving as much information comprised within the filter coefficients as possible. Alternatively, the shift (112) can be equal to K times the equivalent time (70) when the phase error (8) in absolute value is at least (K minus a half) times the equivalent time (70), as illustrated in FIG. 8. In this case, the amount of interpolating performed by the shifting 111 is also minimized to as far as half of an equivalent time.

[0067] Returning to FIG. 1, the interpolator is configured to update (109) the filter coefficients of the FIR filter with the interpolated filter coefficients (50) to compensate for the phase error (8).

[0068] In FIG. 9, another example of a circuitry (100) according to the invention is shown. This example embodiment comprises the same components that were already shown in the example embodiment of FIG. 1. The same reference numerals were used to indicate the same parts of the circuitry (100) and steps of the corresponding method (100). Further, the example embodiment of FIG. 9 comprises features that are additional to those presented in the example embodiment of FIG. 1.

[0069] With reference to FIG. 9, the obtaining (106) of the intermediate filter coefficients (40) comprises calculating (110) the intermediate filter coefficients (40) according to an adaptive filter algorithm based on the input, i.e. digital signal (20), and the output, i.e. recovered digital signal (30), of the fractionally-spaced equalisation. Thereby, an adaptive filtering loop (6) is added to the method, additional to the phase error loop (5), not shown again in FIG. 9. The adaptive filtering loop (6) comprises taking the digital signal (20) and the recovered digital signal (30) to calculate intermediate filter coefficients (40) that are interpolated and then used for the filtering (104) obtaining the recovered digital signal (30). Optionally, previously calculated intermediate filter coefficients (40) may be re-used, to only recalculate the intermediate filter coefficients (40) according to the adaptive filter algorithm after several iterations, resulting in a lower power consumption and higher performance. Alternatively, the intermediate filter coefficients may be recalculated continuously at a beginning stage of a CDR process, e.g. at the beginning of the downstream mode or at the beginning of a burst, to adapt to the PON channel. After the beginning stage, the filter coefficients may sufficiently match the channel and recalculation of the intermediate filter coefficients (40) may only be required every several iterations. Skipping the update of the filter coefficients during certain iterations or periods becomes possible because the interpolation is performed on filter coefficients instead of data, as filter coefficients change much less over time than data. Further, a step of passing the phase error (8) to the adaptive filter (110), is additionally required when performing the adaptive filtering, the reason being as follows. The adaptive filter (110) uses the input (20) and output (30) to update the intermediate filter coefficients (40) that serve the purpose of removing ISI. However, the adaptive filtering is based on the interpolated filter coefficients (50) from a previous iteration, which are the previous intermediate filter coefficients (40) that have been subjected to the interpolating step (108) based on the phase error (8). In order to update the intermediate filter coefficients (40) correctly, an additional calculation step is thus necessary to compensate the interpolating, i.e. an inverse interpolation step. For that purpose, the adaptive filter (110) needs the phase error (8) for its correct operation.

[0070] Further, the FIR filter of the example embodiment shown in FIG. 9 is a polyphase FIR filter (90) with L phases to perform the fractionally-spaced equalisation including the up-sampling (103) and the down-sampling (104). An input-output relation between digital signal x(t) (20) and recovered digital signal y(t) (30) may be described as follows, wherein f(x) represents the FIR filtering (104):

[00003]$y\left(k\right)=\underset{r=-}{\overset{+}{.Math.}}f\left(\mathrm{kM}-\mathrm{rL}\right)*x\left(r\right)$

Applying polyphase factorisation or decomposition by L results in the following filter banks:

[00004]$\begin{array}{c}{y}_0\left(k\right)=\underset{r=-}{\overset{+}{.Math.}}f\left(L\left(\mathrm{kM}-r\right)\right)*x\left(r\right)=\underset{r=-}{\overset{+}{.Math.}}{f}_0\left(\mathrm{kM}-r\right)*x\left(r\right)\\ y_1\left(k\right)=\underset{r=-}{\overset{+}{.Math.}}f\left(L\left(\mathrm{kM}-r\right)+M\right)*x\left(r\right)=\underset{r=-}{\overset{+}{.Math.}}{f}_M\left(\mathrm{kM}-r\right)*x\left(r\right)\\ .Math.\\ y_{L-1}\left(k\right)=\underset{r=-}{\overset{+}{.Math.}}f\left(L\left(\mathrm{kM}-r\right)+\left(L-1\right)*M\right)*x\left(r\right)=\underset{r=-}{\overset{+}{.Math.}}{f}_{\left(L-1\right)M}\left(\mathrm{kM}-r\right)*x\left(r\right)\end{array}$

The polyphase components f.sub.i comprise non-overlapping subsets of the filter coefficients, enabling parallelisation of the L filter phases, whenever M and L do not have any common factors, e.g. for L=4 and M=5.

[0071] Additionally, the recovered digital signal (30) is further equalised according to an additional equalisation scheme (113), e.g. a feed-forward equaliser, FFE, a decision-feedback equaliser, DFE, a maximum likelihood sequence estimator, MLSE, or a combination of equalisation techniques, to further reduce ISI. The additional equaliser (113) may advantageously comprise a high number of filter coefficients to increase the removal of ISI. For example, a FFE may be applied with 32 coefficients in combination with a DFE with 2 coefficients.

[0072] The determining of the phase error (107) comprises applying a low-pass filtering operation (114) on the phase error (8) to ease further processing of the phase error (8). After iteratively performing the method (100) for a while, a steady-state may be reached, wherein a steady-state frequency error, i.e. a frequency offset (9), and a steady-state phase error are reached. Therefore, the low-pass filter of the circuitry (100) may also comprise integrator terms to enable removing the remaining steady-state frequency error (9) and the steady-state phase error.

[0073] Further, the circuitry (100) comprises a sub-circuitry, configured for calculating (115) a frequency correction (9) based on the phase error (8) and applying (116) the frequency correction (9) to the sampling rate F.sub.sample to compensate for frequency deviations from the symbol frequency F.sub.symbol. Such a frequency offset F.sub.offset (9) can, for example, be identified from the phase error (8) as a recurring delay in subsequent periods. When a frequency offset (9) is present, the ADC is sampling at a frequency F.sub.sample equal to (M/L)*F.sub.symbol+F.sub.offset. A frequency correction F.sub.correction can be derived and provided to the ADC by amending the sampling rate of F.sub.sample accordingly, e.g. to F.sub.sampleF.sub.correction. As such, when F correction equals F.sub.offset, the average sample frequency F.sub.sample becomes equal to (M/L)*F.sub.symbol with a corresponding period of (L/M)*T.sub.symbol.

[0074] Further, the digital signal (20) is demultiplexed (117) into N parallel digital signals, before the up-sampling (103), wherein subsequent steps may be performed in parallel. N may, for example, equal 128 or 192.

[0075] Still referring to FIG. 9, the circuitry (100) further comprises a buffer for buffering (118) the digital signal (20) through an elastic buffering scheme. In accordance with the buffering (118), the method (100) may further comprise shifting the digital signal (20) in the buffering scheme when the phase error (8) exceeds a sampling period associated with the sampling rate F.sub.sample,

[00005]$T_{\mathrm{symbol}}*\frac{L}{M},$

to further compensate for the phase error. When the demultiplexer (117) and the buffer (118) are used in combination with the adaptive filter (110) as illustrated in FIG. 9, the adaptive filtering loop (6) comprises taking the digital signal (20) after multiplexing and buffering, instead of the digital signal (20).

[0076] The three ways of compensating the phase error (8) may be combined. A first way comprises interpolating (108) the intermediate filter coefficients (40) based on the phase error (8), resulting in interpolated filter coefficients (50), and updating the filter coefficients of the FIR filter with the interpolated filter coefficients (50). A second way comprises shifting (112) the intermediate filter coefficients (40) when the phase error (8) in absolute value is at least half an equivalent time (70), e.g. an equivalent time, between the intermediate filter coefficients (40). A third way comprises shifting the digital signal (20) in the buffer when the phase error (8) exceeds a sampling period associated with the sampling rate F.sub.sample. For example, if L equals 3, M equals 5 and the phase error equals

[00006]$T_{\mathrm{symbol}}*\frac{9}{10},$

the digital signal may first be shifted by one sample in the buffering scheme, i.e. compensating for a phase error of

[00007]$T_{\mathrm{symbol}}*\frac{3}{5},$

resulting in a remaining phase error of

[00008]$T_{\mathrm{symbol}}*\frac{3}{10}.$

Next, the intermediate filter coefficients may be shifted by the equivalent time (70), i.e. compensating for a phase error of

[00009]$T_{\mathrm{symbol}}*\frac{1}{5},$

resulting in a remaining phase error of

[00010]$T_{\mathrm{symbol}}*\frac{1}{10}.$

Lastly, the remaining phase error may be compensated for by an appropriate interpolation of the intermediate filter coefficients, for example an interpolation using a factor

[00011]$T_{\mathrm{symbol}}*\frac{1}{10}.$

[0077] The abovementioned steps, and circuitry components corresponding therewith, of the example embodiment of FIG. 9 are independent from each other and may each be separately added to the CDR circuitry (100) of FIG. 1. Any combinations of these additional features are possible. This concerns the step of calculating (110) the intermediate filter coefficients (40) according to an adaptive filter algorithm (110), the filter being a polyphase filter (90), the step of applying (113) an additional equalisation scheme (113), the step of applying (114) a low-pass filtering operation, the step of applying (116) a frequency correction (9), the step of demultiplexing (117) and the step of buffering (118).

[0078] As used in this application, the term circuitry may refer to one or more or all of the following: [0079] (a) hardware-only circuit implementations such as implementations in only analogue and/or digital circuitry and [0080] (b) combinations of hardware circuits and software, such as (as applicable): [0081] (i) a combination of analogue and/or digital hardware circuit(s) with software/firmware and [0082] (ii) any portions of hardware processor(s) with software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions) and

[0083] (c) hardware circuit(s) and/or processor(s), such as microprocessor(s) or a portion of a microprocessor(s), that requires software (e.g. firmware) for operation, but the software may not be present when it is not needed for operation.

[0084] This definition of circuitry applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term circuitry also covers an implementation of merely a hardware circuit or processor (or multiple processors) or portion of a hardware circuit or processor and its (or their) accompanying software and/or firmware. The term circuitry also covers, for example and if applicable to the particular claim element, a baseband integrated circuit or processor integrated circuit for a mobile device or a similar integrated circuit in a server, a cellular network device, or other computing or network device.

[0085] Although the present invention has been illustrated by reference to specific embodiments, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied with various changes and modifications without departing from the scope thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the scope of the claims are therefore intended to be embraced therein.

[0086] It will furthermore be understood by the reader of this patent application that the words comprising or comprise do not exclude other elements or steps, that the words a or an do not exclude a plurality, and that a single element, such as a computer system, a processor, or another integrated unit may fulfil the functions of several means recited in the claims. Any reference signs in the claims shall not be construed as limiting the respective claims concerned. The terms first, second, third, a, b, c, and the like, when used in the description or in the claims are introduced to distinguish between similar elements or steps and are not necessarily describing a sequential or chronological order. Similarly, the terms top, bottom, over, under, and the like are introduced for descriptive purposes and not necessarily to denote relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the invention are capable of operating according to the present invention in other sequences, or in orientations different from the one(s) described or illustrated above.