Slew-rate enhanced energy efficient source follower circuit

Abstract

This invention pertains to a source follower circuit suitable for receiving and buffering an input voltage and providing the buffered input voltage to a sampling capacitor via a sampling switch. The source follower circuit employs a slew enhancement circuit which enables the source follower to have fast settling for both high-to-low and low-to-high transitions.

Claims

1. A source follower circuit suitable for receiving and buffering an input voltage (V.sub.in) and providing said buffered input voltage to a sampling capacitor via a sampling switch, the voltage stored on said sampling capacitor being V.sub.s, comprising: an output node at which an output V.sub.out of said source follower circuit is provided; a slew FET having its drain connected to said output node and its source connected to a fixed potential such that, when on, said FET accelerates the slew rate of V.sub.out for one of a high-to-low or low-to-high transition; a slew capacitor C.sub.slew connected between said output node and said slew FET's gate; and a SET switch connected between said slew FET's gate and a voltage V.sub.set; said source follower circuit arranged such that: when said SET switch is closed and said sampling switch is open, the voltage (V.sub.g) at said slew FET's gate is equal to V.sub.set and the slew FET is substantially turned off; and V.sub.out settles to a new value V.sub.out.sub._.sub.new which varies with V.sub.in; and when said SET switch opens and said sampling switch closes, V.sub.out transitions to the voltage (V.sub.s.sub._.sub.prev) previously stored on said sampling capacitor; and V.sub.g changes by a value V.sub.g which is proportional to (V.sub.s.sub._.sub.prevV.sub.out.sub._.sub.new); and if said slew FET is an NMOS FET and V.sub.g>0, said slew FET turns on and pulls V.sub.s down to V.sub.out.sub._.sub.new, and if said slew FET is a PMOS FET and V.sub.g<0, said slew FET turns on and pulls V.sub.s up to V.sub.out.sub._.sub.new.

2. The source follower circuit of claim 1, wherein said circuit further comprises an input FET having its gate connected to input voltage V.sub.in and its source connected to said output node V.sub.out.

3. The source follower circuit of claim 2, further comprising a bias FET connected in series with said input FET, said output node being at the junction of said input and bias FETs.

4. The source follower circuit of claim 3, wherein said input and bias FETs and said slew FET are NMOS FETs and the source of said bias FET is connected to said fixed potential, the fixed potential to which said slew FET and said bias FET are connected being a circuit common point.

5. The source follower circuit of claim 3, wherein said input and bias FETs and said slew FET are PMOS FETs and the source of said bias FET is connected to said fixed potential, the fixed potential to which said slew FET and said bias FET are connected being a circuit supply voltage V.sub.dd.

6. The source follower circuit of claim 3, wherein the gate of said bias FET is connected to a fixed bias voltage V.sub.bias.

7. The source follower circuit of claim 1, further comprising a gate capacitance C.sub.g between the gate of said slew FET and a second fixed potential, such that $V_g=\frac{C_s}{C_s+C_{\mathrm{eq}}}\frac{C_{\mathrm{slew}}}{C_{\mathrm{slew}}+C_g}\left(V_{s\_\mathrm{prev}}-V_{\mathrm{out}\_\mathrm{new}}\right),$ where $C_{\mathrm{eq}}=C_{p,\mathrm{out}}+\frac{C_{\mathrm{slew}}{C}_g}{C_{\mathrm{slew}}+C_g}$ and C.sub.p,out is the capacitance on said output node.

8. The source follower circuit of claim 7, wherein said second fixed potential is a circuit common point if said slew FET is an NMOS FET, and said second fixed potential is a circuit supply voltage V.sub.dd if said slew FET is a PMOS FET.

9. The source follower circuit of claim 7, wherein said gate capacitance C.sub.g is the gate-to-source capacitance of said slew FET.

10. The source follower circuit of claim 1, further comprising a V.sub.set generation circuit, said V.sub.set generation circuit comprising a diode-connected NMOS FET biased such that 0<V.sub.set<V.sub.t when said slew FET is an NMOS FET, or comprising a diode-connected PMOS FET biased such that (V.sub.ddV.sub.t)<V.sub.set<V.sub.dd when said slew FET is a PMOS FET, where V.sub.t is the FET turn-on threshold voltage and V.sub.dd is a circuit supply voltage.

11. A source follower circuit suitable for receiving and buffering an input voltage (V.sub.in) and providing said buffered input voltage to a sampling capacitor via a sampling switch, the voltage stored on said sampling capacitor being V.sub.s comprising: an input stage, comprising: an input NMOS FET connected to receive said input voltage (V.sub.in); and a bias NMOS FET connected in series with said input NMOS FET, the gate of said bias FET connected to a fixed bias voltage V.sub.bias; an output node at the junction of said input and bias NMOS FETs at which an output V.sub.out of said source follower circuit is provided; a slew NMOS FET having its drain connected to said output node and its source connected to a circuit common point such that, when on, said slew NMOS FET accelerates the slew rate of V.sub.out for a high-to-low transition; a slew capacitor C.sub.slew connected between said output node and said slew NMOS FET's gate; and a SET switch connected between said slew NMOS FET's gate and a voltage V.sub.set; said source follower circuit arranged such that: when said SET switch is closed and said sampling switch is open, the voltage (V.sub.g) at said slew NMOS FET's gate is equal to V.sub.set and the slew NMOS FET is substantially turned off; and V.sub.out settles to a new value V.sub.out.sub._.sub.new which varies with V.sub.in; and when said SET switch opens and said sampling switch closes, V.sub.out transitions to the voltage (V.sub.s.sub._.sub.prev) previously stored on said sampling capacitor; and V.sub.g changes by a value V.sub.g which is proportional to (V.sub.s.sub._.sub.prevV.sub.out.sub._.sub.new); and when V.sub.g>0, said slew NMOS FET turns on and pulls V.sub.s down to V.sub.out.sub._.sub.new.

12. The source follower circuit of claim 11, further comprising a V.sub.set generation circuit, said V.sub.set generation circuit comprising a diode-connected NMOS FET biased such that 0<V.sub.set<V.sub.t where V.sub.t is the NMOS FET turn-on threshold voltage.

13. A source follower circuit suitable for receiving and buffering an input voltage (V.sub.in) and providing said buffered input voltage to a sampling capacitor via a sampling switch, the voltage stored on said sampling capacitor being V.sub.s, comprising: an input stage, comprising: an input PMOS FET connected to receive said input voltage (V.sub.in); and a bias PMOS FET connected in series with said input PMOS FET, the gate of said bias FET connected to a fixed bias voltage V.sub.bias; an output node at the junction of said input and bias PMOS FETs at which an output V.sub.out of said source follower circuit is provided; a slew PMOS FET having its drain connected to said output node and its source connected to a circuit supply voltage V.sub.dd such that, when on, said slew PMOS FET accelerates the slew rate of V.sub.out for a low-to-high transition; a slew capacitor C.sub.slew connected between said output node and said slew PMOS FET's gate; and a SET switch connected between said slew PMOS FET's gate and a voltage V.sub.set; said source follower circuit arranged such that: when said SET switch is closed and said sampling switch is open, the voltage (V.sub.g) at said slew PMOS FET's gate is equal to V.sub.set and the slew PMOS FET is substantially turned off; and V.sub.out settles to a new value V.sub.out.sub._.sub.new which varies with V.sub.in; and when said SET switch opens and said sampling switch closes, V.sub.out transitions to the voltage (V.sub.s.sub._.sub.prev) previously stored on said sampling capacitor; and V.sub.g changes by a value V.sub.g which is proportional to (V.sub.s.sub._.sub.prevV.sub.out.sub._.sub.new), and when V.sub.g<0, said slew PMOS FET turns on and pulls V.sub.s up to V.sub.out.sub._.sub.new.

14. The source follower circuit of claim 13, further comprising a V.sub.set generation circuit, said V.sub.set generation circuit comprising a diode-connected PMOS FET biased such that (V.sub.ddV.sub.t)<V.sub.set<V.sub.dd, where V.sub.t is the PMOS FET turn-on threshold voltage and V.sub.dd is a circuit supply voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a schematic diagram of a known source follower circuit.

(2) FIG. 1B is a timing diagram which illustrates the operation of the source follower circuit in FIG. 1A.

(3) FIG. 2A is a schematic diagram of another known source follower circuit.

(4) FIG. 2B is a timing diagram which illustrates the operation of the source follower circuit in FIG. 2A.

(5) FIG. 3A is a schematic diagram of an NMOS embodiment of a source follower circuit in accordance with the present invention.

(6) FIG. 3B is a timing diagram which illustrates the operation of the source follower circuit in FIG. 3A.

(7) FIG. 4A is a schematic diagram of a PMOS embodiment of a source follower circuit in accordance with the present invention.

(8) FIG. 4B is a timing diagram which illustrates the operation of the source follower circuit in FIG. 4A.

(9) FIG. 5A is a schematic diagram of one possible embodiment of a V.sub.set generation circuit for use with an NMOS source follower circuit per the present invention.

(10) FIG. 5B is a schematic diagram of one possible embodiment of a V.sub.set generation circuit for use with a PMOS source follower circuit per the present invention.

(11) FIG. 6 is a table comparing the simulated power consumption for a source follower circuit in accordance with the present invention with those of prior art source follower circuits.

DETAILED DESCRIPTION OF THE INVENTION

(12) The present source follower circuit has a general applicability, but is particularly well-suited for receiving and buffering an input voltage and providing the buffered input voltage to a sampling capacitor via a sampling switch. One possible embodiment is shown in FIG. 3A. The source follower circuit preferably includes an NMOS input FET (M1) having its gate connected to input voltage V.sub.in, its drain connected to a supply voltage V.sub.dd, and its source connected to output node 100, and an NMOS bias FET (M2) having its gate connected to a bias voltage V.sub.bias, its drain connected to output node 100, and its source connected to a circuit common point. M1 and M2 are thus connected in series, with output node 100 being the junction of M1 and M2. The circuit is arranged to receive and buffer an input voltage V.sub.in, and provide the buffered voltage V.sub.out at an output node 100. In this exemplary embodiment, voltage V.sub.out is provided to a sampling capacitor C.sub.s via a sampling switch SAMPLE, with the voltage stored on the sampling capacitor being referred to herein as V.sub.s.

(13) Both NMOS and PMOS source follower circuits are described herein. The source follower circuit includes a slew enhancement circuit 102, which operates to enhance the slew rate of low-to-high transitions (for a PMOS source follower) or high-to-low transitions (for an NMOS source follower) of buffered voltage V.sub.out. Circuit 102 comprises a slew FET M.sub.slew-n having its drain connected to output node 100 and its source connected to a fixed potential (such as ground) such that, when on, the slew FET accelerates the slew rate of V.sub.out for a high-to-low transition. A slew capacitor C.sub.slew is connected between output node 100 and the gate of M.sub.slew-n, and a SET switch is connected between the gate of M.sub.slew-n and a voltage V.sub.set.

(14) A timing diagram illustrating the operation of the circuit shown in FIG. 3A is shown in FIG. 3B. Switches SAMPLE and SET are operated with corresponding control signals SAMPLE and SET, respectively. In this example, the switches are closed when their corresponding control signal goes high; it is understood that the switches might also be arranged to operate with control signals having the opposite polarity to those shown in FIG. 3B. Signals SAMPLE and SET both have the same period t. Signal SAMPLE is high for a sampling time t.sub.sample, which typically takes most of the period t. Signal SET is high while signal SAMPLE is low, i.e. the two signals are non-overlapping. It is also assumed that for every sampling period the input voltage V.sub.in transitions to the new value at the onset of the SET pulse. Let us first consider the circuit operation when switch SET is closed and switch SAMPLE is open. Under these conditions, the voltage V.sub.g at the gate of FET equal M.sub.slew-n is to V.sub.set. V.sub.set is selected to be slightly below V.sub.t, where V.sub.t is the FET turn-on threshold voltage, such that when V.sub.g=V.sub.set, M.sub.slew-g is substantially turned off. Meanwhile, the input voltage V.sub.in transitions to a new value V.sub.in.sub._.sub.new. Since switch SAMPLE is open and the source follower is not loaded by the sampling capacitor C.sub.s, the output voltage V.sub.out quickly settles to a new value V.sub.out.sub._.sub.new corresponding to V.sub.in,new while switch SET is still closed.

(15) Next, switch SET opens and switch SAMPLE closes. This connects node 100 to C.sub.s, forcing V.sub.out to jump from V.sub.out.sub._.sub.new to the voltage V.sub.s.sub._.sub.prev previously stored on C5. The slew capacitor C.sub.slew couples this voltage transition to the gate of FET M.sub.slew-n so that the voltage V.sub.g at the gate of M.sub.slew-n changes by a value V.sub.g which is proportional to (V.sub.s.sub._.sub.prevV.sub.out.sub._.sub.new). Specifically,

(16) $\begin{array}{cc}{V}_g=\frac{C_{\mathrm{slew}}}{C_{\mathrm{slew}}+C_g}\frac{C_s}{C_s+C_{\mathrm{eq}}}\left(V_{s\_\mathrm{prev}}+V_{\mathrm{out}\_\mathrm{new}}\right),& \left(4a\right)\end{array}$
where

(17) $\begin{array}{cc}{C}_{\mathrm{eq}}=C_{p,\mathrm{out}}+\frac{C_{\mathrm{slew}}{C}_g}{C_{\mathrm{slew}}+C_g}.& \left(4b\right).\end{array}$
Capacitor C.sub.g is optional. C.sub.g may be an actual capacitor connected between the gate of M.sub.slew-n and a fixed potential such as ground (as illustrated in FIG. 3A), or may be the gate-to-source capacitance of M.sub.slew-n. C.sub.p,out is the parasitic capacitance at V.sub.out (output node 100). Typically C.sub.eq<<C.sub.s and equation (4a) can be approximated by:

(18) $\begin{array}{cc}{V}_g\frac{C_{\mathrm{slew}}}{C_{\mathrm{slew}}+C_g}\left(V_{s\_\mathrm{prev}}+V_{\mathrm{out}\_\mathrm{new}}\right).& \left(5\right)\end{array}$
If V.sub.in has transitioned from high to low, then V.sub.s.sub._.sub.prev>V.sub.out.sub._.sub.new and V.sub.g>0. Consequently, M.sub.slew-n turns on and provides the current needed to pull the sampling capacitor C.sub.s from V.sub.s.sub._.sub.prev down to V.sub.out.sub._.sub.new. This serves to increase the slew rate and speed up the settling for a high-to-low transition of V.sub.out, as well as V.sub.s.

(19) On the other hand, if V.sub.in has transitioned from low to high, then V.sub.s.sub._.sub.prev<V.sub.out.sub._.sub.new and V.sub.g<0. In this case M.sub.slew-n remains off and plays no role. However, the gate-to-source voltage of the input FET M1 increases, it turns on harder and provides the current needed to pull the sampling capacitor C.sub.s from V.sub.s.sub._.sub.prev up to V.sub.out.sub._.sub.new. Thus, the slew-enhanced NMOS source follower circuit exhibits fast settling on both high-to-low and low-to-high transitions. This is to be contrasted with the conventional source follower which, for the same bias current, exhibits equally fast settling only in one direction.

(20) The circuit shown in FIG. 3A illustrates the application of slew enhancement to an NMOS source follower according to the present invention. It is also possible to apply slew enhancement to a PMOS source follower; one possible embodiment is shown in FIG. 4A, with a corresponding timing diagram shown in FIG. 4B. The source follower circuit preferably includes a PMOS input FET (M4) having its gate connected to input voltage V.sub.in, its drain connected to a circuit common point, and its source connected to output node 110, and a PMOS bias FET (M3) having its gate connected to a bias voltage V.sub.bias, its drain connected to output node 110, and its source connected to supply voltage V.sub.dd. M3 and M4 are thus connected in series, with output node 110 being the junction of M3 and M4. As before, voltage V.sub.out is provided to a sampling capacitor C.sub.s via a sampling switch SAMPLE, with the voltage stored on the sampling capacitor being referred to as V.sub.s. A slew enhancement circuit 112 may be realized as shown, with a slew FET M.sub.slew-p, switch SET and slew capacitor C.sub.slew, preferably coupled to an output node 110.

(21) Signals SAMPLE, SET and V.sub.in in FIG. 4B are defined identically as in FIG. 3B. Let us first consider the circuit operation when switch SET is closed and switch SAMPLE is open. Under these conditions, the voltage V.sub.g at the gate of FET M.sub.slew-p is equal to V.sub.set. V.sub.set is selected to be slightly above (V.sub.ddV.sub.t), where V.sub.t is the FET turn-on threshold voltage, such that when V.sub.g=V.sub.set, M.sub.slew-p is substantially turned off. Meanwhile, the input voltage V.sub.in transitions to a new value V.sub.in.sub._.sub.new. Since switch SAMPLE is open and the source follower is not loaded by the sampling capacitor C.sub.s, the output voltage V.sub.out quickly settles to a new value V.sub.out.sub._.sub.new corresponding to V.sub.in,new while switch SET is still closed.

(22) When switch SET opens and switch SAMPLE closes, output node 110 is connected to C.sub.s, such that V.sub.out transitions to the voltage V.sub.s.sub._.sub.prev previously stored on C.sub.s. The voltage V.sub.g at the gate of M.sub.slew-p, changes by a value V.sub.g which is given by equation (4a) or approximately by equation (5). If V.sub.in has transitioned from low to high, then V.sub.s.sub._.sub.prev<V.sub.out.sub._.sub.new and V.sub.g<0. Consequently, M.sub.slew-p turns on and provides the current needed to pull the sampling capacitor C.sub.s from V.sub.s.sub._.sub.prev up to V.sub.out.sub._.sub.new. This serves to increase the slew rate and speed up the settling for a low-to-high transition of V.sub.out, as well as V.sub.s. On the other hand, if V.sub.in has transitioned from high to low, then V.sub.s.sub._.sub.prev>V.sub.out.sub._.sub.new and V.sub.g>0. In this case M.sub.slew-p remains off and plays no role. However, the gate-to-source voltage of the input FET M4 increases, it turns on harder and provides the current needed to pull the sampling capacitor C.sub.s from V.sub.s.sub._.sub.prev down to V.sub.out.sub._.sub.new. Thus, the slew-enhanced PMOS source follower circuit exhibits fast settling on both high-to-low and low-to-high transitions.

(23) As noted above, V.sub.set is selected to be slightly below V.sub.t when the slew FET is NMOS, and selected to be slightly above (V.sub.ddV.sub.t) when the slew FET is PMOS. Possible embodiments of circuits capable of generating V.sub.set for NMOS and PMOS source follower circuits are shown in FIGS. 5A and 5B, respectively. In FIG. 5A, the generation circuit preferably comprises a diode-connected NMOS FET M5, driven with a bias current I.sub.bias. If I.sub.bias is small and M5's width-to-length (W/L) ratio is large, V.sub.set<V.sub.t. After the SET switch (preferably implemented with an NMOS FET) opens, clock feedthrough and switch charge injection may cause a small voltage error V, so that V.sub.g=V.sub.setV.

(24) In FIG. 5B, the generation circuit preferably comprises a diode-connected PMOS FET M6, driven with a bias current I.sub.bias. If I.sub.bias is small and M6's width-to-length (W/L) ratio is large, V.sub.set>(V.sub.ddV.sub.t), where V.sub.dd is the circuit supply voltage. After the SET switch (preferably implemented with a PMOS FET) opens, switch clock feedthrough and charge injection may cause a small voltage error +V, so that V.sub.g=V.sub.set+V.

(25) Preferred embodiments of the SET switches shown in FIGS. 3A and 4A are also shown in the V.sub.set generation circuits, with the SET switch in FIG. 5A implemented with an NMOS FET M7, and the SET switch in FIG. 5B implemented with an PMOS FET M8.

(26) Below are some additional notes on the operation of the slew-enhanced source follower.

(27) Capacitance C.sub.slew can be much smaller than C.sub.s. Typical values could be, for example, C.sub.slew=20 fF and C.sub.s=1 to 10 pF. As noted above, capacitor C.sub.g may be optional; if used, it provides attenuation to V.sub.g.

(28) V.sub.set+V.sub.g when V.sub.g<0 should not fall below V.sub.t for an NMOS embodiment of the present source follower circuit. Similarly, V.sub.setV.sub.g when V.sub.g>0 should not rise above V.sub.dd+V.sub.t for a PMOS embodiment. Capacitances C.sub.slew and C.sub.g can be ratioed to ensure that this is true for the largest signal swing. For example, assuming that V.sub.setV.sub.t for the NMOS implementation and V.sub.setV.sub.ddV.sub.t for the PMOS implementation, using equation (5) we can write:

(29) $\begin{array}{cc}.Math.V_g.Math.\frac{C_{\mathrm{slew}}}{C_{\mathrm{slew}}+C_g}\left(V_{s\_\max }-V_{s\_\min }\right)2V_t,& \left(6\right)\end{array}$
where V.sub.s,min and V.sub.s,max are respectively the minimum and maximum sampled voltages on capacitor C.sub.s. Solving for C.sub.g/C.sub.slew we obtain:

(30) $\begin{array}{cc}\frac{C_g}{C_{\mathrm{slew}}}\frac{V_{s,\max }-V_{s,\min }}{2V_t}-1.& \left(7\right)\end{array}$

(31) Referring to FIG. 3A, FETs M1 and M2 are preferably in close proximity to slew enhancement circuit 102, to minimize the parasitic capacitance C.sub.p,out at V.sub.out (output node 100). This is because as C.sub.p,out increases, C.sub.eq increases (equation (4b)) and V.sub.g decreases (equation (4a)), thus reducing the effectiveness of the slew enhancement. Similarly, for the PMOS embodiment in FIG. 4A, FETs M3 and M4 are preferably in close proximity to slew enhancement circuit 112.

(32) A source follower circuit as described herein provides numerous advantages in comparison to prior art circuits. While the conventional NMOS source follower of FIG. 1A has fast settling only on low-to-high transitions, the slew-enhanced NMOS source follower of FIG. 3A operated at a similar bias current achieves fast settling on both low-to-high and high-to-low transitions. If the source follower of FIG. 1A is to have similarly fast high-to-low settling then its bias current needs to be increased significantly to provide the needed slew current but it will then be much less energy efficient than the slew-enhanced source follower. The same conclusions are valid if a conventional PMOS source follower is compared with the slew-enhanced source follower of FIG. 4A. When compared to the source follower with precharge of FIG. 2A, the slew-enhanced source follower circuit shows better energy efficiency since the charge on the sampling capacitor is not reset every sampling period. In fact, dynamic current is drawn from the supply only when needed and as much as needed for the sampling capacitor to settle to the new voltage. Consequently, the slew-enhanced source follower operates with a lower average dynamic current than the source follower with precharge of FIG. 2A. This leads to reduced power dissipation, as well as less substrate, ground or supply noise. The power savings provided by the present source follower circuit can be significant, particularly when used with, for example, multiple parallel circuits (for example, pixel or column source followers in image sensors), or when driving relatively large capacitive loads (for example, on-chip or output drivers). The improvement in energy efficiency will be discussed in more detail next.

(33) FIG. 6 is a table comparing simulated typical power consumption values for the present slew-enhanced source follower circuit (rightmost column) and the source follower circuits depicted in prior art FIGS. 1A (leftmost column) and 2A (center column). Though bias current is slightly higher for the present circuit in comparison with the circuit of FIG. 2A, the values for average V.sub.dd current and, consequently, average power, are considerably lower for the present circuit. The last row shows that the total power savings are significant when each of the three circuits is used in a 40964096 pixel array. The following assumptions were made when creating FIG. 6: Spectre simulation over 1000 sampling periods; the input V.sub.in for each sample is random and uniformly distributed over the range from 0 to 2.0 V; the supply voltage V.sub.dd=3.3 V; the sampling capacitor C.sub.s=1 pF; the sampling time t.sub.sample=11 s and the sampling period t=11.5 s; a PMOS source follower is used. when reporting the average power in a 40964096 array, it is assumed that the source follower is powered up for the sampling period t=11.5 is and is powered down for the rest of the frame time of 1 ms.

(34) The present source follower circuit can be used in numerous applications. In addition to those referenced above, examples include in-pixel source follower buffer circuits (for global shutter pixels, for example), source follower signal buffering (on-chip or off-chip load), and reference voltage buffering.

(35) While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.