Semiconductor light emitting diode chip with current extension layer and graphical current extension layers

Abstract

A semiconductor light emitting diode chip relates to the field of production technologies of a light emitting diode. In the present invention, corresponding graphical current extension layers are respectively disposed below an N pad and a P pad, and in all light emitting compound areas, there is electronic compound light emitting. Compared with the prior art, an area of a light emitting compound area is increased, which can effectively improve current distribution and light emitting brightness of a chip. In addition, graphical current extension can effectively increase an adhesion of a pad on a surface and improve the reliability of a chip.

Claims

1. A light emitting diode chip, comprising an N-type semiconductor layer, a light emitting compound layer, and a P-type semiconductor layer sequentially disposed on a rectangular substrate, and an N-type semiconductor layer that is exposed in the middle of the P-type semiconductor layer after being etched, wherein portions of the P-type semiconductor layer on two sides of the rectangular substrate are respectively provided with a P pad and an N pad; and a region of the P-type semiconductor layer outside of areas provided with the P pad and the N pad is provided with a current barrier layer, and the current barrier layer is provided with a current extension layer; the portions of the P-type semiconductor layer corresponding to the P pad and the N pad are respectively provided with graphical current extension layers, and the graphical current extension layers are respectively provided with electrical-insulating layers; and the back of the P pad and the back of the N pad are respectively provided with reflective layers; wherein, the current extension layer is provided with at least two graphical P extended electrodes, and each of the graphical P extended electrodes is electrically connected to the P pad; and wherein, the N pad is electrically connected to a graphical N extended electrode, the graphical N extended electrode is disposed on and is in contact with the exposed N-type semiconductor layer, and each of the graphical P extended electrodes is in contact with the current extension layer.

2. The light emitting diode chip according to claim 1, wherein each graphical current extension layer has a surface which is dotted circular holes, and the diameter of each circular hole is less than 10 um.

3. The light emitting diode chip according to claim 1, wherein a narrow side of the rectangular substrate is less than 300 um.

4. The light emitting diode chip according to claim 1, wherein each reflective layer is a medium layer, an aluminum layer, or a platinum layer.

5. The light emitting diode chip according to claim 1, wherein each electrical-insulating layer is a nitride of aluminum, an oxide of aluminum, an oxide of silicon, or a nitride layer of silicon.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic structural diagram of a sectional-layer shape of an N electrode;

(2) FIG. 2 is a schematic structural diagram of a sectional-layer shape of a P electrode; and

(3) FIG. 3 is a top view of graphical current extension layer (200a) and (200b).

DETAILED DESCRIPTION

(4) As shown in FIGS. 1, 2, and 3: An N-type semiconductor layer 002, a light emitting compound layer 003, and a P-type semiconductor layer 004, and an N-type semiconductor layer 002 that is exposed in the middle of the P-type semiconductor layer 004 after being etched are sequentially disposed on a rectangular substrate 001 having a narrow side L (which is as shown in FIG. 3) less than 300 um. P-type semiconductor layers 004 on two sides of the rectangular substrate 001 are respectively provided with a P pad 101a and an N pad 102a.

(5) P-type semiconductor layers 004 corresponding to the P pad 101a and the N pad 102a are respectively provided with graphical current extension layers 200a and 200b, and the graphical current extension layers 200a and 200b are separately provided with an electrical-insulating layer 201.

(6) The back of the P pad 101a and the back of the N pad 102a are separately provided with a reflector 211.

(7) The P pad 101a is separately electrically connected to two groups of graphical P extended electrodes 101b, and the N pad 102a is electrically connected to an N extended electrode 102b. The N extended electrode 102b is directly disposed on the exposed N-type semiconductor layer 002, and the P extended electrode 101b is disposed on a current extension layer 200.

(8) The P-type semiconductor layer 004 out of disposed areas of the P pad 101a and the N pad 102a is provided with a current barrier layer 300, the current barrier layer 300 is provided with the current extension layer 200, and the two groups of graphical P extended electrodes 101b are disposed on the current extension layer 200.

(9) Graphs of the graphical current extension layer 200b below the N pad 102a and the graphical current extension layer 200a below the P pad 101a may be made by using a photolithographic process.

(10) The reflector 211 may be a conventional medium layer (for example, SiO2/Ti3O5), aluminum layer, or platinum layer.

(11) The electrical-insulating layer 201 is a nitride of aluminum, an oxide of aluminum, an oxide of silicon, or a nitride layer of silicon.

(12) The current extension layers 200a and 200b are current extension layers having a net-dotted surface, and spacing between adjacent net holes is less than 10 um.

(13) It can be seen from FIG. 3 that, for example, circular graphical current extension layers 200a and 200b, which are current extension layers whose surface graph is a net-dotted circular hole, and the diameter of the circular hole is less than 10 um.