LOW-COST HIGH-EFFICIENCY SOLAR MODULE USING EPITAXIAL SI THIN-FILM ABSORBER AND DOUBLE-SIDED HETEROJUNCTION SOLAR CELL WITH INTEGRATED MODULE FABRICATION

Abstract

One embodiment of the present invention provides a double-sided heterojunction solar cell module. The solar cell includes a frontside glass cover, a backside glass cover situated below the frontside glass cover, and a number of solar cells situated between the frontside glass cover and the backside glass cover. Each solar cell includes a semiconductor multilayer structure situated below the frontside glass cover, including: a frontside electrode grid, a first layer of heavily doped amorphous Si (a-Si) situated below the frontside electrode, a layer of lightly doped crystalline-Si (c-Si) situated below the first layer of heavily doped a-Si, and a layer of heavily doped c-Si situated below the lightly doped c-Si layer. The solar cell also includes a second layer of heavily doped a-Si situated below the multilayer structure; and a backside electrode situated below the second layer of heavily doped a-Si.

Claims

1. A solar module, comprising: a first photovoltaic structure; a second photovoltaic structure positioned adjacent to the first photovoltaic structure, wherein each of the first and second photovoltaic structures comprises a first electrode positioned on a first surface and a second electrode positioned on an opposite surface; and wherein a solder tab of the first electrode of the first photovoltaic structure is in direct contact with a solder tab of the second electrode of the second photovoltaic structure, thereby enabling a serial connection between the first and second photovoltaic structures.

2. The solar module of claim 1, further comprising: a first cover; and a second cover.

3. The solar module of claim 2, further comprising: a first adhesive polymer layer positioned between the first cover and the photovoltaic structures; and a second adhesive polymer layer positioned between the second cover and the photovoltaic structures; wherein the first and second adhesive polymer layers, the first and second covers, and the first and second photovoltaic structures are laminated together.

4. The solar module of claim 3, wherein the first cover comprises glass, and wherein a refractive index of the first adhesive polymer layer matches a refractive index of the glass.

5. The solar module of claim 4, wherein the first adhesive polymer layer comprises one or more selected from a group consisting of: ethylene-vinyl acetate (EVA), acrylic, polycarbonate, polyolefin, and thermal plastic.

6. The solar module of claim 1, wherein each of the first and second photovoltaic structures comprises: a lightly doped crystalline-Si layer positioned between the first and second electrodes; a first heavily doped amorphous Si layer positioned between the first electrode and the lightly doped crystalline-Si layer; and a second heavily doped amorphous Si layer positioned between the second electrode and the lightly doped crystalline-Si layer, wherein the first and second heavily doped amorphous Si layers have opposite conductive doping types.

7. The solar module of claim 6, wherein each of the first and second photovoltaic structures further comprises at least one transparent conductive oxide layer positioned between an electrode and a heavily doped amorphous Si layer.

8. The solar module of claim 6, wherein the lightly doped crystalline-Si layer is formed using a chemical vapor deposition technique, wherein a thickness of the lightly doped crystalline-Si layer is between 5 m and 100 m, and wherein a doping concentration for the lightly doped c-Si layer is between 110.sup.16/cm.sup.3 and 110.sup.17/cm.sup.3.

9. The solar module of claim 6, wherein at least one heavily doped crystalline-Si layer is formed using a chemical vapor deposition technique, wherein a thickness of the at least one heavily doped crystalline-Si layer is between 10 nm and 50 nm, and wherein a doping concentration of the at least one heavily doped a-Si layer is between 110.sup.17/cm.sup.3 and 110.sup.20/cm.sup.3.

10. The solar module of claim 6, wherein each of the first and second photovoltaic structures further comprises a passivation layer on at least one surface of the lightly doped crystalline-Si layer, wherein a thickness of the passivation layer is between 1 nm and 10 nm, and wherein the passivation layer includes at least one of: undoped a-Si and SiO.sub.x.

11. The solar module of claim 1, wherein the first or second electrode comprises: Cu or tin-lead-silver coated Cu.

12. A solar panel, comprising: a first cover; a second cover; and a plurality of photovoltaic structures positioned between the first and second covers, wherein a respective photovoltaic structure comprises a first electrode positioned on a first surface and a second electrode positioned on an opposite surface of the photovoltaic structure; and wherein the plurality of photovoltaic structures are arranged in a way that a solder tab of the first electrode of a first photovoltaic structure is in direct contact with a solder tab of the second electrode of an adjacent photovoltaic structure, thereby enabling a serial connection between the first photovoltaic structure and the adjacent photovoltaic structure.

13. The solar panel of claim 12, further comprising: a first adhesive polymer layer positioned between the first cover and the plurality of photovoltaic structures; and a second adhesive polymer layer positioned between the second cover and the plurality of photovoltaic structures; wherein the first and second adhesive polymer layers, the first and second covers, and the plurality of photovoltaic structures are laminated together.

14. The solar panel of claim 13, wherein the first or second adhesive polymer layer comprises one or more selected from a group consisting of: ethylene-vinyl acetate (EVA), acrylic, polycarbonate, polyolefin, and thermal plastic.

15. The solar panel of claim 13, wherein the photovoltaic structure comprises: a lightly doped crystalline-Si layer positioned between the first and second electrodes; a first heavily doped amorphous Si layer positioned between the first electrode and the lightly doped crystalline-Si layer; and a second heavily doped amorphous Si layer positioned between the second electrode and the lightly doped crystalline-Si layer, wherein the first and second heavily doped amorphous Si layers have opposite conductive doping types.

16. The solar panel of claim 15, wherein the photovoltaic structure further comprises at least one transparent conductive oxide layer positioned between an electrode and a heavily doped amorphous Si layer.

17. The solar panel of claim 15, wherein the lightly doped crystalline-Si layer is formed using a chemical vapor deposition technique, wherein a thickness of the lightly doped crystalline-Si layer is between 5 m and 100 m, and wherein a doping concentration for the lightly doped c-Si layer is between 110.sup.16/cm.sup.3 and 110.sup.17/cm.sup.3.

18. The solar panel of claim 15, wherein at least one heavily doped crystalline-Si layer is formed using a chemical vapor deposition technique, wherein a thickness of the at least one heavily doped crystalline-Si layer is between 10 nm and 50 nm, and wherein a doping concentration of the at least one heavily doped a-Si layer is between 110.sup.17/cm.sup.3 and 110.sup.20/cm.sup.3.

19. The solar panel of claim 15, wherein the photovoltaic structure further comprises a passivation layer on at least one surface of the lightly doped crystalline-Si layer, wherein a thickness of the passivation layer is between 1 nm and 10 nm, and wherein the passivation layer includes at least one of: undoped a-Si and SiO.sub.x.

20. The solar panel of claim 12, wherein the first or second electrode comprises: Cu or tin-lead-silver coated Cu.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0028] FIG. 1 presents a diagram illustrating an exemplary SHJ solar cell (prior art).

[0029] FIG. 2 presents a diagram illustrating the process of fabricating a heterojunction multilayer structure in accordance with an embodiment of the present invention. 2A illustrates a MG-Si substrate. 2B illustrates a porous Si bi-layer structure is formed on the surface of MG-Si substrate. 2C illustrates a thin layer of heavily doped crystalline-Si thin film grown on top of the porous layer. 2D illustrates a layer of lightly doped crystalline-Si base film grown on top of the heavily doped crystalline-Si thin film. 2E illustrates that the surface of the base film is textured. 2F illustrates a passivation layer deposited on top of the base film. 2G illustrates a heavily doped a-Si emitter layer deposited on the passivation layer. 2H illustrates a layer of transparent-conducting-oxide (TCO) deposited on top of the a-Si emitter layer. 2I illustrates that the edge isolation process is performed to each individual solar cell. 2J illustrates a frontside electrode grid formed on top of the TCO layer.

[0030] FIG. 3 presents a diagram illustrating the process of transferring the multilayer structure to a glass cover in accordance with an embodiment of the present invention. 3A illustrates multiple heterojunction multilayer structures arranged in a modular configuration. 3B illustrates a layer of metal wires/mesh laid on top of each multilayer structure. 3C illustrates an adhesive polymer layer placed on top of all multilayer structures embedding the metal wires/mesh. 3D illustrates a frontside glass cover/superstrate placed on top of adhesive polymer layer. 3E illustrates the side view of a solar cell module after the lamination of a front cover glass. 3F illustrates a vacuum chuck applied to frontside glass cover and a vacuum chuck applied to the backside of each multilayer structure.

[0031] FIG. 4 presents a diagram illustrating the process of fabricating backside heterojunctions in accordance with an embodiment of the present invention. 4A shows the flipped solar module. 4B illustrates that the backside of the solar cell is textured. 4C illustrates a protective mask applied to the solar cell module. 4D illustrates an ultra-thin backside passivation layer deposited on the textured back surface of the solar cell. 4E illustrates a heavily doped a-Si layer deposited on top of backside passivation layer. 4F illustrates a TCO layer deposited on the heavily doped a-Si layer. 4G illustrates a backside electrode formed on top of the TCO layer. 4H illustrates the removal of the protective mask.

[0032] FIG. 5 presents a diagram illustrating a process of applying a backside protective cover to the solar cell module in accordance with an embodiment of the present invention. 5A illustrates a partially finished solar cell module. 5B illustrates a layer of metal wires/mesh pre-laid on the backside of each individual solar cell. 5C illustrates a layer of adhesive polymer placed on the backside of module. 5D illustrates a layer of protective backside cover placed on top of polymer layer. 5E illustrates the side view of a completed solar cell module.

[0033] FIG. 6 presents a diagram illustrating a process of fabricating a double-sided heterojunction single wafer solar cell in accordance with an embodiment of the present invention. 6A illustrates a layer of metal wires/mesh pre-laid on top of a single-wafer frontside heterojunction multilayer structure. 6B illustrates that the multilayer structure is attached to a layer of adhesive polymer. 6C illustrates vacuum chucks attached to the polymer layer and the MG-Si substrate. 6D illustrates the back side structures of the single wafer solar cell. 6E illustrates the partial removal of the front side polymer layer. 6F illustrates that the selected individual solar cells are arranged in a modular configuration. 6G illustrates the lamination of a frontside glass superstrate and a backside protective cover. 6H illustrates the framed solar module.

[0034] In the figures, like reference numerals refer to the same figure elements.

DETAILED DESCRIPTION

[0035] The following description is presented to enable any person skilled in the art to make and use the embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Overview

[0036] Embodiments of the present invention provide a double-sided heterojunction solar cell module. To fabricate a double-sided heterojunction solar cell, a multilayer heterojunction structure is first grown on top of an MG-Si substrate. The multilayer structure includes a thin layer of heavily doped c-Si acting as a back-surface-field (BSF) layer, a layer of lightly doped c-Si on top of the heavily doped c-Si layer as a base layer, a thin layer of intrinsic a-Si acting as a passivation layer, and a layer of heavily doped a-Si as an emitter. In addition, the multilayer structure includes a layer of transparent-conducting-oxide (TCO) and a frontside electrode grid. In order to be able to passivate the backside of the base film, some embodiments transfer the multilayer structure to a glass cover and subsequently remove the MG-Si substrate. Some embodiments implement a low-cost modular process in which a number of fabricated multilayer structures are laminated to a glass cover with the assistance of an adhesive polymer layer. The removed substrate can be recycled for future fabrication. After the removal of the MG-Si substrates, a thin layer of intrinsic a-Si and a thin layer of heavily doped a-Si are deposited on the backside of the base films to effectively passivate the backside of the base films. Subsequently, a layer of TCO and a backside electrode are deposited, and a backside glass cover is laminated to finish the module fabrication. To provide electrical connection to and from a solar cell, Cu wires are pre-laid between the glass covers and the electrodes, and the soldering of the Cu wires to the electrodes is performed concurrently with the lamination process.

Heterojunction Multilayer Structure

[0037] Before being transferred to a frontside glass cover, which acts as a supporting structure for subsequent fabrication processes, a heterojunction multilayer structure is first formed on a low-cost MG-Si substrate. FIG. 2 presents a diagram illustrating the process of fabricating a heterojunction multilayer structure in accordance with an embodiment of the present invention.

[0038] In operation 2A, an MG-Si substrate 200 is prepared. Because MG-Si is much cheaper than solar grade or semiconductor grade c-Si, solar cells based on MG-Si substrates have a significantly lower manufacture cost. The purity of MG-Si is usually between 98% and 99.99%. To ensure high efficiency of the subsequently fabricated solar cell, the starting MG-Si substrate ideally has a purity of 99.9% or better. Prior to any fabrication processes, a low-cost MG-Si wafer (with resistivity between 0.001 Ohm-cm and 0.1 Ohm-cm) undergoes an acidic chemical polish to remove any surface defects and to produce a smooth surface. In one embodiment, the acidic chemical polish process uses HF, HNO.sub.3, and other additives.

[0039] In operation 2B, a porous Si bi-layer structure is formed on the surface of MG-Si substrate 200. Porous Si bi-layer structure 202 includes a low-porosity Si layer 204 and a high-porosity Si layer 206. In some embodiments, layer 204 has a porosity level between 15% and 30% and a thickness between 0.8 m and 1.5 m. In some embodiments, layer 206 has a porosity level between 50% and 70% and a thickness between 0.1 m and 0.3 m. To construct bi-layer structure 202, some embodiments etch the surface of the MG-Si wafer using an electrochemical etching technique which applies HF solution and a current. The desired Si porosity level and porous layer thickness can be achieved by controlling the current density. The combination of a layer with high porosity and a layer with low porosity ensures not only an easier separation of the substrate (requires high porosity beneath the surface) but also a high-quality epitaxial film growth (requires low porosity at the surface). Some embodiments form multiple porous Si layers on the surface of MG-Si substrate 200.

[0040] Operation 2B also includes a process that can further purify the surface of the MG-Si wafer to ensure the quality of the subsequent epitaxial growth. In one embodiment, MG-Si substrate 200 is baked at a temperature between 1100 C. and 1250 C. in a chemical-vapor-deposition (CVD) chamber filled with hydrogen (H.sub.2) in order to remove native silicon-oxide in the substrate. Afterwards, at approximately the same temperature, hydrogen chloride (HCl) gas is introduced inside the CVD chamber to leach out any residual metal impurities from MG-Si substrate 200, thus further preventing the impurities from diffusing into the subsequently grown c-Si thin films. Due to the fact that metal impurities, such as iron, have a high diffusion coefficient at this temperature, the metal impurities tend to migrate to the surface of substrate 200, and react with the HCl gas to form volatile chloride compounds. The volatile chloride compounds can be effectively purged from the chamber using a purge gas, such as H.sub.2. Note that the metal-impurity leaching process can be carried out either in the CVD chamber, which is subsequently used for the growth of crystalline-Si thin films, or in another stand-alone furnace. The metal-impurity leaching process can take between 1 minute and 120 minutes. MG-Si substrate 200 can be either p-type doped or n-type doped. In one embodiment, MG-Si substrate is n-type doped. Also note that in addition to an MG-Si substrate, it is also possible to use a more expensive Floatzone, Caochralski, or solar grade wafer as a growth substrate.

[0041] In operation 2C, a thin layer of heavily doped (doping concentration greater than 110.sup.17/cm.sup.3) c-Si thin film 210 is epitaxially grown on the surface of low-porosity Si layer 204. Various methods can be used to epitaxially grow c-Si thin film 210 on MG-Si substrate 200. In one embodiment, c-Si thin film 210 is grown using a thermal CVD process. Various types of Si compounds, such as SiH.sub.4, SiH.sub.2Cl.sub.2, and SiHC.sub.3, can be used as a precursor in the CVD process to form c-Si thin film 210. In one embodiment, SiHC.sub.3 (TCS) is used due to its abundance and low cost. C-Si thin film 210 can be either p-type doped or n-type doped. In one embodiment, c-Si thin film 210 is n-type doped. The doping concentration of thin film 210 can be between 110.sup.17/cm.sup.3 and 110.sup.20/cm.sup.3, and the thickness of thin film 202 can be between 1 m and 10 m. The doping level should not exceed a maximum limit, which may cause misfit dislocations in the film. C-Si thin film 210 is heavily doped to act as back-surface field (BSF), impurity barrier, and contaminant getter layer for reducing electron-hole recombination at the surface of the subsequently grown base film.

[0042] In operation 2D, a layer of lightly doped (doping concentration less than 110.sup.17/cm.sup.3) c-Si base film 212 is epitaxially grown on top of thin film 210. The growth process of base film 212 can be similar to that used for thin film 210. Similarly, base film 212 can be either p-type doped or n-type doped. In one embodiment, base film 212 is lightly doped with an n-type dopant, such as phosphorus. The doping concentration of base film 212 can be between 110.sup.16/cm.sup.3 and 110.sup.17/cm.sup.3, and the thickness of base film 212 can be between 5 m and 100 m. After film deposition, in operation 2E, the surface of base film 212 is textured to maximize light absorption inside the solar cell, thus further enhancing efficiency. The surface texturing can be performed using various etching techniques including dry plasma etching and wet chemical etching. The etchants used in the dry plasma etching include, but are not limited to: SF.sub.6, F.sub.2, and NF.sub.3. The wet chemical etchant can be an alkaline solution. The shapes of the surface texture can be pyramids or inverted pyramids, which are randomly or regularly distributed on the surface of base film 212.

[0043] In operation 2F, a passivation layer 214 is deposited on top of base film 212. Passivation layer 214 can significantly reduce the density of surface minority-carrier recombination via hydrogenation passivation of surface defect states, as well as by the built-in heterojunction bandgap offset, hence resulting in higher solar cell efficiency. Passivation layer 214 can be formed using different materials such as intrinsic a-Si or silicon-oxide (SiO.sub.x). Techniques used for forming passivation layer 214 include, but are not limited to: PECVD, sputtering, and electron beam (e-beam) evaporation. The thickness of passivation layer 214 can be between 2 nm and 10 nm. Note that such thickness is thin enough to allow tunneling of majority carriers, thus ensuring low series resistance of the solar cell. In some embodiments, a mixture of SiH.sub.4 and H.sub.2 gases is injected into a PECVD chamber at a pressure of 250-750 mTorr, an RF power of 20-75 mW/cm.sup.2, and a temperature of 100-200 C. in order to form passivation layer 214 that includes intrinsic a-Si.

[0044] In operation 2G, a heavily doped a-Si layer is deposited on passivation layer 214 to form an emitter layer 216. Depending on the doping type of base film 212, emitter layer 216 can be either n-type doped or p-type doped. In one embodiment, emitter layer 216 is heavily doped with a p-type dopant. The doping concentration of emitter layer 216 can be between 110.sup.17/cm.sup.3 and 110.sup.20/cm.sup.3. The thickness of emitter layer 216 can be between 10 nm and 50 nm. Techniques used for depositing emitter layer 216 include PECVD. Some embodiments form emitter layer 216 by injecting a mixture of B.sub.2H.sub.6 (or PH.sub.3), SiH.sub.4 and H.sub.2 gases into a PECVD chamber operating at a pressure of 250-750 mTorr, an RF power of 20-75 mW/cm.sup.2, and a temperature of 125-250 C. The ultra-thin a-Si layer stack, which includes passivation (intrinsic a-Si) layer 214 and heavily doped a-Si layer 216, can improve the absorption efficiency of short wavelength incident light of the solar cell, thus leading to higher efficiency.

[0045] In operation 2H, a layer of transparent-conducting-oxide (TCO) is deposited on top of emitter layer 216 to form a conductive anti-reflection layer 218. Examples of TCO include, but are not limited to: indium-tin-oxide (ITO), tin-oxide (SnO.sub.x), aluminum doped zinc-oxide (ZnO:Al), or Ga doped zinc-oxide (ZnO:Ga). Techniques used for forming anti-reflection layer 218 include, but are not limited to: PECVD, sputtering, and e-beam evaporation.

[0046] In operation 2I, an edge isolation process is performed to each individual solar cell to ensure electrical insulation between emitter layer 216 and base film 212. The edge isolation can be done using at least one of the following techniques: chemical wet etching, plasma dry etching, and laser scribing.

[0047] In operation 2J, frontside electrode grid 220 is formed on top of anti-reflection layer 218. Frontside electrode grid 220 can be formed using various metal deposition techniques including, but not limited to: screen printing of Ag paste, aerosol printing of Ag ink, and e-beam evaporation. The formation of frontside electrode grid completes the fabrication of a multilayer structure with front heterojunction. It is important to ensure that an ohmic contact is formed between frontside electrode grid 220 and anti-reflection layer 218 by using a suitable work function. In some embodiments, a sorting process is performed after the completion of the heterojunction multilayer structure.

Layer Transfer

[0048] In order to passivate the backside of base film 212, some embodiments of the present invention remove the MG-Si substrate and transfer the previously completed heterojunction multilayer structure to a glass cover. FIG. 3 presents a diagram illustrating the process of transferring the multilayer structure to a glass cover in accordance with an embodiment of the present invention.

[0049] In operation 3A, multiple previously fabricated heterojunction multilayer structures, including structure 302, are arranged in a modular configuration 300. Various modular configurations can be applied. For example, module configuration 300 shown in FIG. 3A demonstrates a 6-cell configuration. Other configurations including different numbers of cells, such as 36, 72, and 96 cells, and different geometric configurations, such as a regular matrix formation or irregular formations, are also possible. Note that each individual structure can be hold in place by a vacuum chuck with frontside electrode grid 304 facing up. FIG. 3A demonstrates the top view of modular configuration 300.

[0050] In operation 3B, a layer of metal wires/mesh is laid on top of each multilayer structure to provide electrical connection to the frontside of the multilayer structure. For example, metal wires/mesh 306 is placed in such a way that the wires run vertically across frontside electrode grid 304. In one embodiment, metal wires 306 include tin-lead-silver coated Cu wires.

[0051] In operation 3C, an adhesive polymer layer 308 is placed on top of all multilayer structures embedding the metal wires/mesh. To ensure excellent light transmission, the refractive index of adhesive polymer layer 308 matches that of a subsequently applied frontside glass cover. Examples of index-matching polymer include, but are not limited to: ethylene-vinyl acetate (EVA), acrylic, polycarbonate, polyolefin, and thermal plastic.

[0052] In operation 3D, a frontside glass cover/superstrate 310 is placed on top of adhesive polymer layer 308, and heat and pressure are applied to cure polymer layer 308. As the result of the curing, the multilayer structures are laminated on polymer layer 308, and polymer layer 308 is laminated on frontside glass cover 310. In addition, during the lamination process, metal wires/mesh 306 is soldered to corresponding frontside electrode grid 304, thus forming corresponding bus bars. Note that the one-step lamination and soldering process is a cost-effective way to realize electrical connection and the frontside protection of the solar cell module. In some embodiments, the temperature for curing polymer layer 308 is between 150 C. and 180 C.

[0053] FIG. 3E illustrates the side view of a solar cell module after the lamination of a front cover glass in accordance with an embodiment of the present invention. Note that the sequence of operations for achieving the configuration shown in FIG. 3E can be different than the sequence shown in FIGS. 3A-3D. In some embodiments, polymer layer 308 and metal wires/mesh 306 are laid on the surface of frontside glass cover 310 sequentially, and the multilayer structures are flipped upside down to be placed on corresponding metal wires/mesh 306.

[0054] Once the frontside of multilayer structures 302 is protected, it is possible to perform layer transferring, during which MG-Si substrate 200 is removed. In operation 3F, a vacuum chuck 312 with uniform vacuum is applied to frontside glass cover 310 and a vacuum chuck 314 is applied to the backside of each multilayer structure in order to remove MG-Si substrate 200 via mechanical forces. Due to the existence of high porosity Si layer 206, which forms a line of weakness, MG-Si substrate 200 can be separated from the rest of the multilayer structure 302. Various techniques can be used to separate MG-Si substrate 200 from structure 302, including but not limited to: chemical wet etching, applying shear or piezoelectric forces, applying a temperature gradient, applying ultra/mega-sonic resonance force, applying tensile or compressive mechanical forces, and pumping a pressurized gas (such as H.sub.2) into the porous Si region. Note that the detachment of MG-Si substrate 200 can be separately performed for each individual multilayer structure, or in a batch for the whole module. Detached MG-Si substrate 200 can be subsequently recycled and reused as a substrate for a new epitaxial growth, thus significantly reducing the cost of the solar cell fabrication process. Some embodiments use various etching methods, such as chemical wet etching, plasma dry etching, and chemical mechanical polishing, to etch off MG-Si substrate 200. In these scenarios, the cost savings of recycling/reusing MG-Si substrate 200 are forfeited.

Backside Passivation

[0055] After the detachment/removal of MG-Si substrates, the backside of the c-Si base films becomes accessible for passivation. FIG. 4 presents a diagram illustrating the process of fabricating backside heterojunctions in accordance with an embodiment of the present invention.

[0056] In operation 4A, the solar cell module is flipped over and the residual porous Si layer is removed to expose the backside of epitaxial c-Si films including BSF layer 210. For better demonstration, FIG. 4A only shows the cross section of one solar cell. It is advantageous to remove the residual porous Si layer because its high-density defects sites can result in increased minority carrier recombination at the back surface of the solar cell, thus reducing cell efficiency. Various etching techniques, such as chemical wet etching, can be used to remove the residual porous Si layer.

[0057] In operation 4B, the backside of the solar cell is textured using either chemical wet etching or plasma dry etching techniques. The texturing can significantly improve the amount of light absorbed by c-Si films, including BSF layer 210 and base film 212.

[0058] Operation 4C is an optional operation, during which a protective mask 402 is applied to the solar cell module. Mask 402 covers the entire solar cell module, including the polymer/glass regions between solar cells, except for the backside of individual solar cells. Protective mask 402 can be formed by a Tyflon release paper which can subsequently be easily peeled off, or by a loading and unloading panel cartridge with cutouts.

[0059] In operation 4D, an ultra-thin backside passivation layer 404 is deposited. The material and techniques used to perform operation 4D are similar to those of operation 2F. For example, passivation layer 404 can include intrinsic a-Si or SiO.sub.x. The thickness of backside passivation layer 404 can be between 2 nm and 10 nm.

[0060] In operation 4E, a heavily doped a-Si layer 406 is deposited on top of backside passivation layer 404. The deposition process of a-Si layer 406 is similar to that of operation 2G. Depending on the doping type of base film 212, heavily doped a-Si layer 406 can be n-type doped or p-type doped. In one embodiment, heavily doped a-Si layer 406 is n-type doped. The formation of a heterojunction between the a-Si layers (layers 404 and 406) and base film 212 creates a potential barrier for minority carriers at the backside of base film 212, thus effectively decreasing minority carrier recombination at the back surface. Consequently, higher solar cell efficiency (greater than 19.5%) can be achieved. In some embodiments, operations 4D and 4E are skipped, resulting in a single-sided heterojunction solar cell, which may have lower cell efficiency. However, by skipping the deposition of the a-Si stack (layers 404 and 406), the solar cell module can avoid the high temperature and high pressure PECVD process, thus preserving the integrity of frontside adhesive polymer layer 308.

[0061] In operation 4F, a TCO layer 408 is deposited to make both an anti-reflection layer and a conductive layer. The process of forming TCO layer 408 is similar to operation 2H.

[0062] In operation 4G, a backside electrode 410 is formed on top of TCO layer 408. In some embodiments, backside electrode 410 can be in a grid pattern instead of covering the whole backside. Techniques for depositing backside electrode 410 can include Ag or Al screen printing and metal evaporation.

[0063] In operation 4H, protective mask 402 is removed. Note that in cases where no protective mask is applied, an edge isolation operation, such as laser isolation, will be performed after operation 4F to eliminate possible short circuits among the cells.

Backside Glass Cover

[0064] After the fabrication of the backside heterojunction, a protective backside glass/polymer cover is applied to the backside of the solar cell module. The process of applying the backside glass/polymer cover is similar to that of the frontside glass cover. FIG. 5 presents a diagram illustrating a process of applying a backside protective cover to the solar cell module in accordance with an embodiment of the present invention.

[0065] In operation 5A, a partially finished solar cell module 500 is placed with the backside of solar cells, such as solar cell 502 and solar cell 504, facing upward, whereas glass cover/superstrate 506 is facing downward.

[0066] In operation 5B, a layer of metal wires/mesh is pre-laid on the backside of each individual solar cell. For example, metal wire/mesh 508 is placed on the backside of solar cell 502, thus providing electrical access to the backside electrode of cell 502. In some embodiments, metal wires 508 include tin-lead-silver coated Cu wires. Note that all backside metal wires/meshes are placed in such a way that they are aligned to corresponding frontside metal wires/meshes to form a series of interconnected solar cells as required in a solar cell module arrangement. For example, metal mesh 508 is placed so that its solder tab 510 is directly contacting the solder tab of the frontside metal mesh of solar cell 504, thus forming a series connection between solar cell 502 and solar cell 504.

[0067] In operation 5C, a layer of adhesive polymer 512 is placed on the backside of module 500. Ideally, adhesive polymer layer 512 has a low refractive index and an excellent light transmission coefficient. Materials that can be used to form adhesive polymer layer 512 include, but are not limited to: ethylene-vinyl acetate (EVA), acrylic, polycarbonate, polyolefin, and thermal plastic.

[0068] In operation 5D, a layer of protective backside cover 514 is placed on top of polymer layer 512, and heat and pressure are applied to concurrently cure polymer layer 512 and solder backside metal wires/mesh to the backside electrodes. Backside cover 514 can be formed using glass or a polymer, such as Tedlar. The curing of polymer layer 512 results in the lamination of backside cover 514 to solar cell module 500. In addition, the lamination process involves adhesion and vacuum sealing between frontside polymer layer 308 and backside polymer layer 512. As a result, solar cell module 500 is sealed between the frontside glass superstrate and the backside cover, thus preventing damages caused by exposure to environmental factors. Subsequently, a standard framing/trimming process and formation of a junction box are performed to finish the manufacture of solar cell module 500. In the end, the completed solar cell module is tested. FIG. 5E illustrates the side view of a completed solar cell module in accordance with an embodiment of the present invention.

Single Wafer Process

[0069] In some embodiments, instead of using a modular process to fabricate the backside heterojunctions, a single wafer process is applied to fabricate individual solar cells before putting them into a module. FIG. 6 presents a diagram illustrating a process of fabricating a double-sided heterojunction single wafer solar cell in accordance with an embodiment of the present invention.

[0070] In operation 6A, a layer of metal wires/mesh 606 is pre-laid on top of a previously fabricated (after the completion of operation 2J) single-wafer frontside heterojunction multilayer structure 602, which is placed with its frontside electrode grid 604 facing upward.

[0071] In operation 6B, multilayer structure 602 is attached to a layer of adhesive polymer 608 via a lamination process. During the lamination process, metal wires/mesh 606 is soldered to frontside electrode 604.

[0072] In operation 6C, vacuum chucks are attached to polymer layer 608 and MG-Si substrate 612 to separate the MG-Si substrate from the epitaxial c-Si films. Techniques that can be used to separate MG-Si substrate 612 are similar to the ones used in operation 3F.

[0073] In operation 6D, the single wafer solar cell undergoes backside processing similar to the ones in operations 4A-4H to accomplish backside texturing, depositing a passivation layer 614, depositing a heavily doped a-Si layer 616, depositing a TCO layer 618, and depositing a backside electrode grid 620.

[0074] In operation 6E, the frontside polymer layer 608 is partially removed to expose the frontside metal wires/mesh 606, thus enabling cell level testing and sorting.

[0075] In operation 6F, the selected individual solar cells are arranged in a modular configuration before applying a frontside polymer layer 622, a backside metal wires/mesh 624, and a backside polymer layer 626. Note that backside metal wires/mesh 624 is aligned to corresponding frontside metal wires/mesh in order to form a series of interconnected solar cells.

[0076] In operation 6G, a frontside glass superstrate 628 and a backside protective cover 630, which can be made of glass or Tedlar, are laminated to the solar cell module via curing of polymer layers 622 and 626. Similarly, backside metal wires/mesh 624 is soldered to backside electrode grid 620 during the lamination process.

[0077] In operation 6H, a standard framing/trimming process and the formation of a junction box are performed to finish the manufacture of solar cell module 600.

[0078] The foregoing descriptions of various embodiments have been presented only for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention.