Surface-Mountable Semiconductor Component and Method for Producing Same

Abstract

A surface-mountable semiconductor component and a method for producing the same are disclosed. In an embodiment the component includes an optoelectronic semiconductor chip, first and second contact elements and a molded body, wherein the chip includes a semiconductor body having a semiconductor layer sequence with an active region provided for producing and/or receiving electromagnetic radiation and arranged between a first semiconductor layer and a second semiconductor layer, wherein the first contact elements are electrically conductively connected to the first semiconductor layer and the second contact elements are electrically conductively connected to the second semiconductor layer, wherein the molded body at least partially encloses the optoelectronic semiconductor chip, wherein the semiconductor component includes a mounting face formed by a surface of the molded body, and wherein the first and second contact elements protrudes through the molded body in a region of the mounting face.

Claims

1-15. (canceled)

16. A surface-mountable semiconductor component comprising: an optoelectronic semiconductor chip; a plurality of first contact elements; a plurality of second contact elements; and a molded body, wherein the optoelectronic semiconductor chip comprises a semiconductor body comprising a semiconductor layer sequence with an active region provided for producing and/or receiving electromagnetic radiation and arranged between a first semiconductor layer and a second semiconductor layer, wherein the plurality of first contact elements is electrically conductively connected to the first semiconductor layer and the plurality of second contact elements is electrically conductively connected to the second semiconductor layer, wherein the molded body at least partially encloses the optoelectronic semiconductor chip, wherein the semiconductor component comprises a mounting face formed by a surface of the molded body at least in places, and wherein the plurality of first and the plurality of second contact elements protrude through the molded body in a region of the mounting face.

17. The semiconductor component according to claim 16, wherein the plurality of first contact elements and the plurality of second contact elements overlap with the semiconductor body in a plan view on the semiconductor component.

18. The semiconductor component according to claim 16, wherein the optoelectronic semiconductor chip comprises a carrier body with an electrically insulating design arranged on a side of the semiconductor body facing away from the mounting face.

19. The semiconductor component according to claim 16, wherein the molded body is formed at least in sections to the optoelectronic semiconductor chip and to the plurality of first and second contact elements.

20. The semiconductor component according to claim 16, wherein the molded body encloses the optoelectronic semiconductor chip from all sides.

21. The semiconductor component according to claim 16, wherein each contact element comprises a connection base and a cap element protruding vertically from the mounting face.

22. The semiconductor component according to claim 16, wherein the molded body contains silicone or epoxy.

23. The semiconductor component according to claim 16, wherein the molded body has a height of between 10 m and 150 m in the region of the mounting face.

24. The semiconductor component according to claim 16, wherein the molded body is one piece.

25. The semiconductor component according to claim 16, wherein a varistor paste is applied between the plurality of first contact elements and the plurality of second contact elements, the paste configured to protect the optoelectronic semiconductor chip from an electrostatic discharge.

26. The semiconductor component according to claim 16, wherein the plurality of first contact elements is electrically conductively connected to the first semiconductor layer via a first connection layer and the plurality of second contact elements is electrically conductively connected to the second semiconductor layer via a second connection layer and the first connection layer and the second connection layer overlap in a plan view of the semiconductor component.

27. The semiconductor component according to claim 16, wherein the molded body contains a luminescence conversion material.

28. The semiconductor component according to claim 16, wherein a luminescence conversion material layer is arranged at least in sections between the molded body and the optoelectronic semiconductor chip.

29. A method for producing a plurality of surface-mountable optoelectronic semiconductor components, the method comprising: providing an auxiliary carrier; providing a multitude of optoelectronic semiconductor chips, wherein each of the semiconductor chips comprises a semiconductor body comprising an active region provided for producing and/or generating electromagnetic radiation and arranged between a first semiconductor layer and a second semiconductor layer, fastening the multitude of semiconductor chips on the auxiliary carrier, wherein the semiconductor chips are spaced from one another in a lateral direction and interspaces free of a solid material are provided between each of the semiconductor chips and the auxiliary carrier; forming a molded body compound enclosing the semiconductor chips; removing the auxiliary carrier; and singulating the molded body compound into the plurality of optoelectronic semiconductor components, wherein each semiconductor component comprises at least a semiconductor chip, a plurality of first contact elements, a plurality of second contact elements and part of the molded body compound as a molded body.

30. The method according to claim 29, wherein each of the semiconductor chips comprises a plurality of spacer elements by means of which the interspaces are formed and which form at least parts of the first and second contact elements of the finished components.

31. A surface-mountable semiconductor component comprising: an optoelectronic semiconductor chip; a plurality of first contact elements; a plurality of second contact elements; and a molded body, wherein the optoelectronic semiconductor chip comprises a semiconductor body comprising a semiconductor layer sequence with an active region provided for producing and/or receiving electromagnetic radiation and arranged between a first semiconductor layer and a second semiconductor layer, wherein the plurality of first contact elements is electrically conductively connected to the first semiconductor layer and the plurality of second contact elements is electrically conductively connected to the second semiconductor layer, wherein the molded body at least partially encloses the optoelectronic semiconductor chip, wherein the semiconductor component comprises a mounting face formed by a surface of the molded body at least in places, wherein the plurality of first and the plurality of second contact elements protrude through the molded body in a region of the mounting face, and wherein each contact element comprises a connection base and a cap element which protrudes vertically from the mounting face.

32. The semiconductor component according to claim 31, wherein a varistor paste is located between the plurality of first contact elements and the plurality of second contact elements, the paste configured to protect the optoelectronic semiconductor chip from an electrostatic discharge.

33. A surface-mountable semiconductor component comprising: an optoelectronic semiconductor chip; a plurality of first contact elements; a plurality of second contact elements; and a molded body, wherein the optoelectronic semiconductor chip comprises a semiconductor body comprising a semiconductor layer sequence with an active region provided for producing and/or receiving electromagnetic radiation and arranged between a first semiconductor layer and a second semiconductor layer, wherein the plurality of first contact elements is electrically conductively connected to the first semiconductor layer and the plurality of second contact elements is electrically conductively connected to the second semiconductor layer, wherein the molded body at least partially encloses the optoelectronic semiconductor chip, wherein the semiconductor component comprises a mounting face formed by a surface of the molded body at least in places, wherein the plurality of first and the plurality of second contact elements protrude through the molded body in a region of the mounting face, and wherein a varistor paste is located between the plurality of first contact elements and the plurality of second contact elements, the paste configured to protect the optoelectronic semiconductor chip from an electrostatic discharge.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Further features, configurations and developments result from the following description of the exemplary embodiment in conjunction with the figures.

[0048] Like, similar or equivalent elements are provided with the same reference numerals throughout the drawings.

[0049] The figures and the size ratios of the elements indicated in the Figures are not necessarily to scale. Individual elements and in particular layer thicknesses may rather be illustrated in an exaggerated size for a better understanding and/or for the sakes of clarity.

[0050] The Figures show in:

[0051] FIGS. 1 to 3 a first exemplary embodiment for a surface mountable semiconductor component,

[0052] FIGS. 4 and 5 another exemplary embodiment for a surface mountable semiconductor component,

[0053] FIGS. 6 and 7 another exemplary embodiment for an optoelectronic semiconductor component,

[0054] FIG. 8 an arrangement of a surface mountable semiconductor component according to the invention on a circuit board,

[0055] FIGS. 9 to 13 an exemplary embodiment for a method for producing surface mountable semiconductor components based upon intermediate steps illustrated in a schematic sectional view, and

[0056] FIG. 14 another exemplary embodiment for a surface mountable semiconductor component.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0057] FIGS. 1 to 3 show an exemplary embodiment for a surface mountable semiconductor component. The semiconductor component, generally indicated with 100, comprises an optoelectronic semiconductor chip 10 which is enclosed by a molded body 40 of silicone. The optoelectronic semiconductor chip 10 comprises a semiconductor body 20 which is arranged on a carrier body 12 of sapphire and comprises a semiconductor layer sequence 24, in which an active region 23 is designed between a first semiconductor layer 21 and a second semiconductor layer 22. A mounting face 50 is designed on an underside of the component 100, which is at least in places formed by a surface of the molded body 40. Furthermore, the semiconductor component 100 comprises a plurality of first contact elements 31 and a plurality of second contact elements 32, which protrude through the molded body in the region of the mounting face 50. The first contact elements are electrically conductively connected to the first semiconductor layer and the second contact elements 32 are electrically conductively connected to the second semiconductor layer 22. In the present exemplary embodiment, the second semiconductor layer 22 is removed in the peripheral regions of the semiconductor chip and is directly contacted there by the first contact elements 31. Both the first semiconductor layer 21 and the second semiconductor layer 22 are each connected to the contact elements 31, 32 in regions where the component is contacted from the outside in a plan view. Optionally, a mirror layer, for example made of silver, may be designed between the second semiconductor layer 22 and the contact elements 32 (which is not shown).

[0058] Each of the contact elements 31, 32 comprises a connection base 33, which penetrates through the molded body 40 and terminates flush with the mounting surface 50, as well as a cap element 34, which vertically protrudes from the mounting face. The connection bases 33 may have the shape of cylinders and may consist of copper, for example. The cap elements 34 are designed as solder bumps, for example. The connection bases 33 have a height (dimension in the vertical direction) between 10 m and 150 m. At the same time, this is the height of the molded body 40 in the region of the mounting face 50 (indicated with reference numeral 41).

[0059] In the exemplary embodiment illustrated in FIGS. 1 to 3, the semiconductor chip is a sapphire chip in a flip chip arrangement and is surrounded by a molded body with a thickness of 150 m except for the region of the mounting face 50 (underside of the component). The arrows illustrated in FIGS. 2 and 3 indicate the pressure of the molded body 40 to the semiconductor chip 10, which ensures a good mechanical stability between both elements. For example, the connection bases 33 may be generated galvanically during production of the semiconductor chip 10, while the cap elements 34 are formed but not before first forming the molded body 40.

[0060] In contrast to the exemplary embodiment shown in FIGS. 1 to 3, a varistor paste 35 is applied between the plurality of first contact elements 31 and the plurality of second contact elements 32 in the exemplary embodiment illustrated in FIGS. 4 and 5, which paste is designed for protection of the optoelectronic semiconductor chip 10 from an electrostatic discharge. The use of a varistor paste, which may contain a polymer with semiconductor particles such as particles made of silicon carbide, comes with the advantage that additional efforts are not required due to the installation of an additional switch in the type of a protective diode. Varistor pastes provide forward voltages in the range between 500 and 1000 V.

[0061] In the exemplary embodiment illustrated in FIGS. 1 to 5, the molded body 40 may contain a luminescence conversion material. In contrast, FIGS. 6 and 7 show an exemplary embodiment in which the molded body 40 is free of a luminescence conversion material and a luminescence conversion layer 42 is at least sectionally arranged between the molded body 40 and the semiconductor chip 10. Said luminescence conversion layer 42 may be formed by sedimentation, spray coating or electrophoretic deposition, for example. In the illustrated exemplary embodiment, said layer is a sprayed luminescence conversion layer which is surrounded by a molded body 40 consisting of transparent silicone for fixing and mechanical stabilization here. In addition, the molded body 40 may contain fused silica which increase the mechanic stability and strength of the component.

[0062] FIG. 8 shows the semiconductor component illustrated in FIGS. 6 and 7 in a mounted state. The component 100 is soldered to conductor tracks 80 of a circuit board 200 by the solder bumps thereof. The latter are acting as spacer elements between the mounting face 50 of the component 100 and the surface of the circuit board 200. An intermediate layer 81 may be formed in the resulting interspaces, which acts as a reflector. This achieves that forming a reflecting layer inside the semiconductor chip 10 is no longer required. While the surface of the circuit board 200 is usually not reflecting, since it consists of epoxy and copper, the intermediate layer 81 with the reflecting design advantageously achieves a deflection of light away from the circuit board 200.

[0063] FIGS. 9 to 13 illustrate an exemplary embodiment for a method for producing a multitude of surface mountable semiconductor components. In the method step illustrated in FIG. 9, a plurality of singulized semiconductor chips 10, the semiconductor layers of which are electrically conductively connected to a plurality of connection sockets 33 made of copper, are fastened to an auxiliary carrier 70 by means of an adhesive layer 71. Here, the semiconductor chips 10 are arranged on the auxiliary carrier 71 in such a way that the semiconductor bodies face the auxiliary carrier 71 viewed from the carrier bodies of the semiconductor chips 10. The semiconductor chips 10 are arranged in a grid array and spaced from one another in a lateral direction, i.e., in a direction parallel to the main extension plane of the auxiliary carrier 71.

[0064] The adhesive layer 71 can be a double-sided adhesive film or consist of silicone which additionally acts as an anti-stick layer. Interspaces 72 free of solid material are formed between each of the semiconductor chips 10 and the auxiliary carrier 70, which spaces develop in the regions between the connection bases 33. If a thin silicone layer (with a thickness of between 10 and 20 m, for example) is used, the intermediate spaces 72 can readily be filled with molding material in a subsequent method step. However, using the film as an adhesive layer comes with the disadvantage that it is easily flexible and thus leads to the development of interspaces 72 of reduced size.

[0065] In the subsequent method step shown in FIG. 10, a molded body compound 43 is produced by means of compression molding, said body surrounding the semiconductor chips 10 from all sides and in particular closing the intermediate spaces 72 between the connection bases 33 of semiconductor chips 10. Silicones, acrylates and epoxies are used as molding material. As an alternative, the molded body compound can be formed by an injection molding process, wherein the use of blue-stable or UV stable thermoplastics, polycyclohexylenedimethylene terephthalate (PCT), is advantageous. The use of thermosetting polymers, such as silicone, is possible as well. The molding material can be filled with fillers that contain silicon oxide, boron nitride, aluminum oxide, aluminum nitride or phosphors, for example.

[0066] In the method step illustrated in FIG. 11, the auxiliary carrier 70 is removed by delamination. This may be effected by heating the adhesive layer and/or dissolving the adhesive layer 71 by chemical processes and/or by using a mechanical force.

[0067] In the method step illustrated in FIG. 12, cap elements 34 in the form of solder bumps 34 are formed on the connection bases 33. The solder bumps 34 are re-melted in a thermal process. Advantageously, a flux agent is used to bond the solder bumps and to improve the re-melting behavior. The solder can be applied galvanically.

[0068] For singulation into semiconductor components 100 (see FIG. 13), the molded body compound 43 is separated along singulation lines. This can be effected mechanically, e.g., by means of sawing, cutting or punching, chemically, e.g., by means of etching, and/or by means of coherent radiation, e.g., by laser ablation.

[0069] FIG. 14 shows another exemplary embodiment of an optoelectronic surface-mountable semiconductor component in which compared to the exemplary embodiments described in the foregoing a more complex wiring inside the semiconductor chip 10 is provided, thereby allowing the selecting of a more simple contacting geometry on the level of the carrier on which the surface-mountable semiconductor component is to be mounted later.

[0070] The plurality of first contact elements 31 is electrically connected to the first semiconductor layer 21 via a first connection layer 61. The plurality of second contact elements 32 is electrically conductively connected to the second semiconductor layer 22 via a second connection layer 62. An insulation layer 63 is arranged between the first connection layer 61 and the second connection layer 62. A cut-out 25 is provided in the semiconductor layer sequence 24, which extends through the insulation layer 63, the second connection layer 62, the second semiconductor layer 22 and the active region 23 into the first semiconductor layer 21 and which is at least partially filled with electrically conductive material. The application of an electric voltage between the first contact elements 31 and the second contact elements 32 allows charge carriers to be injected into the active region 23 from opposite directions and recombine there whilst emitting radiation.

[0071] In a plan view of the semiconductor component, the first connection layer 61 and the second connection layer 62 overlap each other. The geometry described makes it possible to contact the semiconductor layers in regions which are different from the regions in which the semiconductor component is contacted externally, viewed in a plan view of the semiconductor component. The second connection layer 62 may be designed as a mirror layer, e.g., of silver.

[0072] The invention is not limited by the description in conjunction with the exemplary embodiments. The invention rather comprises any new feature as well as any combination of features, in particular including any combination of features in the patent claims, even if said feature or said combination per se is not explicitly indicated in the patent claims or exemplary embodiments.