HIGH POWER AND BROADBAND DISTRIBUTED CHOKE INDUCTOR FOR DISTRIBUTED POWER AMPLIFIERS

Abstract

A broadband choke inductor is used in a bias circuit for broadband high-power distributed amplifiers.

Claims

1. A bias circuit used to reduce shunt parasitic capacitors and losses in broadband, high efficiency and high power designs, comprising: at least two choke inductors on the bias circuit, wherein a first choke inductor of the at least two choke inductors is connected to a drain terminal of at least one transistor, and a second choke inductor of the at least two choke inductors is connected to a supply voltage (V.sub.DD) and grounded via a decoupling capacitor.

2. The bias circuit according to claim 1, wherein each of the at least two choke inductors has a transmission line width of 15 μm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is a view of the measurement configuration used in the performance evaluations of the inductor in the conventional bias circuit used in the inventive distributed power amplifier designs.

[0017] FIG. 2 is a view comparing the simulation and measurement results of the inductor (Lc) in the conventional bias circuit used in the inventive distributed power amplifier designs.

[0018] FIG. 3 is a view of the high frequency lumped element model of the inventive bias circuit inductor (Lc).

[0019] FIG. 4 is a view of the simulation result showing the transmission losses and resonant frequency when two inductors with the same inductance value at low frequency with wide and narrow transmission line width are used in the bias circuit.

[0020] FIG. 5 is a view of the simulation result showing the transmission losses and resonant frequency when the parasitic capacitors Cp1 and Co shown in the lumped element model of the inventive inductor are present and when they are eliminated.

[0021] FIG. 6 is a view of the schematic drawing of the distributed amplifier with discrete components, where the inventive distributed amplifier is used.

[0022] FIG. 7 is a view of the lumped element model of the inventive distributed inductor together with the lumped element model of the distributed amplifier.

[0023] FIG. 8 is a view of the configuration of the inventive distributed inductor in a distributed power amplifier.

DESCRIPTION OF PART REFERENCES

[0024] 1. Inductor (L.sub.c)

[0025] C.sub.s, C.sub.o, C.sub.s1, C.sub.s2, C.sub.p1, C.sub.p2, C.sub.p3: Capacitor

[0026] R.sub.1, R.sub.2, R.sub.g : Resistance

[0027] L.sub.1, L.sub.2: Inductor

[0028] V.sub.DD : Drain Voltage

[0029] V.sub.G: Gate Voltage

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] In this detailed description, the preferred configurations of the inductor (1) in the bias circuit of the invention will be explained only for a better understanding of the subject matter.

[0031] The bandwidth of an optimum inductor (1) that fulfills the criterion that the reactance value of the choke inductor (1) should be high at low frequency and the shunt parasitic capacitor (C.sub.p3) should be low in order to sufficiently prevent RF transmission is between 2-18 GHz. The simulation of a choke inductor (1) whose parameters are determined according to this optimum value is shown in FIG. 1.

[0032] Transmission lines having large width provide low resistance (R.sub.1, R.sub.2) but result in more shunt parasitic capacitors (C.sub.p1, C.sub.p2, C.sub.p3). These shunt parasitic capacitors (C.sub.p1, C.sub.p2, C.sub.p3) seriously affect the performance at high frequencies.

[0033] FIG. 4 is a view of the S21 simulation result of the 60 μm inductor (1) and 40 μm inductor (1) with the transmission line width subject to the invention. In addition, the lumped element model of the inductor (1) shown above is shown in FIG. 3. Here, the most important element determining the high frequency cut-off point is the Cp3 shunt capacitor (C.sub.p3). By reducing this parasitic capacitor (C.sub.p3), wider bandwidths can be achieved as can be seen in FIG. 4.

[0034] The most important parasitic capacitors (C.sub.p1, C.sub.o) affecting the high frequency losses are Cp1 and Co. By reducing these parasitic capacitors (C.sub.g), lower losses at high frequency can be achieved as can be seen in FIG. 5.

[0035] To increase the broadband value, the parasitic capacitor (Cp3) needs to be reduced. Reducing the width of the inductor (1) transmission lines reduces the parasitic capacitor (Cp3) but increases the losses. To reduce losses, more than one inductor (1) can be used in parallel. Since the current through each inductor (1) is reduced, the losses are also reduced.

[0036] In addition, when another small inductor (1) is placed between both choke inductors, this distributed structure eliminates the effect of the shunt parasitic capacitors (Cp1+Co). In the distributed amplifier structure, this small inductor (1) is already present between neighboring transistors and is used to neutralize the shunt capacitor of the transistor itself. By further increasing the value of this small inductor (1), the shunt parasitic capacitor of the bias choke inductor (1) can also be eliminated. The value of this small inductor (1) between two adjacent transistors is not equal in non-uniformly distributed power amplifiers (NDPA). In these amplifiers, the impedance seen by the first transistor can be made high and the impedance seen by the last transistor can be made low in order to achieve better power matching and increase efficiency. In this context, each inductor (1) value can be calculated separately according to the respective impedance and shunt parasitic capacitor values.

[0037] In one embodiment of the invention, five inductors (1) having a transmission line width of 15 μm are used in the bias circuit together with smaller inductors (1). Signal measurements are made in the bias circuit with five inductors (1) and it is observed that the bandwidth increases without any performance loss. One end of the inductors (1) used in the bias circuit is connected to the drain terminal of a transistor and the other end is connected to ground via the supply voltage (V.sub.DD) and the decoupling capacitor. The bias circuit with five inductors (1) is connected to five different transistors.