Flash memory and method of manufacturing the same

Abstract

A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

Claims

1. A flash memory, comprising: a memory gate on a substrate; a select gate adjacent to said memory gate, wherein said select gate comprises an upper portion and a lower portion; and an oxide-nitride spacer between said memory gate and said select gate, wherein said oxide-nitride spacer comprises an oxide layer directly contacting said memory gate and a nitride layer having an upper nitride portion corresponding to said upper portion and a lower nitride portion corresponding to said lower portion, wherein said upper portion covers, and is in direct contact with, a topmost surface of said lower nitride portion with respect to said substrate, and a topmost surface of said upper nitride portion is higher than a topmost surface of said oxide layer with respect to said substrate, and a conformal thickness of said upper nitride portion is thinner than a conformal thickness of said lower nitride portion.

2. The flash memory of claim 1, further comprising a plane interface between said upper nitride portion and said lower nitride portion, wherein said plane is higher than the top surface of said memory gate.

3. The flash memory of claim 1, wherein a height of said oxide layer of said oxide-nitride spacer is flush with a top surface of said memory gate.

4. The flash memory of claim 1, wherein a thickness of said upper nitride portion is smaller than 60% of a thickness of said lower nitride portion.

5. The flash memory of claim 1, wherein a thickness of said upper nitride portion is smaller than 30 Angstroms.

6. The flash memory of claim 1, wherein a thickness of said lower nitride portion is larger than 40 Angstroms.

7. The flash memory of claim 1, wherein a height of said select gate is higher than a height of said memory gate.

8. The flash memory of claim 1, further comprising a gate dielectric layer between said memory gate and said substrate and between said select gate and said substrate.

9. The flash memory of claim 8, wherein said gate dielectric layer between said memory gate and said substrate is oxide/nitride/oxide tri-layer.

10. The flash memory of claim 1, wherein said nitride layer comprises silicon nitride (SiN) or silicon carbide nitride (SiCN).

11. The flash memory of claim 1, wherein said memory gate and said select gate comprise polysilicon.

12. A flash memory, comprising: a memory gate on a substrate; a select gate adjacent to said memory gate; and an oxide-nitride spacer between said memory gate and said select gate, wherein said oxide-nitride spacer comprises an oxide layer directly contacting said memory gate and a nitride layer having an upper nitride portion and a lower nitride portion, wherein a topmost surface of said upper nitride portion is higher than a topmost surface of said oxide layer with respect to said substrate and is flushed with a top surface of said select gate with respect to said substrate, and a conformal thickness of said upper nitride portion is thinner than a conformal thickness of said lower nitride portion.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:

(2) FIGS. 1-6 are cross-sectional views depicting an exemplary process flow of manufacturing a flash memory in accordance with the embodiment of the present invention;

(3) FIG. 7 is an enlarged cross-sectional view depicting an exemplary flash memory structure in accordance with the embodiment of the present invention; and

(4) FIG. 8 is a cross-sectional view of a flash memory in prior art.

(5) It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

(6) In the following detailed description of the present invention, reference is made to the accompanying drawings which form a part hereof and is shown by way of illustration and specific embodiments in which the invention may be practiced. These embodiments are described in sufficient details to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

(7) Before describing the preferred embodiment in more detail, further explanation shall be given regarding certain terms that may be used throughout the descriptions.

(8) The term etch or etching is used herein to generally describe a fabrication process of patterning a material, such that at least a portion of the material remains after the etch is completed. For example, it should be understood that the process of etching silicon involves the steps of patterning a masking layer (e.g., photoresist or a hard mask) above the silicon, and then removing the areas of silicon no longer protected by the masking layer. As such, the areas of silicon protected by the mask would remain behind after the etch process is complete. However, in another example, etching may also refer to a process that does not use a mask, but still leaves behind at least a portion of the material after the etch process is complete. The above description serves to distinguish the term etching from removing. When etching a material, at least a portion of the material remains behind after the process is completed. In contrast, when removing a material, substantially all of the material is removed in the process. However, in some embodiments, removing is considered to be a broad term that may incorporate etching.

(9) During the descriptions herein, various regions of the substrate upon which the field-effect devices are fabricated are mentioned. It should be understood that these regions may exist anywhere on the substrate and furthermore that the, regions may not be mutually exclusive. That is, in some embodiments, portions of one or more regions may overlap. Although up to three different regions are described herein, it should be understood that any number of regions may exist on the substrate and may designate areas having certain types of devices or materials. In general, the regions are used to conveniently describe areas of the substrate that include similar devices and should not limit the scope or spirit of the described embodiments.

(10) The terms forming, form, deposit, or dispose are used herein to describe the act of applying a layer of material to the substrate. Such terms are meant to describe any possible layer-forming technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc. According to various embodiments, for instance, deposition may be performed according to any appropriate well-known method. For instance, deposition can comprise any process that grows, coats, or transfers material onto a substrate. Some well-known technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and plasma-enhanced CVD (PECVD), amongst others.

(11) The substrate as used throughout the descriptions is most commonly though to be silicon. However, the substrate may also be any of a wide array of semiconductor materials such as germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate may be electrically non-conductive such as a glass or sapphire wafer.

(12) FIGS. 1-6 are cross-sectional views depicting an exemplary process flow of manufacturing a flash memory in accordance with the embodiment of the present invention. First, please refer to FIG. 1. Memory cell/device is formed preliminarily on a substrate 100, such as silicon. Substrate 100 is commonly p-type or a p-type well while the doped source/drain regions (not shown) are n-type. However, it is also possible for substrate 100 to be n-type while the source/drain regions are p-type.

(13) The substrate 100 is divided several regions 100A, 100B, and 100C. A first memory (array) region 100A of the substrate 100 may be used for memory components. For instance, according to the preferred embodiment, the memory region 100A may be used to form a number of select gate/memory gate pairs. High-voltage (HV) and/or logic circuitry may be formed in periphery, which includes second and third regions 100B and 100C respectively according to the preferred embodiments. The second region 100B may comprise high voltage control logic and the third region 100C may comprise low voltage control logic. The memory array region 100A, the high-voltage region 100B and the logic region 100C or the semiconductor devices formed on each region are isolated from each other by shallow trench isolation (STI) 101.

(14) As shown in FIG. 1, a gate dielectric layer is formed on each region 100A-100C. According to the preferred embodiments, the gate dielectric layers 102a/102b/102c on different regions may be different thicknesses as shown to meet different device requirements, but this need not be the case. The gate dielectrics can be any insulating material including but not limited to oxides, nitrides, or some combination thereof. Preferably, the gate dielectric layer 102a on the memory region 100A is an oxide/nitride/oxide tri-layer stack collectively and commonly referred to as ONO, which commonly serves as a charge trapping dielectric includes a charge trapping silicon nitride layer sandwiched between two silicon dioxide layers. Other charge trapping dielectrics may include a silicon-rich nitride film, or any film that includes, but is not limited to, silicon, oxygen, and nitrogen in various stoichiometries. The gate dielectric layer 102a/102b/102c may be formed through any well-known method. For instance, the dielectrics may be grown on the substrate 100 and comprise an oxide of the substrate material (e.g., silicon oxide).

(15) A gate conductor layer 103 is formed on the gate dielectric layer 102. Any appropriate gate conductor material could be used to form the gate conductor layer 103 such as a polysilicon, according to the preferred embodiments. The gate conductor layer 103 may be formed or disposed according to any appropriate well-known method such as deposition. Deposition can comprise any process that grows, coats, or transfers material onto a substrate. Some well-known technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), moleculear beam epitaxy (MBE), atomic layer deposition (ALD), and plasma-enhanced CVD (PECVD), amongst others.

(16) A hard mask layer 104 is disposed over the gate conductor layer 103. The hard mask layer 104 may comprise any suitable material that allows for selective removal (e.g., etching) of the unmasked portion of the gate conductor layer 103. According to the preferred embodiment, the hard mask layer 104 is a silicon nitride (SiN) layer or a silicon carbon nitride (SiCN) layer.

(17) Refer still to FIG. 1. It can be noticed that the gate dielectric layer 102a, the gate conductor layer 103, and the hard mask layer 104 in the memory region 100A are patterned to create a gate structure 105. This patterning process may comprise several conventional steps. For example, the hard mask layer 104 may be first patterned into hard mask 104a with gate patterns using photoresist. An etch process is then performed with hard mask 104a to pattern the gate conductor layer 103 and the gate dielectric layer 102a into memory gate 103a and gate dielectric. In case of blurring and confusing the key points of the present invention, the above detailed steps of patterning process are not depicted in drawings and the gate structure 105 is consequently presented in FIG. 1.

(18) Refer now refer to FIG. 2. A spacer 106 is formed on the side of the gate structure 105. According to the preferred embodiment, the spacer 106 comprises one or more layers of dielectric such as oxide-nitride (ON), which referred as an ON spacer. The formation of ON spacer 106 may comprise several conventional steps. For example, an oxide layer 106a and a nitride layer 106b may be formed sequentially and conformally on over the gate structure 105 and the substrate 100 by well-known deposition method. The deposited, conformal oxide layer 106a and nitride layer 106b are then subject to an etch process. The etch process would remove the portion of the oxide layer and nitride layer on the plane, thus only the portion on the sidewall of the gate structure 105 is left and forms a spacer structure. Preferably, the material of the nitride layer 106b is the same as the hard mask 104a, such as silicon nitride (SiN) or silicon carbide nitride (SiCN), so that the two nitride portions can be selectively etched or removed in the same process.

(19) Refer now refer to FIG. 3. After forming the ON spacer 106, a sacrificial layer 107 is blanket-covered on the gate structure 105 and the substrate 100. According to the embodiment, the sacrificial layer 107 may be preferably a photoresist layer or an organic dielectric layer (ODL). The advantage of the organic dielectric is that it can be easily patterned or thinned using conventional dry etching techniques which utilize an oxygen-containing ambient. Suitable organic dielectric materials that can be employed in the invention include, but are not limited to: diamond-like carbon (DLC), fluorinated DLC, polyimides, fluorinated polyimides, parylene-N, parylene-F, benzocyclobutanes, poly(arylene ethers), polytetra-fluoroethylene (PTFE) derivatives marketed by Du Pont de Nemours, Inc. under the registered trademark Teflon AF, poly(naphthalenes), poly (norbornenes), foams of polyimides, organic xerogels, porous PTFE and other nano-, micro- or macro-porous organic materials. The photoresist layer 107 may be formed on the surface of substrate 100 using conventional deposition techniques. For example, chemical vapor deposition, plasma vapor deposition, sputtering, dip coating, spin-on coating, brushing, spraying and other like deposition techniques may be employed.

(20) Please now refer to FIG. 4. After forming the photoresist layer 107, a blanket etching back process is performed to thin the thickness of the photoresist layer 107. According to the embodiment, the photoresist layer 107 would be thinned to the extent that the underlying gate structure 105 is exposed, and more specifically, to the extent that the surface of thinned photoresist layer 107 in memory region 100A is flush with the memory gate 103a, without affecting the unexposed nitride hard mask layer in the high-voltage region 100B and the logic region 100C.

(21) The key feature of the above-identified thinning process of the blanket-covered photoresist layer 107 in the present invention is that it can expose a portion of the nitride layer 106b of the ON spacer 106 above the memory gate 103a. Moreover, the thinning process can thin the thickness of the exposed nitride layer 106b of the ON spacer 106 at the same time. For example, according to the preferred embodiment, the thickness of the nitride layer 106b is larger than 40 Angstroms (). The thinned nitride layer 106b above the top surface of the memory gate 103a is smaller than 30 Angstroms, which is about 60% of the thickness of the nitride layer 106b below the top surface of the memory gate 103a.

(22) Please now refer to FIG. 5. After the thinning process, the remaining photoresist layer 107 is first completely removed by an ashing and a Caroz clean process. A select gate 108 is subsequently formed on the side of the ON spacer 106, wherein the ON spacer 106 interfaces between the memory gate 103a and the select gate 108. The formation of the select gate 108 may comprise several conventional steps. For example, a gate conductor layer (not shown) is first conformally formed over the gate structure 105 and the substrate 100. The gate conductor layer may be formed of any suitable conductor, such as polysilicon. After deposition of the gate conductor layer, the gate conductor layer may be removed from all portions of the gate structure 105 except the portion on the sidewall of one spacer 106 according to a number of well-known methods. The select gate 108 formed by the removal of these portions of the gate conductor layer is depicted in FIG. 5, which is substantially taper-shaped and higher than the memory gate 103a. In case of blurring and confusing the key points of the present invention, the above detailed steps of forming select gate 108 are not depicted in drawings and the select gate structure is consequently presented in FIG. 5.

(23) Refer again to FIG. 5. It can also be seen in FIG. 5 that a gate structure 109 is also defined in high-voltage region 100B. The gate structure 109 may be formed by the same process flow as the gate structure 105 after forming the select gate 108. For example, first using a photoresist with gate pattern to pattern the nitride hard mask layer 104, performing a dry etch process using patterned hard mask and with photoresist covering on other regions to pattern the underlying gate conductor layer 103 and the gate dielectric layer 102b. Redundant description of similar steps is herein omitted by simplicity and clarity.

(24) Please refer now to FIG. 6. After forming the select gate 108, the remaining hard mask 104a in memory region 100A and the hard mask layer 104 in HV region 100B and logic region 100C will be removed by a wet etching process using phosphoric acid (H.sub.3PO.sub.4) to expose the underlying memory gate 103a. This removing process reflects the critical feature and function of thinner nitride spacer. As shown in FIG. 5, the thinner upper portion of nitride layer 106b would reduce the contact area with the etchant in the wet etching process for removing the hard mask, thereby significantly mitigating the etch damage of the upper nitride portion of the ON spacer 106. The electrical performance and the reliability of the final memory device are therefore well-maintained. In comparison to the above feature, conventional spacer with larger uniform thickness is highly exposed to the etchant and prone to be damaged and depleted, like the portion 200 shown in FIG. 8. The damage portion 200 shows the condition that a portion of the select gate and memory gate is not isolated from each other by the spacer. This condition would significantly lower the breakdown voltage between the select gate and memory gate and impact the overall electrical performance.

(25) Refer again to FIG. 6. It can also be seen that the gate structure 110 is defined in logic region 100C. The gate structure 110 may be formed by the same process flow as the gate structures 105 and 109 prior to the removal of the hard mask layer 104 in the logic region 100C. Redundant description of similar steps is herein omitted by simplicity and clarity.

(26) Additionally, an optional wet etching process using diluted hydrofluoric acid (DHF) may be performed to remove the oxide layer above the memory gate or clean the substrate.

(27) According to the above-mentioned embodiments shown in FIGS. 1-6, a flash memory structure is also provided in the present invention, as shown in the enlarged cross-sectional view in FIG. 7, wherein the structure includes a memory gate 103a on a substrate 100, a select gate 108 adjacent to the memory gate 103a, wherein the height of the select gate 108 is higher than the height of the memory gate 103a. An oxide-nitride spacer 106 interfaces between the memory gate 103a and the select gate 108, wherein the oxide-nitride spacer 106 further includes an oxide layer 106a and a nitride layer 106b having an upper nitride portion 111a and a lower nitride portion 111b, and the upper nitride portion 111a is thinner than the lower nitride portion 111b. A plane 111 interfaces between the upper nitride portion 111a and the lower nitride portion 111b, wherein the plane 111 is higher than the top surface of the memory gate 103a. The height of oxide layer 106a is preferably flush with the top surface of the memory gate 103a.

(28) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.