Fin-shaped field effect transistor

Abstract

The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET).

Claims

1. A fin-shaped field effect transistor (FinFET), comprising: a substrate having a fin structure; a plurality of trenches formed in the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer being a portion of a surface region of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy.

2. The fin-shaped field effect transistor (FinFET) according to claim 1, wherein the alloy comprises a center region being of higher concentration of a germanium component and a cap region being of lower concentration of the component, the cap region is disposed on the top of the center region.

3. The fin-shaped field effect transistor (FinFET) according to claim 2, wherein the center region is partially covered by the amorphous layer.

4. The fin-shaped field effect transistor (FinFET) according to claim 3, wherein the cap region is laterally adjacent to the amorphous region.

5. The fin-shaped field effect transistor (FinFET) according to claim 2, wherein the germanium component is germanium and the center region has a germanium concentration in a range of 35%-60%.

6. The fin-shaped field effect transistor (FinFET) according to claim 2, wherein the germanium component is germanium and the cap region has a germanium concentration in a range of 20%-30%.

7. The fin-shaped field effect transistor (FinFET) according to claim 1, wherein the gate structure comprises a polysilicon conductor layer, a dielectric protecting layer on the top of the polysilicon conductor layer, and a pair of spacers on sides of a stack of the polysilicon conductor layer and the dielectric protecting layer.

8. The fin-shaped field effect transistor (FinFET) according to claim 7, wherein the dielectric protecting layer is a multi-layer structure.

9. The fin-shaped field effect transistor (FinFET) according to claim 1, wherein the gate structure comprises a metal electrode and a pair of spacers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

(2) FIG. 1 is a cross-sectional view illustrating a manufacturing step of a substrate having a gate structure according to the method provided by the present invention;

(3) FIG. 2 is a cross-sectional view illustrating an amorphous layer formation step according to the method provided by the present invention;

(4) FIG. 3 is a cross-sectional view illustrating formation of a pair of sacrificial spacers according to the method provided by the present invention;

(5) FIG. 4 is a cross-sectional view illustrating formation of a trench according to the method provided by the present invention;

(6) FIGS. 5-6 are cross-sectional views illustrating a process of selective epitaxial growth according to the method provided by the present invention; and

(7) FIG. 7 is a cross-sectional view illustrating removal of the sacrificial spacers and source/drain implantation according to the method provided by the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(8) The present invention provides a manufacturing method of a FinFET and a device thereof with an amorphous implantation in order to improve height variation of epitaxial grown sources and drains and is described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only but not intended to be exhaustive or to be limited to the precise form disclosed.

(9) In the following illustration, the element arranged repeatedly is described in word one, a or an for simpler explanation. However, one skilled in the art should understand the practical structure and arrangement of each element based on the following illustration and figures provided in the present application.

(10) FIGS. 1-7 are cross-sectional structures illustrating different steps during the manufacturing process following the method provided by the present invention. As shown in FIG. 1, a substrate 1 has a base 11 and a fin structure 12 on the base 11. The substrate 1 can be a polysilicon or silicon-containing substrate with polycrystalline lattice, and formation of the fin structure 12 can be similar or the same as conventional methods and are omitted from the illustration below for the sake of brevity. Then a gate structure 2 is formed on the fin structure 12 with a direction perpendicular to an extending direction of the fin structure 12. The gate structure 2 can comprises a conductor layer 21, a protecting layer 22, and a pair of spacers 23. The conductor layer 21 can be made of polysilicon or other conducting material. The protecting layer 22 is formed on the top of the conductor layer 21, to be used for protection. And the pair of spacers 23 is formed on two lateral/opposite sides of the stack of the conductor layer 21 and the protecting layer 22. The protecting layer 22 is made of dielectric material and can be multi-layer structure depending on different cases. For example, the protecting layer 22 may comprise a nitride layer (such as silicon nitride) right on the top of the conductor layer 21 and an oxide layer (for example, used as a hard mask) is then formed on the top of the nitride layer. The spacers 23 can also be a multi-layer structure formed by more than one layer of dielectric material.

(11) Then as shown in FIG. 2, an amorphous implantation P1 is performed to form an amorphous layer 3 on an exposed portion of the fin structure 12 exposed by the gate structure 2. The precursor used in the amorphous implantation P1 is better to be heavy ions or atoms, and can be no electric charges to avoid affecting doping implantation later on in the manufacturing process. The precursor(s) can be selected from the group consisting of indium (In), argon (Ar), (Antimony) Sb, and germanium (Ge). However, as long as the amorphous layer 3, being a portion of a surface region of the fin structure exposed by the gate structure, can be formed properly and the amorphous implantation P1 does not affect later process and product yield, precursor(s) can be selected from whatever it's suitable, such as boron (B) or difluoroboron (BF.sub.2). Moreover, due to the impact of the precursor(s) to the surface of the exposed portion of the fin structure 12, the top surface of the amorphous layer 3 can be slightly curved down as shown in FIG. 2. In the case of polysilicon as the substrate 1, the amorphous layer 3 is amorphous silicon.

(12) Then as shown in FIG. 3, a pair of sacrificial spacers 4 is formed on the lateral sides of the gate structure 2 covering the spacers 23 and a portion of the amorphous layer 3. A light doped source and drain (LDD) implantation (not shown) is selectively performed before the amorphous implantation P1 or before the formation of sacrificial spacers 4.

(13) A trench T1 is then formed on the fin structure adjacent to the sacrificial spacers 4 by etching and using the gate structure 2 and the sacrificial spacers 4 as a mask as shown in FIG. 4. Thus, the portion of the amorphous layer 3 covered by the sacrificial spacers 4 is remained on the fin structure 12 on the top edge of the trench T1. The shape of the trench T1 can be altered by different etching process, such as dry etch and wet etch, and also by different parameters of the process. However, the shape of the trench T1 is most-likely to be slightly narrower on the top and slightly larger in the middle of the trench T1 as shown in FIG. 4.

(14) Then as shown in FIG. 5-6, a selectively epitaxial growth is performed to grow an alloy 5 in the trench T1. The alloy 5 can comprise three regions: a buffer region 51, a center region 52, and a cap region 53. As shown in FIG. 5, a buffer region 51 is firstly grown along the inner surface of the trench T1 having a relatively low concentration of germanium component, and the center region 52 is then grown along the inner surface of the buffer region 51 having a relatively high concentration of component as shown in FIG. 5. The center region 52 has a germanium concentration in a range of 35%-60% and preferably in a range of 40%-50%, and the buffer region 51 has a germanium concentration in a range of 20%-30%. The buffer region 51 is used for preventing mismatch and interface effect between high concentration of germanium component of an alloy 5 and the fin structure 12 of the substrate 1. For instance, in the case where the alloy 5 is silicon-germanium (SiGe) doped with boron, the buffer region 51 contains about 25% of germanium, and the center region 52 contains about 45% of germanium.

(15) Following the method provided by the present invention, the center region 52 with higher concentration of germanium will stop growing at the bottom of the remained amorphous layer 3, as shown in FIG. 5. The buffer region 51 and the center region 52 are partially covered by the amorphous layer 3. Due to the crystal structure of the amorphous layer 3 and characteristics of selective epitaxial growth, a portion of an alloy with higher concentration of germanium is difficult to grow above the remained amorphous layer 3. Thus a height of the center region 52 of the alloy 5 with higher concentration of germanium is well-controlled. And as shown in FIG. 6, only the cap region 53 with a relatively low concentration of germanium is then able to grow on the top of the center region 52 horizontally contacted with the remained amorphous layer 3. The cap region 53 has a metal concentration in a range of 20%-30% to be used to protect the center region 52. In an embodiment, the alloy 5 is silicon-germanium (SiGe) doped with boron, and the cap region 53 has a metal concentration of about 25% to be used as a SiGe cap to protect the higher-concentration center region 52.

(16) Sequentially as shown in FIG. 7, the sacrificial spacers 4 are removed, and then a source/drain implantation P2 is performed to form a source/drain epitaxial structure 6.

(17) In the case of polysilicon gate, the conductor layer 21 is polysilicon, and the gate structure 2 can be formed by gate-first process as the illustration above. On the other hand, in the case of metal gate, the conductor layer 21 is made of copper, or any other suitable metal, the gate structure 2 can be formed by gate-last process using silicon as a dummy gate as the process illustrated above. And then a dummy gate removal process is performed after the source/drain implantation to refill in a metal electrode in-between the spacers 23 (not shown). In one embodiment, the metal electrode is copper; however, other suitable metal can be used in different cases.

(18) In the conventional manufacturing method, the height of source/drain epitaxial structure is varied (being of different heights), and most commonly, the center region of a wafer is higher than the edge region of a wafer. The present invention provides a method of manufacturing a FinFET and a device thereof with an amorphous layer by an amorphous implantation in order to improve (by reducing) height variation of epitaxial grown sources and drains. Due to the amorphous layer 3 on the top edge of the trench T1, the high concentrated center region 52 of the alloy 5 (active region of the source/drain) is not able to grow above the amorphous layer even with longer time of epitaxial growth. And thus, the height of the source/drain epitaxial structure at the edge of a wafer can have about same height as the source/drain epitaxial structure at the center of the wafer. Better product yield and better performance of a FinFET device is then achieved.

(19) While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.