Distributed driver circuitry integrated with GaN power transistors

Abstract

Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D3) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D3. Each driver element is placed in proximity to a respective section of D3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.

Claims

1. A GaN switching device comprising: a large area lateral GaN power transistor (GaN FET) arranged as a plurality of sections, and a distributed driver comprising a plurality of driver elements, each driver element comprising a pull-up driver transistor and a pull-down driver transistor connected in series, wherein the output of each one of the distributed driver elements is selectively connected to drive a respective one of the sections of the large GaN power transistor.

2. The GaN switching device of claim 1, wherein the pull-down driver transistor is distributed as a plurality of pull-down driver transistor elements, each pull-down driver transistor element being arranged for driving a respective section of the GaN power transistor and wherein a single pull-up driver transistor is provided for driving all sections of the GaN power transistor.

3. The GaN switching device of claim 1, wherein both the pull-up driver transistor and pull-down driver transistor are distributed as a plurality of distributed driver elements, each driver element comprising an individual pull-down driver transistor and an individual pull-up driver transistor in series and providing a gate output for driving its respective section of the GaN power transistor.

4. The GaN switching device of claim 1, wherein the plurality of sections of the GaN FET and the plurality of driver elements are arranged to provide a layout wherein each one of the distributed driver elements is placed in close physical proximity to the respective one of the sections of the large GaN FET that it drives.

5. The GaN switching device of claim 1, wherein each one of the driver elements is placed in close physical proximity to the respective one of the sections of the large GaN power switch, and wherein routing and sizing of respective interconnect tracks connecting the distributed driver elements and respective sections of GaN switch are selected to minimize loop inductance.

6. The device of claim 1, wherein the gate output track connection of the driver element which drives a section of the gate of the large GaN power switch and the return track connection to the source of the pull-down driver transistor of the driver element are magnetically mirrored so as to reduce the loop inductance.

7. The device of claim 1, wherein the routing and sizing of interconnect tracks for the gate output and return between each driver element and respective sections of the GaN power switch are arranged to reduce the loop inductance.

8. The device of claim 7, wherein said tracks comprise two layer tracks arranged in parallel.

9. The device of claim 7, wherein said tracks comprise three parallel tracks wherein a signal line is encompassed by drive lines, above and below the signal line.

10. A GaN switching device comprising: a substrate; an enhancement mode (E-Mode) GaN switch and an integrated GaN driver formed on the substrate; the E-Mode GaN switch comprising a large area lateral GaN transistor switch D3 having an active area that is partitioned into a plurality of sections (D3.sub.1 to D3.sub.n); the integrated GaN driver being integrated monolithically on the substrate adjacent the active area of GaN transistor D3; and the integrated GaN driver being distributed as a corresponding plurality of driver elements, each driver element being located on the substrate in close proximity to a respective one of the plurality of sections of D3 and coupled to the respective section of D3 by low inductance interconnects.

11. A GaN switching device according to claim 10, wherein each driver element comprises a first, pull-up E-Mode GaN driver transistor D1 and a second, pull-down E-Mode GaN driver transistor D2; the drain of D1 being coupled to Vcc, and the source of D1 being coupled to the drain of D2 at node N, which is coupled to the gate of the respective section of D3, and an internal source-sense connection closely coupling the source of the respective section of D3 and the source of D2, such that the first transistor D1 delivers a drive voltage to the gate of the respective section of the GaN transistor switch D3, and the second transistor D2 clamps the gate of the respective section the GaN transistor switch D3 by means of the internal source-sense connection SS.sub.internal; inputs for coupling to a pre-driver supplying gate drive voltages to the gates of D1 and D2 of each driver element and optionally to the gates of each section of D3, and an external source-sense connection SS.sub.external for coupling to the pre-driver.

12. The device of claim 10, wherein each section D3.sub.n of D3 has a respective individual driver element comprising a pull-up driver element D1.sub.n, and a pull-down driver element D2.sub.n.

13. The device of claim 10, wherein each section D3.sub.n of D3 is coupled to a respective individual pull-down driver element D1.sub.n, and wherein a single pull-up driver element D2 is coupled to the plurality of sections of D3.

14. The device of claim 11, wherein each section D3.sub.n of D3 has a respective individual driver element comprising a pull-up driver D1.sub.n and a pull-down driver D2.sub.n.

15. The device of claim 11, wherein each section D3.sub.n of D3 is coupled to a respective individual pull-down driver element D1.sub.n, and wherein a single pull-up driver element D2 is coupled to a plurality of sections of D3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the drawings, identical or corresponding elements in the different Figures have the same reference numeral, or corresponding elements have reference numerals incremented by 100 in successive Figures.

(2) FIG. 1 (Prior Art) shows a circuit schematic of a device comprising a GaN transistor D3; driver circuitry comprising pull-up and pull-down driver transistors, D1 and D2, respectively; and a pre-driver;

(3) FIG. 2 (Prior Art) shows a diagram representing schematically the external pads for source, drain, gate and Vcc connections for the device of FIG. 1;

(4) FIG. 3 (Prior Art) shows a circuit schematic representing a system comprising a large area GaN FET device D3 arranged as a plurality of sections D3.sub.1 to D3.sub.n, coupled to a single centralized driver circuit comprising driver transistors D1 and D2, to illustrate schematically parasitic inductances L.sub.1, L.sub.2, L.sub.3, L.sub.4 introduced by multiple connection paths or tracks of different lengths coupling the driver circuit to the large area GaN FET D3;

(5) FIG. 4 shows a circuit schematic representing a system, according to an embodiment of the present invention, comprising a large area GaN FET D3, arranged as a plurality of sections D3.sub.1 to D3.sub.n, coupled to distributed driver circuitry comprising a pull-up driver transistor D1, and a distributed pull-down driver transistor D2 comprising a plurality of individual sections D2.sub.1 to D2.sub.n, each coupled to respective sections D3.sub.1 to D3.sub.n of the large area GaN FET, to illustrate schematically parasitic inductances L.sub.1, L.sub.2, L.sub.3, L.sub.4, L.sub.5 introduced by multiple connection paths or tracks coupling the driver circuit to the large area GaN FET D3;

(6) FIG. 5 (Prior Art) shows another schematic diagram representing a layout of the system shown in FIG. 3, showing parasitic capacitances L.sub.p of interconnect tracks to each section D3.sub.n of the large area transistor D3, and a source interconnect bus and a drain interconnect bus coupling the sections D3.sub.1 to D3.sub.n in parallel;

(7) FIG. 6 shows another schematic diagram representing a layout of the system, according to the embodiment shown in FIG. 5, comprising a large area GaN FET D3 comprising sections D3.sub.1 to D3.sub.n and distributed driver circuitry wherein sections D1.sub.1 to D1.sub.n and D2.sub.1 to D2.sub.n of distributed driver transistors D1 and D2 are coupled to respective sections D3.sub.1 to D3.sub.n of the large area GaN FET, and comprising low inductance source, drain and gate connection paths and tracks;

(8) FIG. 7 shows schematically the physical layout of a device structure comprising part of a power switch, according to an embodiment of the invention, comprising a large area GaN FET D3 comprising a plurality of active areas and a distributed driver comprising distributed drive transistors D1 and D2 distributed as a plurality of elements driving respective sections D3.sub.1 to D3.sub.n of the GaN FET D3;

(9) FIG. 8 shows schematically another view of the physical layout of a device structure comprising the power switch of FIG. 7, showing source, drain and gate interconnect metallization layers of the GaN FET D3 comprising a metal Redistribution Layer (RDL), with respective source and gate connections to corresponding elements of the distributed the pull-up driver D1 and pull-down driver D2;

(10) FIG. 9 shows an enlarged view of part of FIG. 8, representing part of the source, drain and gate interconnect metallization with interconnections to the respective elements of the pull-up and pull-down driver transistors; and

(11) FIG. 10 shows a schematic cross-sectional view of some parts of FIG. 9, through line B-B of FIG. 9.

(12) The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, of preferred embodiments of the invention, which description is by way of example only.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(13) Embodiments of the present invention provide devices and systems comprising distributed driver circuitry for large area GaN power transistors. Large GaN transistors may be arranged as blocks or sections, for example as described in the Applicant's related International Patent Application No. PCT/CA2014/000762 (Publication No. 2015061881), entitled Fault Tolerant Design for Large Area Nitride Semiconductor Devices, filed Oct. 28, 2014, which claims priority from U.S. Patent Application No. 61/896,871 filed Oct. 29, 2013. The large area GaN transistor disclosed therein comprises a plurality of transistor elements comprising transistor islands that are arranged as an array, in rows and columns. For example, transistor elements in each row are connected in parallel using conductive tracks, preferably using low inductance metal straps, e.g. relatively thick layers of copper RDL (Cu RDL), which form source, drain and gate interconnects running in a row-wise direction, to provide a plurality of transistor sections. Then, the row-wise transistor sections of the GaN transistor are connected in parallel with busses running in a column-wise direction.

(14) Embodiments of a switching system comprising a large area E-mode GaN transistor, driven by an integrated on-chip driver and discrete pre-driver, are disclosed for example, in the above referenced PCT International application No. PCT/CA2015/00168 (Publication No. WO2015135072).

(15) Referring to the circuit schematic of FIG. 3 (Prior Art), a switching system 100 comprises a large area GaN FET D3 with an integrated on-chip driver 101, comprising two smaller GaN FETs, D1 and D2. The large area GaN FET D3 is arranged as a plurality of sections D3.sub.1 to D3.sub.n. In this example, n=3. The on-chip driver 101 is centralized and comprises driver transistors D1 (pull-up) and D2 (pull-down), having respective gate inputs GH and GL. The centralized driver circuit 101 is placed on the GaN substrate adjacent the large area GaN FET D3. When the driver circuit 101, comprising driver transistors D1 (high-side/pull-up) and D2 (low-side/pull-down), is coupled to the plurality of sections of the large area GaN FET transistor D3, there may be significantly different lengths of interconnect tracks between the driver circuitry and the source, drain and gate connections of each section D3.sub.1 to D3.sub.n of the GaN FET D3, which can result in dissynchronous operation at higher switching speeds. As represented schematically in FIG. 3, each segment, or length, of interconnect between the driver circuitry and sections of the GaN FET D3 contribute parasitic inductances (L.sub.1, L.sub.2, L.sub.3 and L.sub.4). Different lengths of interconnect extend between the driver circuitry to each section. This results in different inductances in the gate loop of each of the transistor sections D3.sub.1 to D3.sub.n, i.e. depending on the physical location of each section in the chip layout, relative to the location of the driver circuitry. For larger area transistors, this may result in significant differences in the inductances in the return gate loop of each section of the transistor D3.

(16) FIG. 5 shows an alternative representation 100A of the circuit shown in FIG. 3, having a centralized driver, to illustrate schematically the physical layout of the interconnect tracks and parasitic inductances Lp (i.e. L.sub.1 to L.sub.4 of FIG. 3) introduced by different lengths of tracks between the driver transistor D2 of the on-chip driver 101 and each section D3.sub.1 to D3.sub.n of D3.

(17) At higher switching speeds when switching losses are the dominant loss, stray parameters differentially present in the driver internal track interconnect circuitry prevent coherent operation of the main power switch D3. This creates a differential phase action, and results in dissynchronous operation, since the timing of signals to each section becomes out of parallel. That is, the plurality of transistor sections D3.sub.1 to D3.sub.n may not turn on and off synchronously.

(18) A system 200 comprising a distributed driver arrangement 201 comprising driver transistors D1 and D2, according to an embodiment of the present invention, is shown schematically in FIG. 4, in which at least the low-side, pull-down, driver transistor D2 is distributed. That is, D2 comprises elements D2.1, D2.2, to D2.n, each driving respective sections D3.sub.1 to D3.sub.n of the large area GaN FET D3. The driver elements D2.1, D2.2, to D2.n are placed in closer physical proximity to the respective sections of D3 that they drive. In this device architecture, the on-chip layout of the driver elements, with distributed placement of the driver elements relative to respective sections of the GaN FET D3, helps to equalize lengths of interconnect tracks, which influence factors such as loop inductance and signal delays, for each section of the GaN FET D3.

(19) The distributed driver circuitry addresses the problem of dynamic unbalance. Optimum high speed operation is possible if the drivers are properly distributed such that each section D3.sub.n of the large power switch D3 has a nearly uniform driver condition. Thus, beneficially the pull-up driver D1 may also be similarly distributed, as illustrated schematically in FIG. 6, which shows a schematic physical layout where both pull-up and pull-down driver transistors D1 and D2 are distributed and placed in closer physical proximity to the respective sections D3.sub.1 to D3.sub.n of D3 that they drive.

(20) A system 200A comprising an integrated distributed driver according to the embodiment shown in FIG. 6 comprises a large area GaN transistor D3 arranged as a plurality of sections D3.sub.1 to D3.sub.n integrated with a plurality of separate driver elements comprising drive transistor sections D1.sub.n and D2.sub.n, each dedicated and sized appropriately to drive their respective sections D3.sub.n of the combined integrated device. Each individual driver element 201n, as referred to herein, is made up of two relatively small transistors, D1.sub.n and D2.sub.n, i.e., connected in series to provide a pull-up driver transistor D1.sub.n and a pull-down driver transistor D2.sub.n, the output of which is connected to drive the gate of a respective section D3.sub.n of the very large GaN power switch D3. The devices D1, D2 and D3 are E-mode GaN transistors.

(21) Preferably, the source of the pull-down small transistor D2.sub.n of the driver element is connected as closely as feasible to the intrinsic source of the respective section D3.sub.n of the large GaN transistor D3 that it is dedicated to drive.

(22) Thus, as illustrated in FIG. 6, the system 200A according to this embodiment comprises a plurality of driver elements each selectively connected to drive its appropriate section of the large GaN power switch. The driver transistors D1.sub.n and D2.sub.n are sized to provide optimum drive conditions, for each section D3.sub.n.

(23) The top transistor D1 of the driver comprises a GaN FET. The source electrode of the top side transistor D1 is connected to the output of the driver. The gate electrode of the top transistor D1 is driven from a pre-driver internally or externally provided. The bottom transistor D2 of the driver comprises a GaN FET. The drain of the bottom transistor D2 of the driver is connected to the output of the driver. The gate electrode of the bottom transistor D2 is driven from a pre-driver internally or externally provided.

(24) One of the factors which contribute to the gate to source impedance is the inductance added by the interconnection busses to the gates of driver transistor elements D1.sub.n and D2.sub.n. From comparison of FIG. 5 and FIG. 6, it will be apparent that the gate loop inductance of a centralized driver is much higher than that for the distributed driver.

(25) As represented in FIG. 6, two large power supply bus lines 202 are preferably provided for the driver elements so that many individual driver elements may be supplied with their power requirements. Electrodes are joined to form a driver output connection 204. Optionally the driver would be directly joined with no intermediate track 226 to the gate of the large power switching transistor D3.

(26) Advantageously, the output track connection 226 of the driver element which drives a section of the gate of the large GaN power switch D3 and the aforementioned track connection 224 from the source of the bottom transistor D1 of the driver are magnetically mirrored so as to reduce the loop inductance of the drive circuit. The other electrode 202 of the driver is the drain of the top transistor D1 and this is connected to an external power source Vdd.

(27) The conductive tracks, including the driver output and return conductive tracks, are provided by a suitable type of metallization layer that can provide tracks of relatively large dimensions and thicknesses. The tracks are also spaced as closely as possible within the limits of the space and within the limitations of the process parameters. The metal tracks are made as substantial as possible, i.e. metal layers having substantial thickness and line/track width to reduce inductance. Therefore, by means of proximity and sizing/layout of the interconnect tracks, the loop inductance of the driver circuitry is reduced significantly.

(28) An example of a physical layout or topology for a large area GaN FET D3 200B with on-chip distributed pull-up and pull-down driver transistors D1 and D2 is shown in FIG. 7. FIG. 7 shows schematically the physical layout of a device structure 200B comprising part of a power switch comprising a large area GaN FET D3 comprising a plurality of active areas 210 and a distributed driver 220 comprising distributed drive transistors D1 and D2 distributed as a plurality of elements D1.sub.1 to D1.sub.n and D2.sub.1 to D2.sub.n, each driving respective sections D1.sub.1 to D3.sub.n of the GaN FET D3.

(29) FIG. 8 shows schematically another view of the physical layout of a device structure 200C comprising the power switch shown in of FIG. 7, and further comprising overlying source, drain and gate interconnect metallization layers 232, 234 and 236 of the GaN FET sections D3.sub.n, comprising RDL metal, with respective source and gate connections to corresponding elements of the distributed the pull-up drivers D1.sub.n and pull-down drivers D2.sub.n.

(30) FIG. 9 shows an enlarged view of part 203 of the structure 200C shown in FIG. 8, representing part of the source, drain and gate interconnect metallization, of section D3.sub.n of GaN FET D3, which includes the Source RDL 232 and Gate RDL 236 providing low inductance interconnections to the respective elements of the pull-down and pull-up driver transistors, D1.sub.n and D2.sub.n. Also shown are parts of the drain electrodes 114, and source electrodes 12, which are interconnected to respective portions of the overlying drain metal RDL 236 and source metal RDL 232 by via/pad openings 228

(31) The physical layout also reduces the overshoot voltage drive for the separated gates of the sections of the large area GaN transistor switch.

(32) FIG. 10 shows a schematic cross-sectional view of some parts of FIG. 9, through line B-B of FIG. 9. As illustrated in the schematic cross-sectional view in FIG. 10, the driver output bus 236 may be juxtaposed above large source connected field plates 222 so as to create a larger gate-source capacitance C.sub.gs. This larger gate-source capacitance improves the Miller Ratio.

(33) The distributed inductances of the tracks, between the distributed high and pull-down transistors and the sections of the GaN switch that they drive, are preferably arranged to reduce the loop inductance of the driver output and return tracks. For example, two layer tracks are arranged in parallel, as illustrated in FIG. 4, to reduce the loop inductance, i.e. from the source of the high-side pull-up driver and the return path from source of the GaN switch, and from the drain of the low-side pull-down driver and the return path to the source of the GaN switch.

(34) By way of example, a large area GaN die may comprise a die area of 100 mm.sup.2, for example die sizes, such as, 2 mm6 mm, 10 mm10 mm, and potentially up to a full reticle size, e.g. 20 mm20 mm. An E-mode lateral GaN FET with high voltage/high current capability, e.g. 650 V/100 A, may for example have a gate width Wg of 1000 mm. Driver transistors D1 and D2 are smaller E-mode lateral GaN transistors, e.g. having gate widths of 60 mm and 30 mm, respectively (see for example, J. Roberts et al., Integrated Power Packaging (IWIPP, 2015 IEEE International Workshop on, 3-6 May 2015).

(35) It will be apparent that variations and modifications to these specific embodiments may be made to meet other processes and design aims. For example with different number of sections n of the large GaN transistor D3 and various physical arrangements for the on-chip layout of the respective elements of the driver transistors D1 and D2 relative to D3.

(36) For example, in other embodiments, not illustrated, alternative layout architectures may be used. For example, in one embodiment the driver output and return connection tracks are laid out at the same level in lateral close proximity to each other. In another embodiment, the driver output and return tracks are laid out on different levels so as to allow vertical close proximity. In yet another embodiment, multi-level metallization provides three vertical tracks, so that the output track of the driver is effectively enclosed within a pair of return tracks. The arrangement of interconnect tracks may be made at a chip level, or a packaging level, or a plating level of the die metallization, or a combination of these.

(37) Embodiments with various arrangements for the distributed driver circuitry are envisaged, in which both the driver and a pre-driver may be fully integrated on chip, or a discrete pre-driver may be used.

(38) One embodiment comprises a single driver for the entire circuit with a large driver top and bottom, using more optimized layout and routing, e.g. by locating a single driver more optimally and centrally relative to the active area of the GaN transistor switch to reduce inductance, and selecting the routing and sizing of interconnect tracks to reduce inductance, and minimize dissynchronous operation.

(39) Another embodiment comprises a distributed driver with a plurality of driver elements, each driver element serving several sections or a subset of sections of the GaN transistor switch (i.e. the driver is partially distributed).

(40) In another embodiment, both high and pull-down drivers that are distributed so each of the plurality of driver elements serves a respective one of the plurality of sections of the GaN transistor switch.

(41) In another embodiment, only the pull-down driver is distributed, while a centralized/common pull-up driver is provided. The use of a distributed pull-down driver is key to clamping down the bottom device and offers significant beneficial effect, even if the pull-up driver is not distributed.

(42) Referring to the above mentioned PCT International patent application No. PCT/CA2015/00168 (Publication No. WO2015135072), a GaN device or GaN chip is disclosed comprising a high voltage/high current GaN E-mode transistor switch D3 with on-chip integrated E-mode GaN driver transistors D1 and D2. The latter is referred to by the Applicant as a Drive Assist GaN E-mode transistor switch and the driver transistors D1 and D2 are referred to as the upper and lower drive assist transistors. When driven by an appropriately designed external driver, D1 operates to provide the drive voltage for the gate G of the GaN power switch D3 and D2 operates to clamp the gate G of D3 to the source S of D2 via the internal source-sense Kelvin connection. Moreover, the integrated upper drive assist transistor D1 assists in providing noise immunity to the gate of D3, e.g. voltage spikes coming in on the gate of D3; and the integrated lower drive assist transistor D2, assists in preventing false turn-on due to the Miller effect during a switching transition of D3. Unexpectedly, it has been observed that the integrated lower drive assist transistor D2 also helps significantly to provide noise immunity to the gate of D3, i.e. by clamping the gate of D3 to the source to hold D3 off in the presence of noise voltage spikes coming in externally on the gate or source sense lines.

(43) Effect of a Distributed Gate Driver on a Half Bridge Circuit

(44) A half-bridge circuit has to prevent against a cross-conduction which results in short circuit between the high and low rail and damage the switching transistors. In fact, a dead time exists between the on-state of the two transistors for this very purpose in a half-bridge driver. However, there are conditions when unwanted cross-conduction may occur. For example, referring to FIG. 6, if transistors D1 and D2 transition from both off to D1 on and D2 off, the rail voltage may suddenly drop on the drain of D2 and voltage is divided on the gate of this transistor. In order to make sure that this voltage does not turn on this transistor, care has to be taken to insure that the gate to source impedance is significantly smaller than the drain to source impedance.

(45) While devices and systems according to specific embodiments have been described by way of example, it will be appreciated that in other embodiments, other specific numbers of driver elements and other specific layout arrangements of sections of the large area GaN FET may be used.

(46) Although embodiments of the invention have been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and not to be taken by way of limitation, the scope of the present invention being limited only by the appended claims.