Power adjustment of in-phase and quadrature components at a coherent optical receiver

Abstract

It is disclosed an optical coherent receiver for an optical communication network. The optical coherent receiver is configured to receive a modulated optical signal and to process it for generating an in-phase component and a quadrature component. The optical coherent receiver comprises a power adjuster in turn comprising a multiplying unit and a retroactively connected digital circuit. The multiplying unit is configured to multiply the in-phase and quadrature components by in-phase and quadrature gains, respectively, thereby providing power-adjusted in-phase and quadrature components. The digital circuit is configured to compute: a common gain indicative of a sum of the powers of the power-adjusted in-phase and quadrature components; a differential gain indicative of a difference between the powers of the power-adjusted in-phase and quadrature components; and the in-phase and quadrature gains as a product and a ratio, respectively, between the common gain and the differential gain.

Claims

1. An optical coherent receiver for an optical communication network, said optical coherent receiver being configured to receive a modulated optical signal and to process said modulated optical signal for generating an in-phase component and a quadrature component, said in-phase component and said quadrature component being electrical signals, said optical coherent receiver comprising a power adjuster in turn comprising: a multiplying unit configured to multiply said in-phase component by an in-phase gain thereby providing a power-adjusted in-phase component, and to multiply said quadrature component by a quadrature gain thereby providing a power-adjusted quadrature component; and a digital circuit connected between output and input of said multiplying unit and configured to compute: a common gain indicative of a sum of a power of said power-adjusted in-phase component and a power of said power-adjusted quadrature component, and a differential gain indicative of a difference between said power of said power-adjusted in-phase component and said power of said power-adjusted quadrature component; and said in-phase gain as a product between said common gain and said differential gain, and said quadrature gain as a ratio between said common gain and said differential gain.

2. An optical coherent receiver according to claim 1, wherein it further comprises an analog-to-digital unit connected at the input of said power adjuster, said analog-to-digital unit being configured to sample said in-phase component and said quadrature component for providing N in-phase component and N quadrature component samples to said power adjuster at each clock cycle of a clock signal generated at said optical coherent receiver, N being an integer equal to or higher than 1.

3. An optical coherent receiver according to claim 2, wherein said multiplying unit is a digital unit configured to multiply said N in-phase component samples by said in-phase gain thereby providing N power-adjusted in-phase component samples, and to multiply said N quadrature component samples by said quadrature gain thereby providing N power-adjusted quadrature component samples.

4. An optical coherent receiver according to claim 1, wherein said multiplying unit is an analog unit.

5. An optical coherent receiver according to claim 4, wherein said power adjuster comprises an analog-to-digital unit connected at the output of said multiplying unit, said analog-to-digital unit being configured to sample said power-adjusted in-phase component and said power-adjusted quadrature component for providing N power-adjusted in-phase component samples and N power-adjusted quadrature component samples at each clock cycle of a clock signal generated at said optical coherent receiver, N being an integer equal to or higher than 1.

6. An optical coherent receiver according to claim 3, wherein said digital circuit comprises a computation module configured to receive said N power-adjusted in-phase component samples and said N power-adjusted quadrature component samples and to calculate a common metric according to the following equation: $c = {.Math.}_{k = 0}^{N - 1} \sqrt{{.Math. I_{k}^{} .Math.}^{2} + {.Math. Q_{k}^{} .Math.}^{2}},$ c being said common metric, I.sub.k being said N power-adjusted in-phase component samples and Q.sub.k being said N power-adjusted quadrature component samples.

7. An optical coherent receiver according to claim 3, wherein said digital circuit comprises a computation module configured to receive said N power-adjusted in-phase component samples and said N power-adjusted quadrature component samples and to calculate a common metric according to the following equation: $c = {.Math.}_{k = 0}^{N - 1} (\frac{.Math. I_{k}^{} .Math. + .Math. Q_{k}^{} .Math.}{\sqrt{2}} + (1 - \frac{1}{\sqrt{2}}) .Math. .Math. .Math. I_{k}^{} .Math. - .Math. Q_{k}^{} .Math. .Math.),$ c being said common metric, I.sub.k being said N power-adjusted in-phase component samples and Q.sub.k being said N power-adjusted quadrature component samples.

8. An optical coherent receiver according to claim 6, wherein said digital circuit further comprises a cascade of an adder, a common multiplier and a common accumulator connected at the output of said computation module, wherein: said adder is configured to calculate c2T, T being a target value that the power of said power-adjusted in-phase component and the power of said power-adjusted quadrature component should reach; said common multiplier is configured to calculate S.sub.c.Math.(c2T), S.sub.c being a common loop gain; and said common accumulator is configured to update its content (a.sub.c[n1]) by adding S.sub.c.Math.(c2T) to it, thereby providing an updated common content (a.sub.c[n]).

9. An optical coherent receiver according to claim 8, wherein said computation module is further configured to calculate a differential metric according to the following equation: $d = {.Math.}_{k = 0}^{N - 1} (.Math. I_{k}^{} .Math. - .Math. Q_{k}^{} .Math.),$ d being said differential metric, I.sub.k being said N power-adjusted in-phase component samples and Q.sub.k being said N power-adjusted quadrature component samples.

10. An optical coherent receiver according to claim 9, wherein said digital circuit further comprises a cascade of a differential multiplier and a differential accumulator connected at the output of said computation module, wherein: said differential multiplier is configured to calculate S.sub.d.Math.d, S.sub.d being a differential loop gain; and said differential accumulator is configured to update its content (a.sub.d[n1]) by adding S.sub.d.Math.d to it, thereby providing an updated differential content (a.sub.d[n]).

11. An optical coherent receiver according to claim 10, wherein said differential loop gain is lower than said common loop gain.

12. An optical coherent receiver according to claim 8, wherein said digital circuit further comprises an in-phase adder and a quadrature adder connected both to said common accumulator and to said differential accumulator, wherein: said in-phase adder is configured to provide a sum (a.sub.c[n]+a.sub.d[n]) of said updated common content (a.sub.c[n]) and said updated differential content (a.sub.d[n]); and said quadrature adder is configured to provide a difference (a.sub.c[n]a.sub.d[n]) between said updated common content (a.sub.c[n]) and said updated differential content (a.sub.d[n]).

13. An optical coherent receiver according to claim 12, wherein said digital circuit further comprises an in-phase exponential module connected between said in-phase adder and said multiplying unit and a quadrature exponential module connected between said quadrature adder and said multiplying unit, wherein: said in-phase exponential module is configured to calculate said in-phase gain as a negative exponential function of said sum; and said quadrature exponential module is configured to calculate said quadrature gain as a negative exponential function of said difference.

14. A node for a communication network comprising an optical coherent receiver, said optical coherent receiver being configured to receive a modulated optical signal and to process said modulated optical signal for generating an in-phase component and a quadrature component, said in-phase component and said quadrature component being electrical signals, said optical coherent receiver comprising a power adjuster in turn comprising: a multiplying unit configured to multiply said in-phase component by an in-phase gain thereby providing a power-adjusted in-phase component, and to multiply said quadrature component by a quadrature gain thereby providing a power-adjusted quadrature component; and a digital circuit connected between output and input of said multiplying unit and configured to compute: a common gain indicative of a sum of a power of said power-adjusted in-phase component and a power of said power-adjusted quadrature component, and a differential gain indicative of a difference between said power of said power-adjusted in-phase component and said power of said power-adjusted quadrature component; and said in-phase gain as a product between said common gain and said differential gain, and said quadrature gain as a ratio between said common gain and said differential gain.

15. A method for adjusting power of an in-phase component and a quadrature component of a modulated optical signal received at an optical coherent receiver for an optical communication network, said in-phase component and said quadrature component being electrical signals, said method comprising: multiplying said in-phase component by an in-phase gain thereby providing a power-adjusted in-phase component, and multiplying said quadrature component by a quadrature gain thereby providing a power-adjusted quadrature component; and computing: a common gain indicative of a sum of a power of said power-adjusted in-phase component and a power of said power-adjusted quadrature component, and a differential gain indicative of a difference between said power of said power-adjusted in-phase component and said power of said power-adjusted quadrature component; and said in-phase gain as a product between said common gain and said differential gain, and said quadrature gain as a ratio between said common gain and said differential gain.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention will be better understood by reading the following detailed description, given by way of example and not of limitation, to be read with reference to the accompanying drawings, wherein:

(2) FIG. 1 is a block diagram of a coherent optical receiver according to a first embodiment of the present invention;

(3) FIG. 2 is a more detailed block diagram of the power adjuster comprised in the coherent optical receiver of FIG. 1;

(4) FIG. 3 is a block diagram of a coherent optical receiver according to a second embodiment of the present invention;

(5) FIG. 4 is a more detailed block diagram of the power adjuster comprised in the coherent optical receiver of FIG. 3; and

(6) FIG. 5 is a block diagram of a coherent optical receiver according to a third embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

(7) FIG. 1 schematically shows a coherent optical receiver RX according to a first embodiment of the present invention.

(8) The coherent optical receiver RX preferably comprises an analog portion AP, an in-phase analog-to-digital converter A/D.sub.I, a quadrature analog-to-digital converter A/D.sub.Q, a power adjuster PA and a digital portion DP. The coherent optical receiver RX may comprise further modules, that are not shown in FIG. 1 and will not be described since they are not relevant to the present description.

(9) The analog portion AP preferably has an input substantially corresponding to the input of the coherent optical receiver RX, and two outputs. The analog portion AP is preferably implemented as an arrangement of optical, electrical and electro-optical components. The physical implementation of the analog portion AP will not be described in detail, since it is not relevant to the present description.

(10) Preferably, the in-phase analog-to-digital converter A/D.sub.I and the quadrature analog-to-digital converter A/D.sub.Q are connected to the outputs of the analog portion AP. The power adjuster PA preferably has two inputs and two outputs. The outputs of the in-phase analog-to-digital converter A/D.sub.I and the quadrature analog-to-digital converter A/D.sub.Q are preferably connected to the inputs of the power adjuster PA. The digital portion DP has two inputs, which are preferably connected to the outputs of the power adjuster PA.

(11) When a modulated optical signal s(t)=A cos(2ft-0) is received at the input of the optical coherent receiver RX, the analog portion AP preferably processes it for generating an in-phase component I of the modulated optical signal s(t) and a quadrature component Q of the modulated optical signal s(t). Both the in-phase component I and the quadrature component Q output by the analog portion AP are preferably in the form of analog electrical signals. The operation of the analog portion AP will not be described in further detail, since it is not relevant to the present description.

(12) Then, according to this first embodiment, the in-phase analog-to-digital converter A/D.sub.I preferably samples the in-phase component I, thereby generating a sequence of in-phase component samples I.sub.k. Substantially at the same time, the quadrature analog-to-digital converter A/D.sub.Q preferably samples the quadrature component Q, thereby generating a sequence of quadrature component samples Q.sub.k.

(13) Preferably, the power adjuster PA receives the in-phase component samples I.sub.k and multiplies them by an in-phase gain G.sub.I, thereby providing corresponding power-adjusted in-phase component samples I.sub.k at its output. Substantially at the same time, the power adjuster PA receives the quadrature component samples Q.sub.k and multiplies them by a quadrature gain G.sub.Q, thereby providing corresponding power-adjusted quadrature component samples Q.sub.k at its output. Preferably, the in-phase gain G.sub.I and the quadrature gain G.sub.Q are given by the following equations:
G.sub.I=G.sub.C.Math.G.sub.D[4a]
G.sub.Q=G.sub.C/G.sub.D,[4b]
where G.sub.C is a fast-varying common gain suitable for controlling possible common variations of the powers of the in-phase component I and the quadrature component Q, whereas G.sub.D is a slow-varying differential gain suitable for controlling possible differential variations of the powers of the in-phase component I and the quadrature component Q, as it will be described in further detail herein after. The in-phase gain G.sub.I and the quadrature gain G.sub.Q are preferably computed by the power adjuster PA based on the in-phase component samples I.sub.k and the quadrature component samples Q.sub.k, as it will be described in further detail herein after.

(14) Then, the power adjuster PA preferably forwards the power-adjusted in-phase component samples I.sub.k and power-adjusted quadrature component samples Q.sub.k to the digital portion DP, that processes them for retrieving the digital data originally transmitted. The operation of the digital portion DP depends on the type of digital modulation applied to the modulated optical signal s(t), and will not be described in further detail, since it is not relevant to the present description.

(15) With reference to FIG. 2, the power adjuster PA according to the first embodiment of the present invention will be now described in detail.

(16) The power adjuster PA preferably comprises an in-phase multiplier M.sub.I, a quadrature multiplier M.sub.Q, a computation module C, an adder S, an common multiplier M.sub.C, a differential multiplier M.sub.D, a common accumulator ACC-C, a differential accumulator ACC-D, an in-phase adder S.sub.I, a quadrature adder S.sub.Q, an in-phase exponential module P.sub.I and a quadrature exponential module P.sub.Q. All the above components are preferably digital components, and they may be implemented as an ASIC.

(17) The above components of the power adjuster PA are preferably arranged according to two partially overlapping feedback loops, the two feedback loops being configured to calculate the in-phase gain G.sub.I and the quadrature gain G.sub.Q according to the above equations [4a] and [4b].

(18) In particular, one of the inputs of the in-phase multiplier M.sub.I and one of the inputs of the quadrature multiplier M.sub.Q correspond to the inputs of the power adjuster PA. Besides, preferably, the output of the in-phase multiplier M.sub.I and the output of the quadrature multiplier M.sub.Q correspond to the outputs of the power adjuster PA.

(19) The computation module C has two inputs and two outputs. The outputs of the in-phase multiplier M.sub.I and the quadrature multiplier M.sub.Q are connected to the inputs of the computation module C. One of the outputs of the computation module C is connected to the common multiplier M.sub.C through the adder S, while the other one is directly connected to the differential multiplier M.sub.D. The common multiplier M.sub.C is preferably connected to the common accumulator ACC-C, while the differential multiplier M.sub.D is preferably connected to the differential accumulator ACC-D. The outputs of the common accumulator ACC-C and the differential accumulator ACC-D are preferably connected to the inputs of both the in-phase adder S.sub.I and the quadrature adder S.sub.Q. The in-phase adder S.sub.I is then connected to the in-phase exponential module P.sub.I, that is in turn connected at one of the inputs of the in-phase multiplier M.sub.I. Similarly, the quadrature adder S.sub.Q is connected to the quadrature exponential module P.sub.Q, that is in turn connected at one of the inputs of the quadrature multiplier M.sub.Q.

(20) The power adjuster PA further preferably comprises a clock input (not shown in the drawings) configured to receive a clock signal from a clock unit (also not shown in the drawings) comprised in the receiver RX, and to provide it to all the components of the power adjuster PA for synchronizing their operation.

(21) The functions of the various elements shown in FIG. 2 may be provided through the use of dedicated hardware, programmable hardware or a hardware capable of executing software in association with appropriate software. In particular, the functions of the various elements shown in FIG. 2 are preferably provided through the use of one or more application specific integrated circuits (ASIC) and/or one or more field programmable gate arrays (FPGA). Preferably, the functions of the various elements shown in FIG. 2 are provided through the use of a single ASIC or a single FPGA.

(22) The operation of the power adjuster PA of FIG. 2 will be now described in detail.

(23) As mentioned above, the power adjuster PA preferably receives at its inputs the in-phase component samples I.sub.k and the quadrature component samples Q.sub.k from the in-phase analog-to-digital converter A/D.sub.I and the quadrature analog-to-digital converter A/D.sub.Q, respectively. In particular, at each clock cycle of the received clock signal, the power adjuster PA preferably receives at its inputs N in-phase component samples I.sub.k and N quadrature component samples Q.sub.k, N being an integer equal to or higher than 1. The integer N is preferably equal to 128.

(24) At each clock cycle, the in-phase multiplier M.sub.I preferably multiplies the N in-phase component samples I.sub.k by an in-phase gain G.sub.I that is currently output by the in-phase exponential module P.sub.I (and that has been calculated during the previous clock cycle), thereby providing at the output of the power adjuster PA N corresponding power-adjusted in-phase component samples I.sub.k. Substantially at the same time, the quadrature multiplier M.sub.Q preferably multiplies the N quadrature component samples Q.sub.k by a quadrature gain G.sub.Q that is currently output by the quadrature exponential module P.sub.Q (and that has been calculated during the previous clock cycle), thereby providing at the output of the power adjuster PA N corresponding power-adjusted quadrature component samples Q.sub.k.

(25) The N power-adjusted in-phase component samples I.sub.k and the N power-adjusted quadrature component samples Q.sub.k are preferably received also at the computation module C. The computation module C is preferably provided with one or more storing devices suitable for storing N samples I.sub.k and N samples Q.sub.k.

(26) Then, the computation module C preferably computes a common metric c and a differential metric d. The common metric c is preferably indicative of the sum of the powers of the in-phase component I and the quadrature component Q after multiplication during the current clock cycle. On the other hand, the differential metric d is preferably indicative of the difference between the power of the in-phase component I and the power of the quadrature component Q after multiplication during the current clock cycle. In particular, the common metric c and the differential metric d are preferably computed according to the following equations:

(27) $\begin{matrix} c = {.Math.}_{k = 0}^{N - 1} \sqrt{{.Math. I_{k}^{} .Math.}^{2} + {.Math. Q_{k}^{} .Math.}^{2}} & [5 a] \\ d = {.Math.}_{k = 0}^{N - 1} (.Math. I_{k}^{} .Math. - .Math. Q_{k}^{} .Math.) . & [5 b] \end{matrix}$

(28) Then, the common metric c is forwarded to the adder S, to the common multiplier M.sub.C and then to the common accumulator ACC-C. The adder S preferably subtracts 2T from the common metric c, the common multiplier M.sub.C multiplies the result by a common loop gain S.sub.c, and the common accumulator ACC-C preferably updates its content by adding to it the result of the multiplication. T is a target value, i.e. the value that the power of the samples I.sub.k and Q.sub.k should reach when the feedback loop suitable for calculating the common gain G.sub.C reaches a steady state, as it will be described in detail herein after. The target value T may be configured and possibly changed according to the features of the digital portion DP (namely, the saturation value and granularity of the digital portion DP).

(29) Substantially at the same time, the differential metric d is forwarded to the differential multiplier M.sub.D and then to the differential accumulator ACC-D. The differential multiplier M.sub.D multiplies the result by a differential loop gain S.sub.d, and the differential accumulator ACC-D preferably updates its content by adding to it the result of the multiplication.

(30) The content a.sub.c[n] of the common accumulator ACC-C and the content a.sub.d[n] of the differential accumulator ACC-D as updated during the current clock cycle are therefore given by the two following equations:
a.sub.c[n]=a.sub.c[n1]+S.sub.c.Math.(c2t)[6a]
a.sub.d[n]=a.sub.d[n1]+S.sub.d.Math.d,[6b]
wherein a.sub.c[n1] and a.sub.d[n1] are the contents of the accumulators ACC-C and ACC-D, respectively, at the end of the previous clock cycle (i.e. before the updates performed at the current clock cycle). Basically, the accumulators ACC-C, ACC-D act as digital integrators calculating the integral of the common metric c and the differential metric d, respectively. Integrating the common metric c and the differential metric d advantageously allows smoothing the common variations and the differential variations of the components I and Q, and therefore basically provides a low-pass filtering function upon the in-phase gain G.sub.I and quadrature gain G.sub.Q.

(31) Advantageously, the values of the common loop gain S.sub.c and the differential loop gain S.sub.d may be independently selected. Preferably, they are selected so that 0<S.sub.d<S.sub.c<<1. This advantageously implies that the variation in time of the content of the differential accumulator ACC-D is much slower than the variation in time of the content of the common accumulator ACC-C.

(32) The updated contents a.sub.d[n] and a.sub.c[n] of the accumulators ACC-D and ACC-C are then forwarded to the in-phase adder S.sub.I and the quadrature adder S.sub.Q. The in-phase adder S.sub.I calculates a.sub.c[n]+a.sub.d[n], and sends the sum to the in-phase exponential module P.sub.I that calculates the in-phase gain G.sub.I according to the following equation:
G.sub.I=2.sup.a.sup.c.sup.[n]a.sup.d.sup.[n].[7a]

(33) Besides, the quadrature adder S.sub.Q calculates a.sub.c[n]a.sub.d[n], and sends the difference to the quadrature exponential module P.sub.Q that calculates the quadrature gain G.sub.Q according to the following equation:
G.sub.Q=2.sup.a.sup.c.sup.[n]+a.sup.d.sup.[n].[7b]

(34) In other words, the in-phase gain G.sub.I and the quadrature gain G.sub.Q are calculated through a non-linear mapping of the contents a.sub.d[n] and a.sub.c[n]. This basically provides a logarithmic control of the in-phase gain G.sub.I and the quadrature gain G.sub.Q.

(35) The in-phase gain G.sub.I and the quadrature gain G.sub.Q calculated according to the equations [7a] and [7b] during the current clock cycle based on the currently received N samples I.sub.k and N samples Q.sub.k will then be used for multiplying the N samples I.sub.k and the N samples Q.sub.k that will be received during the next clock cycle.

(36) The above described operation of the power adjuster PA is preferably repeated at each clock cycle.

(37) It can be noticed that the in-phase gain G.sub.I and the quadrature gain G.sub.Q calculated according to the equations [7a] and [7b] correspond to the in-phase gain G.sub.I and the quadrature gain G.sub.Q calculated according to the above equations [4a] and [4b], provided that:
G.sub.C=2.sup.a.sup.c.sup.[n][8a]
G.sub.D=2.sup.a.sup.d.sup.[n].[8b]

(38) Therefore, when the power of the in-phase component I and the quadrature component Q are substantially equal to the target value T, the common metric c is substantially equal to 2T, and therefore the output of the adder S is substantially equal to zero. Hence, the content of the common accumulator ACC-C is substantially constant (or slightly oscillating) and, as a consequence, also the common gain G.sub.C=2.sup.a.sup.c.sup.[n] is substantially constant. In other words, the feedback loop calculating the common gain is basically in its steady state. If, by way of example, the in-phase component I and the quadrature component Q undergo a common increase of their powers, the common metric c becomes higher than 2T, and accordingly the output of the adder S becomes positive. Hence, the content of the common accumulator ACC-C increases and, as a consequence, the common gain G.sub.C=2.sup.a.sup.c.sup.[n] decreases. Therefore, both the in-phase gain G.sub.I and the quadrature gain G.sub.Q are decreased by a same amount, and accordingly the power of both the components I and Q is decreased by a same amount. This mechanism continues until the steady state is reached again (i.e. the powers of I and Q become again substantially equal to T). The rate at which the common gain G.sub.C=2.sup.a.sup.c.sup.[n] evolves towards its steady state value basically depends on the common loop gain S.sub.c.

(39) On the other hand, when the power of the in-phase component I is equal to the power of the quadrature component Q, the differential metric d is substantially equal to zero. Hence, the content of the differential accumulator ACC-D is substantially constant (or slightly oscillating) and, as a consequence, also the differential gain G.sub.D=2.sup.a.sup.d.sup.[n] is substantially constant. In other words, the feedback loop calculating the differential gain is basically in its steady state. If, by way of example, the power of the in-phase component I increases relative to the power of the quadrature component Q, the differential metric d becomes positive. Hence, the content of the differential accumulator ACC-D increases and, as a consequence, the differential gain G.sub.D=2.sup.a.sup.d.sup.[n] decreases. Therefore, the in-phase gain G.sub.I is decreased by a given amount, while the quadrature gain G.sub.Q is increased by a same amount. Accordingly the power of the component I is decreased by a given amount, while the power of the component Q is increased by a same amount. This mechanism continues until the steady state is reached again (the power of I becomes equal to the power of Q). The rate at which the differential gain G.sub.D=2.sup.a.sup.d.sup.[n] evolves towards its steady state value basically depends on the differential loop gain S.sub.d.

(40) The coherent optical receiver RX described above (and, in particular, the power adjuster PA comprised therein) is advantageously capable of adjusting the powers of the in-phase component I and the quadrature component Q so as to control both their common variations and their differential variations.

(41) Indeed, the in-phase gain G.sub.I and the quadrature gain G.sub.Q calculated by the power adjuster PA advantageously comprise both a common gain G.sub.C=2.sup.a.sup.c.sup.[n] that varies in a faster way and compensates the common variations, and a differential gain G.sub.D=2.sup.a.sup.d.sup.[n] that varies in a slower way and compensates the differential variations.

(42) The common variations and the differential variations are advantageously controlled independently, since the common gain G.sub.C and the differential gain G.sub.D are calculated independently by two different feedback loops, according to two different metrics c and d.

(43) Advantageously, the adjustment rate of the common gain G.sub.C and the differential gain G.sub.D may be selected independently, by suitably choosing the common loop gain S.sub.c and the differential loop gain S.sub.d. Hence, by selecting 0<S.sub.d<S.sub.c<<1, the common gain G.sub.C will vary in a faster way (thereby compensating the faster common variations), and while the differential gain G.sub.D will vary in a slower way (thereby compensating the slower differential variations).

(44) Further, the logarithmic control of the in-phase gain G.sub.I and the quadrature gain G.sub.Q advantageously allows keeping the adjustment rates of the in-phase gain G.sub.I and the quadrature gain G.sub.Q substantially constant, independently of the power of the samples I.sub.k and Q.sub.k received at the computation module C.

(45) Further, advantageously, the power adjuster PA is very simple to implement. Indeed, the in-phase gain G.sub.I and the quadrature gain G.sub.Q are calculated using very simple components. In particular, while implementing the division G.sub.D/G.sub.C comprised in equation [4b] would require a very complex digital circuit, the digital circuit required for implementing computation of the quadrature gain G.sub.Q according to the above equations [7b] is advantageously very simple. Indeed, implementation of the equation [7b] basically requires the accumulators ACC-C, ACC-D, the quadrature adder S.sub.Q and the quadrature exponential module S.sub.Q. On the other hand, the calculation of the quadrature gain G.sub.Q according to the above equations [7b] is much faster than the calculation of the division G.sub.D/G.sub.C comprised in equation [4b]. This is very advantageous, since the calculation of the quadrature gain G.sub.Q must be performed at every clock cycle and should not introduce delay in the processing of the samples I.sub.k and Q.sub.k.

(46) According to a first variant of this first embodiment, the common metric c may be approximated, instead of using equation [5a] (that basically provides an approximation of the Euclidean norm), according to the following equation:

(47) $\begin{matrix} c = {.Math.}_{k = 0}^{N - 1} (.Math. I_{k}^{} .Math. + .Math. Q_{k}^{} .Math.) . & [5 a^{}] \end{matrix}$

(48) Equation [5a] is basically an approximation of equation [5a] based on an average of an L1 norm. This advantageously allows simplifying the structure of the computation module C, since neither square nor square root operations must be implemented.

(49) According to a second variant of this first embodiment, the common metric c may be approximated according to the following equation:

(50) $\begin{matrix} c = {.Math.}_{k = 0}^{N - 1} (\frac{.Math. I_{k}^{} .Math. + .Math. Q_{k}^{} .Math.}{\sqrt{2}} + (1 - \frac{1}{\sqrt{2}}) .Math. .Math. .Math. I_{k}^{} .Math. - .Math. Q_{k}^{} .Math. .Math.) . & [5 a^{}] \end{matrix}$

(51) Equation [5a] is basically a further approximation of equation [5a], which is more accurate than the approximation calculated according to equation [5a]. Indeed, equation [5a] is an Euclidean norm whereby points lying on a circle have a same norm. On the other hand, equation [5a] is an L1 norm, whereby points lying on a square tilted by 45 have a same norm. Further equation [5a] is a further type of norm, whereby points lying on an octagon have a same norm. Equation [5a] is a better approximation of equation [5a] than equation [5a], since an octagon approximates a circle better than a square.

(52) Even if equation [5a] is more complex than equation [5a], its implementation is still advantageously very simple, since it comprises neither square nor square root operations. In other words, equation [5a] is a trade-off between equation [5a] (that provides an exact value of the common metric c, but that is rather complex to implement) and equation [5a] (that provides a rough approximation of the common metric c, but that is very simple to implement).

(53) FIG. 3 schematically shows a coherent optical receiver RX according to a second embodiment of the present invention.

(54) The structure of the coherent optical receiver RX is similar to the structure of the coherent optical receiver RX of FIG. 1. However, differently from the coherent optical receiver RX of FIG. 1, the outputs of the analog portion AP are directly connected to a power adjuster PA. Hence, according to this second embodiment, the in-phase component I and the quadrature component Q output by the analog portion AP are provided to the power adjuster PA in an analog form.

(55) With reference now to FIG. 4, the structure of the power adjuster PA according to the second embodiment of the present invention is similar to the structure of the power adjuster PA of FIG. 2. Hence, a detailed description will not be repeated. However, differently from the power adjuster PA of FIG. 2, the in-phase multiplier M.sub.I and the quadrature multiplier M.sub.Q are analog multipliers. In addition, the power adjuster PA preferably comprises an in-phase analog-to-digital converter A/D.sub.I connected at the output of the in-phase multiplier M.sub.I and a quadrature analog-to-digital converter A/D.sub.Q connected at the output of the quadrature multiplier M.sub.Q. The other components of the power adjuster PA are digital components, similarly to the power adjuster PA according to the first embodiment of the present invention.

(56) The functions of the various elements shown in FIG. 4 (except the analog multipliers) may be provided through the use of dedicated hardware, programmable hardware or a hardware capable of executing software in association with appropriate software. In particular, the functions of the various elements shown in FIG. 4 (except the analog multipliers) are preferably provided through the use of one or more application specific integrated circuits (ASIC) and/or one or more field programmable gate arrays (FPGA) cooperating with the analog multipliers. Preferably, the functions of the various elements shown in FIG. 4 (except the analog multipliers) are provided through the use of a single ASIC or a single FPGA cooperating with the analog multipliers.

(57) The operation of the power adjuster PA of FIG. 4 will be now described in detail.

(58) As mentioned above, the power adjuster PA preferably receives at its inputs the in-phase component I and the quadrature component Q in analog form from the analog portion AP.

(59) The in-phase multiplier M.sub.I preferably multiplies the in-phase component I by an in-phase gain G.sub.I that is currently output by the in-phase exponential module P.sub.I, thereby continuously providing at its output a power-adjusted in-phase component I. Substantially at the same time, the quadrature multiplier M.sub.Q preferably continuously multiplies the quadrature component Q by a quadrature gain G.sub.Q that is currently output by the quadrature exponential module P.sub.Q, thereby continuously providing at its output a power-adjusted quadrature component Q.

(60) Then, the in-phase analog-to-digital converter A/D.sub.I preferably samples the power-adjusted in-phase component I, thereby generating a sequence of power-adjusted in-phase component samples I.sub.k. Substantially at the same time, the quadrature analog-to-digital converter A/D.sub.Q preferably samples the power-adjusted quadrature component Q, thereby generating a sequence of power-adjusted quadrature component samples Q.sub.k. In particular, at each clock cycle, N power-adjusted in-phase component samples I.sub.k and N power-adjusted quadrature component samples Q.sub.k are generated and provided at the output of the power adjuster PA, N being an integer equal to or higher than 1. The integer N is preferably equal to 128.

(61) The N power-adjusted in-phase component samples I.sub.k and the N power-adjusted quadrature component samples Q.sub.k are preferably received also at the computation module C. Subsequent processing of the N power-adjusted in-phase component samples I.sub.k and the N power-adjusted quadrature component samples Q.sub.k for computing the in-phase gain G.sub.I and quadrature gain G.sub.Q are substantially identical to the above described processing performed by the power adjuster PA according to the first embodiment of the present invention. Hence, such processing will be only briefly summarized.

(62) First of all, at each clock cycle the N power-adjusted in-phase component samples I.sub.k and the N power-adjusted quadrature component samples Q.sub.k are preferably processed by the computation module C for computing a common metric c and a differential metric d. The common metric c may be computed according to any of the above equations [5a], [5a] or [5a]. The differential metric d is preferably computed according to the above equation [5b].

(63) Then, the common metric c is forwarded to the adder S, then to the common multiplier M.sub.C and then to the common accumulator ACC-C, that uses it for updating its content according to the above equation [6a]. Substantially at the same time, the differential metric d is forwarded to the differential multiplier M.sub.D and then to the differential accumulator ACC-D, that uses it for updating its content according to the above equation [6b]. It should be noticed that, according to this second embodiment, the nominal value T used by the adder S depends on the features of the in-phase analog-to-digital converter A/D.sub.I and the quadrature analog-to-digital converter A/D.sub.Q (namely, their saturation values and their granularities).

(64) Then, the updated contents a.sub.d[n] and a.sub.c[n] of the accumulators ACC-D and ACC-C are forwarded to the in-phase adder S.sub.I and the quadrature adder S.sub.Q. The in-phase adder S.sub.I calculates a.sub.c[n]+a.sub.d[n], and sends the sum to the in-phase exponential module P.sub.I that calculates the in-phase gain G.sub.I according to the above equation [7a]. Besides, the quadrature adder S.sub.Q calculates a.sub.c[n]a.sub.d[n], and sends the difference to the quadrature exponential module P.sub.Q that calculates the quadrature gain G.sub.Q according to the above equation [7b].

(65) The in-phase gain G.sub.I and the quadrature gain G.sub.Q calculated according to the equations [7a] and [7b] during the current clock cycle based on the N currently received samples I.sub.k and Q.sub.k will then be used for multiplying the components I and Q during the next clock cycle.

(66) Therefore, while according to the first embodiment power adjustment is performed at the input of the digital portion DP, according to this second embodiment power adjustment is performed at the input of the analog-to-digital converters A/D.sub.I, A/D.sub.Q, the analog-to-digital converters A/D.sub.I, A/D.sub.Q being integrated in the power adjuster PA itself.

(67) Also the coherent optical receiver RX according to the second embodiment (and, in particular, the power adjuster PA comprised therein) is therefore advantageously capable of adjusting the powers of the in-phase component I and the quadrature component Q so as to control both their common variations and their differential variations, and substantially has the same advantages of the power adjuster PA according to the first embodiment.

(68) In addition, according to the second embodiment, the operation of the analog-to-digital converters is improved, since power adjustment of the in-phase and quadrature components is performed before they are provided at the inputs of the analog-to-digital converters.

(69) FIG. 5 schematically shows a coherent optical receiver RX according to a third embodiment of the present invention.

(70) The coherent optical receiver RX is basically a combination of the coherent optical receiver RX according to the first embodiment (FIG. 1) and the coherent optical receiver RX according to the second embodiment (FIG. 3).

(71) In particular, the coherent optical receiver RX comprises an analog portion AP, a first power adjuster PA1 connected at the output of the analog portion AP, a second power adjuster PA2 connected at the output of the first power adjuster PA1, and a digital portion DP connected at the output of the second power adjuster PA2.

(72) Preferably, the first power adjuster PA1 is similar to the power adjuster PA according to the second embodiment of the present invention (FIG. 4). In other words, the first power adjuster PA1 comprises the analog-to-digital converters A/D.sub.I, A/D.sub.Q. Further, the multipliers M.sub.I, M.sub.Q are analog devices suitable for adjusting the power of the components I and Q before they are received at the analog-to-digital converters A/D.sub.I, A/D.sub.Q. Hence, according to this third embodiment, the first power adjuster PA1 performs a first power adjusting operation for keeping the powers of the components I and Q substantially equal to a first target value T1, that depends on the features (namely, saturation value and granularity) of the analog-to-digital converters A/D.sub.I, A/D.sub.Q.

(73) On the other hand, the second power adjuster PA2 is similar to the power adjuster PA according to the first embodiment of the present invention (FIG. 2). In other words, the second power adjuster PA2 is a totally digital module suitable for further adjusting the power of the components I and Q after analog-to-digital conversion, before they are received at the digital portion DP. Hence, the second power adjuster PA2 performs a second power adjusting operation for keeping the powers of the components I and Q (after they are sampled) substantially equal to a second target value T2 that depends on the features (namely, saturation value and granularity) of the digital portion DP.

(74) Preferably, the first power adjustment may be rough, while the second power adjustment may be finer.

(75) Also according to this third embodiment, both common variations are differential variations are advantageously compensated.

Power adjustment of in-phase and quadrature components at a coherent optical receiver

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H03G3/3084

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H04L27/2096

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Abstract

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