Successive approximation sigma delta analog-to-digital converters

Abstract

An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.

Claims

1. An analog-to-digital converter comprising: a first analog-to-digital converter configured to receive an analog input signal and convert the analog input signal to a first digital signal, the first analog-to-digital converter comprising a successive approximation module, wherein the successive approximation module is configured to perform a successive approximation to generate the first digital signal; a second analog-to-digital converter configured to convert an analog output of the first-analog-to-digital converter to a second digital signal, wherein the analog output of the first analog-to-digital converter is generated based on the analog input signal, wherein the second analog-to-digital converter is a fine conversion analog-to-digital converter relative to the first analog-to-digital converter, wherein the second analog-to-digital converter performs the delta-sigma conversion process and comprises a decimation filter, and wherein the decimation filter is configured to suppress noise which reduces amplification and power consumption requirements of the first analog-to-digital converter, and perform a delta-sigma decimation process to generate the second digital signal based on the analog output of the first analog-to-digital converter; and a combination module configured to combine the first digital signal and the second digital signal to provide a resultant output signal.

2. The analog-to-digital converter of claim 1, wherein the second analog-to-digital converter comprises: a digital-to-analog converter, a subtractor configured to receive the output of the first analog-to-digital converter and an output of the digital-to-analog converter, a comparator configured to receive an output of the subtractor and a first reference voltage, wherein the comparator comprises a loop filter configured to filter the output of the subtractor, and a latch configured to receive an output of the loop filter, and wherein the decimation filter is configured to filter and perform the delta-sigma decimation process to generate the second digital signal based on an output of the latch, wherein the output of the second digital-to-analog converter is generated based on the second digital signal.

3. The analog-to-digital converter of claim 1, wherein the first analog-to-digital converter comprises: a first digital-to-analog converter, a first subtractor configured to receive a sample and hold signal and an output of the first digital-to-analog converter, and a first comparator configured to compare an output of the first subtractor with a first reference voltage, wherein the successive approximation module is configured to perform the successive approximation to generate the first digital signal based on an output of the first comparator, wherein the output of the first digital-to-analog converter is generated based on the first digital signal.

4. The analog-to-digital converter of claim 3, wherein the first digital-to-analog converter comprises a charge sharing digital-to-analog converter or a charge redistribution digital-to-analog converter configuration.

5. The analog-to-digital converter of claim 3, wherein the second analog-to-digital converter comprises: a second digital-to-analog converter, a second subtractor configured to receive the output of the first subtractor and an output of the second digital-to-analog converter, a second comparator configured to receive an output of the second subtractor and the first reference voltage, wherein the second comparator comprises a loop filter configured to filter the output of the subtractor, and a latch configured to receive an output of the loop filter, and wherein the decimation filter is configured to perform the delta-sigma decimation process to generate the second digital signal based on an output of the latch, wherein the output of the second digital-to-analog converter is generated based on the second digital signal.

6. The analog-to-digital converter of claim 5, wherein: the first analog-to-digital converter is configured to, for a plurality of cycles, generate the first digital signal based on the sample and hold signal; and the second analog-to-digital converter is configured to generate the second digital signal based on a difference between (i) the sample and hold signal and (ii) a result of a successive approximation performed subsequent to the plurality of cycles, wherein the second analog-to-digital converter does not generate the second digital signal during the plurality of cycles.

7. The analog-to-digital converter of claim 5, wherein: the first digital-to-analog converter is configured to convert a first most-significant-bit of a plurality of bits to be converted to an analog output signal; the first digital-to-analog converter comprises a first plurality of capacitors; the first plurality of capacitors of the a first digital-to-analog converter are charged by a plurality of reference voltages during a sampling phase of the analog signal; the plurality of reference voltages includes the first reference voltage; charges of the first plurality of capacitors of the first digital-to-analog converter are shared during successive approximations of a first one or more bits of the first digital signal; the second digital-to-analog converter is configured to convert a first least-significant-bit of the plurality of bits to be converted to the analog output signal; the second digital-to-analog converter comprises a second plurality of capacitors; the second plurality of capacitors of the second digital-to-analog converter are charged based on a common mode voltage during the sampling phase of the analog output signal; and the second digital-to-analog converter is configured to perform charge redistribution by connecting the second plurality of capacitors of the second digital-to-analog converter to receive the plurality of reference voltages during successive approximations of a second one or more bits of the first digital signal.

8. A method comprising: receiving an analog input signal and converting the analog input signal to a first digital signal at a first analog-to-digital converter; performing a successive approximation to generate the first digital signal via the first analog-to-digital converter; converting an analog output of the first analog-to-digital converter to a second digital signal via a second analog-to-digital converter, wherein the second analog-to-digital converter is a fine conversion analog-to-digital converter relative to the first analog-to-digital converter; suppressing noise of the second analog-to-digital converter via a decimation filter; performing a delta-sigma conversion via the second analog-to-digital converter to generate the second digital signal based on the analog output of the first analog-to-digital converter, wherein the analog output of the first digital-to-analog converter is generated based on the analog input signal; and combining the first digital signal and the second digital signal to provide a resultant output signal.

9. The method of claim 8, further comprising: receiving a sample and hold signal and an output of a first digital-to-analog converter at a first subtractor; comparing an output of the first subtractor with a first reference voltage at a first comparator, wherein the first analog-to-digital converter comprises the first subtractor, the first comparator and the first analog-to-digital converter; and performing the successive approximation to generate the first digital signal based on an output of the first comparator, wherein the output of the first digital-to-analog converter is generated based on the first digital signal.

10. The method of claim 9, further comprising: receiving the output of the first subtractor and an output of a second digital-to-analog converter at a second subtractor; receiving an output of the second subtractor and the first reference voltage at a second comparator; filter the output of the subtractor via a loop filter of the second comparator; latching an output of the loop filter via a latch of the second comparator; and performing the delta-sigma conversion process to generate the second digital signal based on an output of the latch, wherein the output of the second digital-to-analog converter is generated based on the second digital signal.

11. The method of claim 8, further comprising: converting a first most-significant-bit of a plurality of bits to be converted to an analog output signal via the first digital-to-analog converter; charging a first plurality of capacitors of the first digital-to-analog converter by a plurality of reference voltages during a sampling phase of the analog signal; sharing charges of the first plurality of capacitors of the first digital-to-analog converter during successive approximations of a first one or more bits of the first digital signal; converting a first least-significant-bit of the plurality of bits to be converted to the analog output signal via the second digital-to-analog converter; charging second plurality of capacitors of the second digital-to-analog converter based on a common mode voltage during the sampling phase of the analog output signal; and performing charge redistribution by connecting the second plurality of capacitors of the second digital-to-analog converter to receive the plurality of reference voltages during successive approximations of a second one or more bits of the first digital signal.

12. An analog-to-digital converter comprising: a digital-to-analog converter circuit configured to convert a plurality of bits of a digital signal to an analog signal; a sample and hold circuit to sample an analog input signal; a subtractor configured to subtract the analog signal from an output of the sample and hold circuit; wherein the digital-to-analog converter circuit comprises a first digital-to-analog converter configured to convert a first most-significant-bit of the plurality of bits; a second digital-to-analog converter configured to convert a first least-significant-bit of the plurality of bits, wherein the second digital-to-analog converter is a delta-sigma digital-to-analog converter; an amplifier configured to amplify an output of the digital-to-analog converter circuit; a latch configured to latch an output of the amplifier; and a successive approximation module configured to (i) receive an output of the latch, and (ii) perform successive approximations to generate the digital signal.

13. The analog-to-digital converter circuit of claim 12, wherein the amplifier is configured to amplify an output of the first digital-to-analog converter and an output of the second digital-to-analog converter.

14. The analog-to-digital converter circuit of claim 12, wherein the first digital-to-analog converter is a charge sharing digital-to-analog converter.

15. The analog-to-digital converter circuit of claim 12, wherein: the first digital-to-analog converter comprises a plurality of circuits corresponding to some of the plurality of bits; each of the plurality of circuits is configured to convert a respective one of a plurality of most-significant-bits of the plurality of bits; the plurality of most-significant-bits comprise the first most-significant-bit; the second digital-to-analog converter comprises one or more circuits corresponding to one or more of the plurality of bits; each of the one or more circuits is configured to convert a respective one of a plurality of least-significant-bits of the plurality of bits; the plurality of least-significant-bits comprise the first least-significant-bit; and the plurality of circuits do not include the one or more circuits.

16. The analog-to-digital converter circuit of claim 12, further comprising a capacitor, a switch and a NOR gate, wherein: the amplifier comprises an integrator; the capacitor is connected between an output of the integrator and a reference terminal; and the switch is connected across the capacitor and receives a control signal from the NOR gate.

17. The analog-to-digital converter circuit of claim 16, further comprising a control module, wherein: the first digital-to-analog converter comprises a first plurality of switches; the second digital-to-analog converter comprises a second plurality of switches; and the control module is configured to, based on the output of the latch, control states of the first plurality of switches and states of the second plurality of switches.

18. The analog-to-digital converter circuit of claim 16, further comprising a control module which sets an input of the NOR gate based on the output of the latch.

19. The analog-to-digital converter circuit of claim 16, further comprising a control module: the control module comprises a decimation filter; and the decimation filter is configured to suppress noise which reduces amplification and power consumption requirements of the first analog-to-digital converter.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a block schematic view of an example SAR-ADC incorporating a hybrid SAR-DAC in accordance with an embodiment of the present disclosure.

(2) FIG. 2 is a schematic view of an example of the hybrid SAR-DAC of FIG. 1.

(3) FIG. 3 illustrates an example of an analog-to-digital conversion method including a digital-to-analog conversion method which in accordance with an embodiment of the present disclosure is implemented by the SAR-ADC of FIG. 1.

(4) FIG. 4 is a block schematic view of an example of a SAR- ADC incorporating coarse and fine DACs in accordance with an embodiment of the present disclosure.

(5) FIG. 5 is a block schematic view of examples of a SAR comparator and a comparator of the SAR- ADC of FIG. 4.

(6) FIG. 6 is an example plot of SAR residual voltage ranges in accordance with an embodiment of the present disclosure.

(7) FIG. 7 is another example plot of SAR residual voltage ranges in accordance with an embodiment of the present disclosure.

(8) FIG. 8 is an example signal plot for the SAR- ADC of FIG. 4.

(9) FIG. 9 is a block schematic view of an example of a SAR- ADC incorporating a switched integrator and latch for both coarse and fine DAC conversions in accordance with an embodiment of the present disclosure.

(10) FIG. 10 illustrates another analog-to-digital conversion method in accordance with an embodiment of the present disclosure is implemented by the SAR- ADC of FIG. 9.

(11) FIG. 11 is a block schematic view of another example of a hybrid DAC including a charge-sharing (CS) charge-redistribution (CR) segmented DAC and a DAC in accordance with an embodiment of the present disclosure.

(12) FIG. 12 illustrates an example of another analog-to-digital conversion method in accordance with an embodiment of the present disclosure is implemented by the hybrid DAC of FIG. 11.

(13) FIG. 13 is a block schematic view of an example of a 4-way interleaved SAR- ADC in accordance with an embodiment of the present disclosure.

(14) FIG. 14 is an example signal plot and a timing diagram for the ADC of FIG. 13.

(15) In the drawings, reference numbers are reused to identify similar and/or identical elements.

DESCRIPTION

(16) The below disclosed examples provide different implementations of SAR-DACs. These different implementations are referred to as hybrid charge-sharing charge-redistribution SAR-DACs or simply hybrid SAR-DACs and have corresponding disclosed circuits, systems and methods. The hybrid SAR-DACs are introduced to provide area efficient SAR-ADCs due to SAR-DAC architectures that minimize substrate surface area requirements of both a DAC core and a DAC reference voltage generator. Examples of hybrid SAR-DACs are shown in FIGS. 4, 6, 9, 11 and 12.

(17) FIG. 1 shows a SAR-ADC 130 that includes a hybrid SAR-DAC 132, an amplifier 134, a latch 136 and a SAR control module 138. A combination of the amplifier 134 and the latch 136 referred to as a comparator and, in an embodiment, compares an output of the hybrid SAR-DAC 132 with, for example, a reference voltage Vref. The amplifiers disclosed herein are referred to as pre-amplifiers as the amplifiers perform amplification prior to latching and successive approximation. The SAR control module 138 is part of a feedback loop that feeds back a digital signal V.sub.DACIN. The hybrid SAR-DAC 132 receives an analog input voltage V.sub.ADCIN, the digital signal V.sub.DACIN, and a S/H phase signal .sub.SH. The hybrid SAR-DAC 132 includes a sample and hold (S/H) circuit 140, a charge-sharing (CS) DAC (CS-DAC) 142, and a charge-redistribution (CR) DAC (CR-DAC) 144. The S/H circuit 140 receives and samples the analog input voltage V.sub.ADCIN. The DACs 142, 144 perform digital-to-analog conversions, as further described below. Output of the S/H circuit 140 is provided to the CS-DAC 142. Output of the CS-DAC 142 is provided to the CR-DAC 144. Output of the CR-DAC 144 is provided to the amplifier 134.

(18) The amplifier 134 provides an amplified output across a capacitor Ccmp. The latch 136 operates based on a clock signal Clk and latches an output of the amplifier 134, which is provided to the SAR control module 138. The SAR control module 138 performs a successive approximation algorithm (or sometimes referred to as a binary search algorithm) based on the output of the latch 136 to provide a binary code, which is dependent on (i) a current bit being approximated and (ii) bits previously approximated. The SAR control module 138 provides (i) the S/H phase signal .sub.SH to the S/H circuit 140, and (ii) the digital signal V.sub.DACIN in the form of switch control signals b[1:n] to the DACs 142, 144 to control switches of bit circuits of the DACs 142, 144.

(19) FIG. 2 shows a hybrid SAR-DAC 150, which is a n-bit fully differential SAR-DAC and in one embodiment replaces the hybrid SAR-DAC 132 of FIG. 1. The SAR-DAC 150 includes DACs 152, 154, which are binary-weighted. A binary weighted DAC refers to a DAC where capacitance weighting for each bit being converted is a product of (i) 2.sup.bit#-1 and (ii) a capacitance weighting for a corresponding bit (e.g., a most significant bit for a charge sharing DAC or a least significant bit (LSB) for a charge redistribution DAC). For example, if a capacitance weighting for a LSB is 600 atto-Farad (aF), then a capacitance weighting for a second bit is 600.Math.2.sup.2-1=1200 aF, a third bit is 600.Math.2.sup.3-1=2400 aF, etc. . . . . Each of the DACs 152, 154 is binary-weighted as the value of the capacitor pair C.sub.CSm1=C.sub.CSm2 scales between the different bits (n . . . to p+1 for DAC 152 and p . . . to 1 for DAC 154) according to the law C.sub.CSm1(j)=C.sub.CSm2(j)=C0*2^(j) (or C.sub.CSm1(j)=C.sub.CSm2(j)=C0.Math.2.sup.j), where j is the bit number ranging from 1 to n. The capacitors C.sub.CSm1, C.sub.CSm2 are shared based on control signals b.sub.n, b.sub.n. The capacitors C.sub.CRp1, C.sub.CRp2 are connected to reference voltages based on control signals b.sub.n, b.sub.n. The hybrid SAR-DAC 150 includes (i) a m-bit binary weighted charge-sharing (CS) DAC (CS-DAC) 152 that resolves a first m most-significant-bits (MSBs), and (ii) a p-bit binary weighted charge-redistribution (CR) DAC (CR-DAC) 154 that resolves last p LSBs, where n=m+p and m and p are integers. In one embodiment, the operation of the SAR-DAC 150 is applied to non-binary weighted DACs.

(20) The CS-DAC 152 includes bit circuits p+1 to n, where n is the number of bits being converted. Each of the bit circuits p+1 to n includes a first capacitor C.sub.CSm1, a first pair of switches 156, a second pair of switches 158, and a second capacitor C.sub.CSm2. In one embodiment, the capacitors C.sub.CSm1, C.sub.CSm2 have the same capacitance and are connected to a ground reference 160. A first node 162 is connected to the first capacitor C.sub.CSm1 and receives a reference voltage V.sub.REFP based on a state of a first switch 164. A second node 166 is connected between one of the switches 156 and one of the switches 158. The second node 166 receives an input voltage VINP based on a state of a first input switch 168, and provides an output voltage VRP. A third node 170 is connected between a second one of the switches 156 and a second one of the switches 158. The third node 170 receives an input voltage VINN based on a state of a second input switch 172 and provides an output voltage VRN. A fourth node 173 is connected to capacitor C.sub.CSm2, and receives a reference voltage V.sub.REFN based on a state of a switch 174. In one embodiment, a difference between the input voltages VINP, VINN is the same as the input voltage V.sub.ADCIN of FIG. 1. Each of the switches 156, 158 receives a corresponding one of control signals b.sub.n, b.sub.n. Each of the switches 164, 168, 172, 174 is controlled by a S/H phase signal .sub.SH, which part of the sample and hold circuit 140 of FIG. 1. The switches 164, 174 receive reference voltages V.sub.REFP, V.sub.REFN. Two sampling capacitors CS are connected in series between nodes 166, 170. A common mode voltage VCM exists between the capacitors CS. In one embodiment, the common mode voltage VCM is predetermined and/or generated by a voltage generator and/or a control module (e.g., one of the control modules disclosed herein). Each of the bit circuits p+1 to n receives the input voltages VINP, VINN, performs a respective conversion based on corresponding ones of received control signals b.sub.n, b.sub.n from the SAR control module 138 of FIG. 1 and provides output voltages VRP, VRN.

(21) A S/H circuit 175 includes the switches 168, 172 that receive the analog input voltages VINP, VINN. The analog input voltages VINP, VINN are provided to capacitors CS, which are connected to inputs of CS-DAC 152. A first pair of switches 176 is connected in series and between (i) a first terminal connected between the switch 168 and a first one of the capacitors CS, and (ii) a second terminal connected between the switch 172 and a second one of the capacitors CS. A second pair of switches 178 is connected in series and between (i) a first terminal connected between the first one of the capacitors CS and a first input of the CS-DAC 152, and (ii) a second terminal connected between the second one of the capacitors CS and a second input of the CS-DAC 152. Terminals between the first pair of switches 176 and between the second pair of switches 178 are connected to ground. The switches 168, 172, 178 receive S/H phase signal .sub.SH. The switches 176 receive an inverted version of the S/H phase signal .sub.SH.

(22) The CR-DAC 154 is connected to the output of the CS-DAC 152 and includes bit circuits 1 to p. Each of the bit circuits 1 to p includes a first pair of switches 180, a first capacitor C.sub.CRp1, a second capacitance C.sub.CRp2, and a second pair of switches 182. The capacitors C.sub.CRp1, C.sub.CRp2 are the same capacitance, in an embodiment. The first pair of switches 180 are connected respectively between the voltage references V.sub.REFN, V.sub.REFP and the first capacitor C.sub.CRp1. The second pair of switches 182 are connected respectively between the voltage references V.sub.REFN, V.sub.REFP and the second capacitor C.sub.CRp2. Each of the switches 180, 182 in the bit circuits 1 to p receives a corresponding one of digital output bits (or control signals) b.sub.n, b.sub.n from the SAR control module 138 for the bit number associated with the bit circuit of the switches 180, 182.

(23) A first node 184 between the switches 180 and the capacitor C.sub.CRp1 receives the common mode voltage VCM based on a state of a first S/H switch 186. A second node 185 between the capacitor C.sub.CRp1 and the CS-DAC 152 provides the positive output voltage VRP. A third node 187 between the capacitor C.sub.CRp2 and a second output of the CS-DAC 152 provides the negative output voltage VRN. A fourth node 188 between the switches 182 and the second capacitor C.sub.CRp2 receives the common mode voltage VCM based on a state of switch 190. The switches 186, 190 receive the S/H phase signal .sub.SH. Each of the bit circuits 1 to p: receives the input voltages VINP, VINN; performs a respective conversion based on corresponding ones of the control signals b.sub.n, b.sub.n; and provides outputs voltages VRP, VRN.

(24) During a sampling phase, capacitor CS and CCS.sub.DAC of the CS-DAC 152 are pre-charged with input voltages VINP, VINN and reference voltages V.sub.REFP, V.sub.REFN respectively while capacitor CCR.sub.DAC of the CR-DAC 154 is pre-charged at VCM. During the sampling phase, each of the switches 164, 168, 172, 174, 186, 190 are closed and switches 156, 158, 180, 182 are open. During a first m-cycles, states of the switches 156, 158, 180, 182 change based on the control signals b.sub.n, b.sub.n and the charges are shared (additively/subtractively) in successive approximations between the capacitors CS and CCS.sub.DAC to be minimized at the end of the m-cycle conversion. Each of the m-cycles is associated with a respective successive approximation. A residual output voltage after the m-cycles is then converted in successive approximation using the CR-DAC 154. An n-bit data output of the hybrid SAR-DAC 150 provided after a last cycle n as represented by equation 1, where

(25) $\frac{\mathrm{CS}}{\mathrm{CS}+{\mathrm{CCS}}_{\mathrm{DAC}}+{\mathrm{CCR}}_{\mathrm{DAC}}}$
is the transfer function from the reference voltage to the input of the comparator.

(26) $\begin{array}{cc}\mathrm{Vr}\left(n\right)=\frac{\mathrm{CS}}{\mathrm{CS}+{\mathrm{CCS}}_{\mathrm{DAC}}+{\mathrm{CCR}}_{\mathrm{DAC}}}\left[-V_{\mathrm{IN}}+\left(\underset{i=1}{\overset{m}{.Math.}}{b}_{i+p}\frac{{\mathrm{CCS}}_i}{\mathrm{CS}}\right).Math.V_{\mathrm{REF}}+\left(\underset{i=1}{\overset{p}{.Math.}}{b}_i\frac{{\mathrm{CCR}}_i}{\mathrm{CS}}\right).Math.V_{\mathrm{REF}}\right],w\mathrm{here}\underset{i=1}{\overset{m}{.Math.}}{\mathrm{CCS}}_i={\mathrm{CCS}}_{\mathrm{DAC}},\underset{i=1}{\overset{p}{.Math.}}{\mathrm{CCR}}_i={\mathrm{CCR}}_{\mathrm{DAC}},b_i=1& \left(1\right)\end{array}$

(27) The hybrid SAR-DAC 150 uses charge-sharing capacitors for MSB transitions. Switch parasitics associated with the MSBs is a small portion of the capacitance of the hybrid SAR-DAC 150 and does not significantly impact linearity performance of the hybrid SAR-DAC 150. Reference capacitors, capacitors connected to reference voltage terminals, do not have constraints on noise/ripple during the MSBs transitions, where the noise/ripple on the reference capacitors is at a maximum. Consequently, selection restrictions of the reference capacitors is relaxed (or reduced) to reduce a required substrate surface area. Smaller reference capacitors are used due to the CS-DAC 152 converting MSBs. Since smaller capacitances are used, surface area needed for the reference capacitors is reduced. Reference capacitors (not shown in FIG. 2) are used to minimize the ripple on the reference voltages VREFP and VREFN due to the DAC activity (connecting and disconnecting the DAC capacitances C.sub.CSm1, C.sub.CSm2, C.sub.CRp1, C.sub.CRp2, etc. . . . in FIG. 2).

(28) The hybrid SAR-DAC 150 uses charge-redistribution capacitors for LSB transitions. Noise/ripple of reference voltages during LSB transitions is small and has a transfer function corresponding to comparator input nodes with a large attenuation benefit due to the charge-sharing capacitors associated with the MSBs, as indicated in equation 1. Consequently, the noise/ripple during the LSB transitions does not significantly impact linearity/noise performance of the hybrid SAR-DAC 150. Capacitors associated with the LSBs are parasitic-insensitive (switch parasitic is on the reference sides of DAC capacitors) and the LSB capacitance is therefore scaled down to a technology node limit capacitance (e.g., C.sub.min.sub._.sub.tech) or to a kT/C limit (e.g., C.sub.min.sub._.sub.noise), which allows a DAC core area to be minimized. Alignment between the CS-DAC 152 and the CR-DAC 154 is accomplished through calibration of the capacitors C.sub.CSm1, C.sub.CSm2, C.sub.CRp1, C.sub.CRp2. This calibration is performed to adjust and/or measure the values of the capacitors C.sub.CSm1, C.sub.CSm2, C.sub.CRp1, C.sub.CRp2 due to differences between preselected capacitances and actual capacitances.

(29) Referring again to FIG. 1, the SAR control module 138 includes a SAR and control logic devices for generating, for example bit control signals b.sub.n, b.sub.n, S/H phase signal .sub.SH, etc. The SAR control module 138 performs a successive approximation algorithm to generate the bit control signals b.sub.n, b.sub.n based on a clock signal Clk and an output of the latch 136. For further defined structure of the SAR control module 138 of FIG. 1 see below provided methods and below provided definition for the term module. In one embodiment, the circuits disclosed herein are operated using example methods illustrated in FIGS. 2, 7 and 14.

(30) FIG. 3 shows an example of an analog-to-digital conversion method including a digital-to-analog conversion method. Although the following operations are primarily described with respect to the implementations of FIGS. 1-2, the operations are readily modified to apply to other implementations of the present disclosure. The operations are iteratively performed. In an embodiment, and begin at 200. At 202, the S/H circuit 140 receives the analog signal VINP, VINN. The following operations 204, 206 and 208 are performed during the same (first) period of time. At 204, the S/H circuit 140 including switches 168, 172 samples and holds a voltage of the analog signal VINP, VINN. At 206, capacitors C.sub.CSm1, C.sub.CSm2 of the CS-DAC 152 are charged based on reference voltages V.sub.REFP, V.sub.REFN. At 208, capacitors C.sub.CRp1, C.sub.CRp2 of the CR-DAC 154 are charged based on the common mode voltage VCM.

(31) At 210, the hybrid DAC 150 performs a conversion for current bit during a second period of time. If a MSB of a predetermined number of MSBs is being converted, then the SAR control module 138 at 210A generates the bit control signals b[1:n] such that charges on the capacitors C.sub.CSm1, C.sub.CSm2 of CS-DAC 152 are shared by changing states of switches 156, 158. If a LSB of a predetermined number of LSBs is being converted, then the SAR control module 138 at 210B generates the bit control signals b[1:n] such that charges on the capacitors C.sub.CRp1, C.sub.CRp2 are redistributed by changing states of the switches 180, 182 to connect the capacitors C.sub.CRp1, C.sub.CRp2 to received reference voltages V.sub.REFN, V.sub.REFP.

(32) At 212, output of the hybrid SAR-DAC 132 is provided to the amplifier 134. The output is residual voltage Vr (or positive and negative output residual voltages VRP, VRN of the nodes 166, 170). At 214, the latch 136 latches the residual voltage Vr based on the clock signal Clk. At 216, the SAR control module 138 performs a successive approximation algorithm based on the clock signal Clk and latched amplified output of the latch 136. The successive approximation algorithm includes, for example, converting an analog signal into a discrete digital representation via a binary search of all possible quantization levels before finally converging upon a digital output for each conversion.

(33) At 218, the SAR control module 138 determines whether another cycle for current conversion is to be performed. If another conversion is to be performed, task 210 is performed, otherwise task 219 is performed. At 219, the SAR control module 138 outputs a digital signal representing a word converted by the SAR-ADC 130.

(34) At 220, the SAR control module 138 determines whether another conversion is to be performed. If another conversion is to be performed, task 222 is performed, otherwise the method ends at 226. At 222, a conversion count is incremented by the SAR control module 138. The method ends at 226.

(35) The above-described operations are meant to be illustrative examples; in one or more embodiments, the operations are performed sequentially, synchronously, simultaneously, continuously, during overlapping time periods or in a different order depending upon the application. Also, in one or more embodiments, one or more of the operations is not performed or skipped depending on the implementation and/or sequence of events.

(36) In addition, to providing area efficient SAR-ADCs with reduced size as compared to traditional SAR-ADCs, power efficient ADCs that consume less power than traditional ADCs are also disclosed herein. The disclosed ADCs include successive approximation delta sigma () ADCs. The ADCs are applicable to the hybrid SAR-DACs or used in other applications separate and/or independent of the hybrid SAR-DACs. The ADCs are applicable to any type of ADC, where thermal noise is a significant contributor to an effective number of bits (ENOBs) being converted.

(37) In one embodiment, a combined low power and substrate surface area efficient ADC is used on a mixed signal system-on-chip (SOC). In scaled technologies, power challenges have been addressed using SAR architectures often in combination with techniques such as redundancy and asynchronous operation and time interleaving to meet application sampling rate requirements. However, for high-resolution ADCs (e.g., greater than or equal to 10 effective number of bits (ENOB)), a traditional SAR-ADC is intrinsically energy inefficient since the SAR-ADC reuses a same low noise comparator to perform both (i) coarse conversions where little accuracy is required, and (ii) fine conversions where thermal noise is of importance. The energy inefficiency associated with a traditional SAR-ADC is addressed by the example hybrid SAR- ADCs disclosed below with respect to FIGS. 4-6.

(38) Substrate surface area associated with a SAR-ADC has been reduced in recent years with the introduction of digital DAC linearity calibration schemes that relax matching requirements allowing SAR-DAC capacitors to be scaled down to kT/C limits. In high-resolution noise-limited DAC, DAC capacitance grows 4x for every extra bit of resolution while, at the same time, a size of voltage noise/ripple on a reference voltage needs to be reduced 2 to preserve linearity. This sets difficult to meet requirements for a reference generator of a high-resolution charge-redistribution SAR-ADC, especially if no external components are used. This requires large on chip capacitors. Traditionally this issue has been addressed using (i) traditional DAC switching schemes that optimize current absorbed, or (ii) traditional DAC topologies that are more immune to reference voltage ripple (e.g., current steering or capacitive charge sharing).

(39) FIG. 4 shows an example ADC 250. The ADC 250 includes a SAR coarse ADC 252, a fine ADC 254 and a recombination module 256. The SAR coarse ADC 252 includes a S/H circuit 258, a subtractor 260, a SAR comparator 262, a SAR control module 264, and a SAR-DAC 266. The fine ADC 254 includes a subtractor 270, a comparator 272, a control module 273, a decimation filter 274, and a DAC 276. The S/H circuit 258 receives an analog input voltage LANE.sub.IN, samples the analog input voltage LANE.sub.IN, and holds the sampled voltage based on a S/H phase signal .sub.SH. The term lane as used herein refers to a signal path, bit circuit, and/or a conductor. In one embodiment, a lane has a single input and a single output or a differential input and a differential output. The subtractor 260 subtracts output of the SAR-DAC 266 from an output of the S/H circuit 258.

(40) The SAR comparator 262 compares an output of the subtractor 260 with a reference voltage Vref based on an enable signal enSAR. The SAR control module 264 performs a successive approximation algorithm and provides a digital output to the SAR-DAC 266. After a last cycle of an analog-to-digital conversion, the SAR control module 264 provides a digital output SAR.sub.OUT to the recombination module 256. In one embodiment, the S/H circuit 258, subtractor 260 and SAR-DAC 266 are replaced by one of the hybrid SAR-DACs 132, 150 of FIGS. 1 and 2. The SAR-DAC 266 or one of the hybrid SAR-DACs 132, 150 performs a digital-to-analog conversion for a predetermined number of bits (e.g., 10 bits with 9 bit resolution). In one embodiment, if one of the hybrid SAR-DACs 132, 150 is used, 4 MSBs and 6 LSBs are converted, where one of the CS-DACs 142, 152 converts the 4 MSBs and one of the CR-DACs 144, 154 converts the 6 LSBs.

(41) The subtractor 270 subtracts a residual output voltage Vr of the SAR subtractor 260 from an output of the -DAC 276. The comparator 272 compares an output of the subtractor 270 with the reference voltage Vref based on an enable signal en. The control module 273 performs a algorithm and provides a digital output to the -DAC 276 and the decimation filter 274. In one embodiment, the algorithm includes (i) providing an output of the comparator 272 directly to the DAC 276 and directly to the decimation filter 274, and (ii) tracking a number of cycles performed by the fine ADC 254 to provide a status of a conversion being performed. The decimation filter 274 filters an output of the control module 273 and provides a digital output to the recombination module 256. After a last cycle of an analog-to-digital conversion, the decimation filter 274 provides the digital output Z.sub.OUT to the recombination module 256. In one embodiment, the -DAC 276 is configured as shown in FIG. 11 and performs a digital-to-analog conversion for one or more LSBs. As an example, the one or more LSBs include a first LSB. The next 6 LSBs are converted by the SAR-DAC 266 or one of the hybrid SAR-DACs 132, 150. The recombination module 256 combines the outputs SAR.sub.OUT and .sub.OUT to provide a digital output LANE.sub.OUT (12-bit output with a 11-bit resolution).

(42) During operation, the fine ADC 254 converts the SAR residual error (V.sub.SV.sub.DAC) at an end of the conversion performed by the SAR coarse ADC 252. The SAR coarse ADC 252 periodically and/or iteratively performs multiple conversion cycles for each conversion performed by the fine ADC 254. In one embodiment, the SAR control module 264 performs multiple successive approximations until settling on a final successive approximation for one or more bits prior to the fine ADC 254 performing a conversion based on a difference between the result of the final successive approximation and an output of the DAC 276. The filtered output .sub.OUT of the fine ADC 254 is combined with the output SAR.sub.OUT of the SAR conversion performed by the SAR coarse ADC 252 to provide a final output LANE.sub.OUT. During a SAR phase, the received signal LANE.sub.IN is sampled and the SAR coarse ADC 252 performs a first N conversions, where enSAR=1 and enSD=0 for N clock periods. Subsequent to the SAR phase, a phase is performed, the error (V.sub.SV.sub.DAC) at the end of the SAR phase is fed into the fine ADC 254 and is converted for M clock periods, where enSAR=0 and enSD=1 for the M clock periods.

(43) FIG. 5 shows examples of the SAR comparator 262 and comparator 272. The SAR comparator 262 includes an amplifier 280, a first latch 282 and a first AND gate 284. The amplifier 280 (i) receives the residual voltage Vr from the subtractor 260 of FIG. 4, and (ii) compares the residual voltage Vr to a reference voltage or ground reference, as shown. The amplifier 280 receives the voltage Vr and a reference voltage from, for example, a reference terminal or ground, as shown. The amplifier 280 compares the voltage Vr to the reference voltage. An output of the amplifier 280 is connected to a capacitor Ccmp, which is connected to a ground reference. The latch 282 latches (or holds) a voltage seen across the capacitor Ccmp based on an output of the first AND gate 284 and provides the voltage as an output. The first AND gate 284 receives the enable signal enSAR and clock signal Clk. The SAR control module 264 of FIG. 4 generates the enable signal enSAR, as described above with respect to FIG. 4.

(44) The comparator 272 includes a loop filter 286, a second latch 288 and a second AND gate 290. The loop filter 286 includes and/or be implemented as an integrator and receives an output of the subtractor 270 (shown in FIG. 4). The loop filter 286 filters and/or integrates the output of the subtractor 270. The integration includes summing outputs of the subtractor 270. An output of the loop filter 286 is provided to the second latch 288, which is controlled by the second AND gate 290. The second AND gate 290 receives the enable signal en and the clock signal Clk.

(45) Referring again to FIG. 4, the SAR coarse ADC 252 is a non-binary 10-bit SAR-ADC (with 9 bit equivalent resolution). The fine ADC 254 is implemented as a single-bit first-order continuous-time incremental ADC (with a 2 over range). The SAR coarse ADC 252 and A fine ADC 254 as shown provide improved resolution over traditional SAR-ADCs due to use of both a SAR coarse ADC and a fine ADC having a 2 over range. This is shown in FIG. 6, where the fine ADC input range (or input range of the fine ADC 254) is twice the SAR quantization range (or output range of the SAR coarse ADC 252). FIG. 6 shows an example plot of SAR residual voltage ranges for a fine ADC input, SAR quantization plus SAR loop noise, and SAR quantization alone. The SAR residual voltage V.sub.SAR Residual (or Vr) is equal to V.sub.SV.sub.DAC.

(46) FIG. 7 shows an example plot of SAR voltage residual ranges for another example implementation, where the fine ADC input range (or full scale voltage V.sub.FSSD of the fine ADC 254) is greater than 3 times SAR loop noise .sub.loop. By setting the full scale voltage V.sub.FSSD greater than 3 times SAR loop noise .sub.loop, noise and power requirements permitted to be reduced.

(47) FIG. 8 shows an example signal plot illustrating cycle timing of the SAR- ADCs. A clock signal Clk, a S/H phase signal .sub.SH, a SAR (or first) enable signal enSAR, and a (or second) enable signal are shown. As shown, an analog input signal is sampled during an OFF period T.sub.TH of the clock signal Clk. Then the clock signal Clk is ON and the first enable signal enSAR is transitioned HIGH to enable the SAR comparator 262 and perform MSB conversions during a second period T.sub.SAR. As an example, this occurs for 10 clock cycles. Following the second period, the first enable signal enSAR is transitioned LOW and the second enable signal en is transitioned HIGH to enable the comparator 272. The comparator 272 is HIGH for a third period T.sub. (e.g., 8 clock cycles) to perform LSB conversions. The overall time to perform an analog-to-digital conversion, which includes a sum of the periods T.sub.TH, T.sub.SAR, T.sub. is referred to as lane period T.sub.LANE.

(48) After sampling of analog signal and a coarse SAR-ADC conversion phase (e.g., 10 clock cycles) of the SAR coarse ADC 252, a SAR residual error is converted by the fine fine ADC 254 during a fine ADC conversion phase (e.g., 8 clock cycles). The decisions (e.g., 8 decisions) performed by the comparator of the fine ADC 254 are summed with different weights before being recombined with the SAR.sub.ouT to provide a final code (e.g., the 12-bit signal LANE.sub.OUT). In one embodiment, the operation of the fine ADC 254 is equivalent to applying an 8-tap low pass finite impulse response (FIR) filter and then performing a decimation by 8.

(49) Once SAR.sub.OUT and .sub.OUT are combined, the residual error includes, in addition to sampling kT/C noise, only fine ADC 204 noise components (i.e. quantization noise, latch thermal-noise, and loop filter thermal-noise). All these components are low-pass filtered by the decimation filter 274 (shown in FIG. 4), which in one embodiment operates as a low pass FIR filter having an equivalent bandwidth approximately equal to 1/T, where T is a conversion time of the fine ADC 254. Since both quantization and latch thermal-noise are 1.sup.st order shaped, the quantization and latch thermal-noise are strongly suppressed by the FIR leaving as dominant terms the sampling kT/C noise and the input referred noise of the integrator of the fine ADC 254 with an integration time TAX. Since the integrator is inside a loop, a gain calibration is not needed and improved linearity performance is provided.

Reduced Hardware Implementation

(50) In one embodiment, the fine ADC 254 is embedded in and/or merged with the SAR coarse ADC 252 and a single comparator latch is reused to minimize hardware overhead. FIG. 9 shows a SAR-ADC 300 that includes a S/H circuit 302, a subtractor 304, a comparator static amplifier (or gain integrator (Gmint)) 306, a latch 308, a SAR- control module 312, and a SAR- DAC 314. The SAR-ADC 300 is a reduced hardware example of the SAR- ADC of FIG. 4 with reduced number of hardware components and thus reduced overall size. If a switched integrator (e.g., switched integrator 315) is used as a SAR amplifier (e.g., replaces the amplifier 280 of FIG. 5), then the switched integrator is reused as a first order loop filter of a -ADC, as provided by a combination of the gain integrator 306 and the switch 316. In one embodiment, the switch integrator 315 includes and/or functions as a combination of the gain integrator, a load capacitor Cint and/or the switch 316. When the switched integrator is reused, the load capacitor Ccmp is not reset via switch 316. In one embodiment, the SAR comparator (e.g., combination of amplifier 280 and latch 282 or combination of gain integrator 306 and latch 308) is reused for, as an example, a single bit implementation, where a single bit is converted during each clock cycle.

(51) The S/H circuit 302 receives an analog input voltage LANE.sub.IN, samples the analog input voltage LANE.sub.IN, and holds the sampled voltage based on a S/H phase signal .sub.SH. The subtractor 304 subtracts an output of the SAR- DAC 314 from an output of the S/H circuit 302. The gain integrator 306 receives an output voltage V.sub.SARRES from the subtractor 304 performs integration to provide an output across the load capacitor Cint. A transistor 316 is connected across the load capacitor Cint and receives a control input from an output of a NOR-gate 318. The NOR-gate 318 receives an enable signal en and a clock signal Clk, such that the switch is On when both the enable signal en and the clock signal Clk are low. The latch 308 latches, based on the clock signal Clk, a voltage across the load capacitor Cint and the transistor 316. The SAR- control module 312 performs a algorithm and provides signal SAR.sub.OUT to the recombination module 256. Digital output of the SAR- control module 312 is provided to the SAR- DAC 314 and a decimation filter 320. At the end of a conversion, the decimation filter 320 provides a digital output signal to the recombination module 256, which provides the signal LANE.sub.OUT (e.g., 12-bits representing analog input voltage provided by signal LANE.sub.IN). The latch 308, switch integrator 315, NOR gate 318 operate as a combined coarse/fine ADC. The SAR- DAC 314 replaces and operates similar as the SAR DAC 266 and DAC of FIG. 4.

(52) Reconfiguring a comparator static amplifier Gmint into a integrator includes stopping reset of the load capacitor Cint after a last SAR cycle (an example of which is shown in FIG. 11). In one embodiment, timing signals used for the conversion are generated using a self-timed loop technique including, for example a delay lock loop to generate timing signals, such as the S/H phase signal .sub.SH, the clock signal Clk, and/or one or more enable signals (e.g., one of the enable signals en, enSAR shown in FIGS. 4 and 9).

(53) A SAR-ADC that includes a CS-DAC (e.g., one of the CS-DACs 142, 152 of FIGS. 1-2) reduces substrate surface area (and power) requirements of a reference generator. A CS-DAC is highly insensitive to noise/ripple on voltage references since the voltage references (e.g., voltage references V.sub.REFN, V.sub.REFP of FIG. 2) are physically disconnected via switches (e.g., switches 164, 174 of FIG. 2) from the CS-DAC during a successive approximations phase, as described above. This allows for a reduction in capacitances corresponding to voltage references. The CS-DAC, however, requires a top plate switch (switches are on a comparator end of the CS-DAC 152, such as switches 156, 158 of FIG. 2) and thus is parasitic capacitance sensitive. Scaling of LSB capacitances is therefore dictated by the parasitic capacitance of a minimum size top plate switch instead of kT/C noise requirements. For deep-submicron technology systems, this results in a higher DAC core area with respect to a CR-DAC. Use of a CS-DAC in combination with a CR-DAC allows for the DAC core area to not be increased since as described above the switch parasitics associated with MSBs is a small portion of the capacitance of the hybrid SAR-DAC. A large portion of the capacitance of the hybrid SAR-DAC is associated with the CS-DAC. Capacitances associated with the LSBs, which are handled by the CR-DAC, are small. Thus, the overall capacitance of the SAR-DAC is minimized, thereby reducing DAC core area and/or corresponding substrate area.

Loop Noise Comparison

(54) A conventional SAR ADC experiences loop noise generated by a switched integrator (efficient amplifier implementation) with a settling time equal to T.sub.clk/20, where the SAR loop noise is represented by equation 2, g.sub.M,A is the transconductance of the switched integrator, T.sub.settl is settling time, T.sub.clk is, k is Boltzman constant, T is sampling time.

(55) $\begin{array}{cc}{}_{\mathrm{loop},\mathrm{SAR}}=\sqrt{\frac{2\mathrm{kT}}{g_{M,A}{T}_{\mathrm{settl}}}}=\sqrt{\frac{40\mathrm{kT}}{g_{M,A}{T}_{\mathrm{clk}}}}& \left(2\right)\end{array}$

(56) In one embodiment, the ADC architectures of FIGS. 4, 5 and/or 9 having a first order single bit g.sub.m,lpf-C type integrator circuit that experiences loop noise .sub.SD represented by equation 3, where: g.sub.M,lpf is gain associated with the integrator and low pass filter (provided by the capacitor C) of the integrator circuit;

(57) $\frac{{}^2{V}_{\mathrm{FSSD}}^2}{9M^3}$
is SD quantization noise, and

(58) $\frac{2\mathrm{KT}}{g_{M,\mathrm{lpf}}{\mathrm{MT}}_{\mathrm{clk}}}$
is loop filter thermal noise.

(59) $\begin{array}{cc}{}_{\mathrm{SD}}=\sqrt{\frac{{}^2{V}_{\mathrm{FSSD}}^2}{9M^3}+\frac{2\mathrm{KT}}{g_{M,\mathrm{lpf}}{\mathrm{MT}}_{\mathrm{clk}}}}& \left(3\right)\end{array}$
By choosing VFSSD=3.sub.loop,SAR and g.sub.M,lpf=g.sub.M,A, the SAR loop noise .sub.SD is represented by equation 4.

(60) $\begin{array}{cc}{}_{\mathrm{SD}}{}_{\mathrm{loop},\mathrm{SAR}}\sqrt{\frac{{}^2}{M^3}+\frac{1}{20M}}& \left(4\right)\end{array}$

(61) If M=4, the SAR amplifier noise is suppressed by approximately 8 decibels (dB) with a 1.5 bit increase in ENOB with 4 additional clock cycles.

Energy Efficiency

(62) A traditional SAR ADC, using a same amplifier for each SAR conversion cycle, having MSB decisions done with full noise performance, and implementing an integrator with a limited settling time T.sub.settl (e.g., T.sub.clk/20), in one embodiment, has a required amount of amplifier power represented by equation 5.

(63) $\begin{array}{cc}{P}_{\mathrm{SAR}}\frac{2\mathrm{KT}}{{}_{\mathrm{loop}}^2}{N}_{\mathrm{SAR}}& \left(5\right)\end{array}$

(64) The SAR amplifier noise for N.sub.b SAR conversion cycles of the ADC architectures of FIGS. 4-5 and/or 9 is suppressed during the phase. The SAR amplifier (e.g., the amplifier 280 of FIG. 5) is noisier and requires less power than the amplifier of the traditional SAR ADC. Loop filter noise is filtered by the decimation filter, where bandwidth (BW)=1/MT.sub.clk. In one embodiment, the power provided to the SAR amplifiers of the disclosed ADC architectures is represented by equation 6.

(65) $\begin{array}{cc}{P}_{\mathrm{SAR}\text{-}\mathrm{SD}}\frac{2\mathrm{kT}}{{}_{\mathrm{loop}}^2}\left(\frac{{}^2}{M^3}+\frac{1}{20M}\right)\left(N_b+20M\right).fwdarw.\frac{2\mathrm{kT}}{{}_{\mathrm{loop}}^2}& \left(6\right)\end{array}$

(66) for high M

(67) There is a 3 times power reduction for a same ENOB, where M=8, from the traditional SAR ADC and the disclosed ADC (or SAR- arrangement). For the same amount of noise and an example embodiment, the energy drawn by the disclosed SAR- arrangement is equal to the energy used by the traditional SAR ADC for a single SAR conversion cycle.

(68) Energy efficiency is improved by incorporating a coarse ADC and a Delta-Sigma () ADC as a fine ADC in a SAR-ADC as above-described. Energy efficiency is also improved while substrate surface area requirements are significantly reduced by using a segmented charge-sharing charge-redistribution DAC, such as that described above with respect to FIGS. 1-2.

(69) Referring again to FIG. 5, noise associated with the latches 282, 288 (referred to as latch noise Vn) exists and/or is effectively provided (i) between the amplifier 280 and the latch 282, and (ii) between the loop filter 286 and the latch 288. The latch noise Vn is added to a signal provided to the latch 282 divided by dynamic gain of the amplifier 280. The latch noise Vn is added after the loop filter 286 and is suppressed by the feedback loop provided by the -DAC 276 of FIG. 4.

(70) FIG. 10 shows an analog-to-digital conversion method. Although the following operations are primarily described with respect to the implementations of FIGS. 4-5 and 9, the operations are easily modified to apply to other implementations of the present disclosure. The operations are iteratively performed in an embodiment.

(71) The method begins at 330. At 332, an analog signal LANE.sub.IN is received. At 334, a S/H circuit (e.g., one of the S/H circuits 258, 302) receives the analog signal LANE.sub.IN.

(72) The following operations 336-341 are performed by the SAR coarse ADC 252 or the ADC 300. At 336, the subtractor 260, 304 subtracts an output of the DAC 266, 314 from a held value provided by the S/H circuit. At 337, the output Vr of the subtractor 260, 304 is compared with a reference voltage, integrated, amplified and/or latched, as described above.

(73) At 338, the control module 264, 312 executes a successive approximation algorithm based on the output of the latch 282, 308 to generate a digital approximation signal. At 339, the control module 264, 312 determines whether another cycle is to be performed for a current bit. If another cycle is to be performed, task 340 is performed, otherwise operations 341 and 342 are performed. At 340, the DAC 266, 314 performs a digital-to-analog conversion to generate an analog signal based on the digital approximation signal. Task 336 is performed subsequent to task 340. At 341, the last generated digital approximation signal is output from the control module 264, 312 to the recombination module 256.

(74) The following operations 342-346 are performed by the fine ADC 254 or the hybrid ADC 300. At 342, the subtractor 270 subtracts an output of the -DAC 276 from Vr or the subtractor 304 subtracts the output of the SAR- DAC 314 from the held value of the S/H circuit 302. At 343, the output of the subtractor 270, 304 is compared with a reference voltage, integrated, amplified and/or latched, as described above.

(75) At 344, the control module 273, 312 executes a algorithm based on the output of the latch 288, 308 to generate a second digital approximation signal. At 345, the decimation filter 274, 320 filters the output of the control module 273, 312 to generate a digital approximation signal. At 346 the control module 264, 312 determines whether another cycle is to be performed for a current bit. If another cycle is to be performed, task 347 is performed, otherwise operation 348 is performed. At 347 the -DAC 276 or SAR- DAC 314 (hybrid DAC) performs a digital-to-analog conversion of the digital approximation signal generated at 345. Task 343 is performed subsequent to task 347.

(76) At 348 the last generated digital approximation signal generated by the fine ADC 254 or the hybrid ADC 300 is output from the decimation filter 274 or the control module 312 to the recombination module 256. At 349, the recombination module 256 combines the first converted digital signal and the second converted digital signals received at 341 and 348 to generate a resultant output signal LANE.sub.OUT. As an example, the method ends at 350.

(77) The above-described operations are meant to be illustrative examples; in one or more embodiments, the operations are performed sequentially, synchronously, simultaneously, continuously, during overlapping time periods or in a different order depending upon the application. Also, in one embodiment, one or more of the operations are not performed or skipped depending on the implementation and/or sequence of events.

(78) To exploit the reduced surface area advantage of a CS-DAC in selection of voltage references while maintaining and/or minimizing the DAC core area, a segmented SAR-DAC architecture is disclosed. A detailed example of this architecture is shown in FIG. 11. FIG. 11 shows a SAR-ADC 351 that includes a S/H circuit 352, a hybrid DAC 354, a comparator static pre-amplifier 356, a latch 358, and a SAR- control module 360. The hybrid DAC 354 includes a CS-DAC 362, a CR-DAC 364 and a -DAC 366. Each bit circuit of the -DAC 366 is configured similarly to each bit circuit of the CR-DAC 364, but with different capacitance weighting, as is further described below.

(79) The S/H circuit 352 includes switches 370, 372 that receive analog input voltages LANE INP, LANE INN. The analog input voltages LANE INP, LANE INN are provided to capacitors CTH, which are connected to inputs of CS-DAC 362. A first pair of switches 374 is connected in series and between (i) a first terminal connected between the switch 370 and a first one of the capacitors CTH, and (ii) a second terminal connected between the switch 372 and a second one of the capacitors CTH. A second pair of switches 376 is connected in series and between (i) a first terminal connected between the first one of the capacitors CTH and a first input of the CS-DAC 362, and (ii) a second terminal connected between the second one of the capacitors CTH and a second input of the CS-DAC 362. Terminals between the first pair of switches 374 and between the second pair of switches 376 are connected to ground. The switches 370, 372, 376 receive S/H phase signal .sub.SH. The switches 374 receive an inverted version of the S/H phase signal .sub.SH.

(80) The CS-DAC 362 includes bit circuits 379 (e.g., bit circuits for bits b[n:p+1] or b[10:7] as shown in FIG. 2) and is configured similar to the CS-DAC 152 of FIG. 2. Each of the bit circuits 379 includes capacitors CS.sub.10, a first pair of switches 380, and a second pair of switches 382. In one embodiment, the capacitors CS.sub.10 have the same capacitance and are connected to a ground reference 384. A first node 386 is connected to one of the capacitors CS.sub.10, and receives a reference voltage V.sub.REFP based on a state of a switch 388. A second node 390 is connected between one of the switches 380 and one of the switches 382. The second node 390 receives an input voltage from one of the capacitors CTH and provides an output voltage to the CR-DAC 364. A third node 392 is connected between a second one of the switches 380 and a second one of the switches 382. The third node 392 receives an input voltage from a second one of the capacitors CTH and provides an output voltage to the CR-DAC 364. A second one of the switches 380 and a first one of the switches 382 receives control signals b.sub.SAR10. A first one of the switches 380 and a second one of the switches 382 receives inverted control signal b.sub.SAR10 represented by inverter signals on certain ones of the switches 380, 382. A fourth node 394 is connected to one of the capacitors CS.sub.10, and receives a reference voltage V.sub.REFN based on a state of a switch 396. The switches 388, 396 are respectively controlled by a S/H phase signal .sub.SH. The switches 388, 396 receive reference voltages V.sub.REFP, V.sub.REFN. Bit circuits 379 respectively receive voltages output from the S/H circuit 352 and perform a respective conversion based on corresponding ones of received control signals b.sub.SAR10, b.sub.SAR10 from the SAR-A control module 360; and provides output voltages to the comparator static pre-amplifier 356.

(81) The CR-DAC 364 is connected to the output of the CS-DAC 362 and includes bit circuits 400 and is configured similar to the CR-DAC 154 of FIG. 2. Each of the bit circuits 400 includes a first pair of switches 402, capacitors CR.sub.6, and a second pair of switches 404. In one embodiment, the capacitors CR.sub.6 have the same capacitance. The first pair of switches 402 is connected respectively between the voltage references V.sub.REFN, V.sub.REFP and one of the capacitors CR.sub.6. The second pair of switches 404 is connected respectively between the voltage references V.sub.REFN, V.sub.REFP and a second of the capacitors CR.sub.6. Each of the switches 402, 404 receives a corresponding one of control signals b.sub.SAR6, b.sub.SAR6 from the SAR-AE control module 360. As an example, the bit circuits 400 receive respective control signals for converting bits [6:1].

(82) A first node 410 between the switches 402 and a first terminal of the first one of the capacitors CR.sub.6 is connected to the ground reference 384 based on a state of a switch 412. A second node 414 connected to a second terminal of the first one of the capacitors CR.sub.6 provides a first output voltage to the -DAC 366. A third node 416 connected to a first terminal of the second one of the capacitors CR.sub.6 provides a second output voltage to the -DAC 366. A fourth node 418 between the switches 404 and a second terminal of the second one of the capacitors CR.sub.6 is connected to the ground reference 384 based on a state of switch 420. The switches 412, 420 receive the S/H phase signal .sub.SH. Each of the bit circuits 400: receives input voltages from the CS-DAC 362; performs a respective conversion based on corresponding ones of the control signals b.sub.SAR6, b.sub.SAR6; and provides output voltages to the comparator static pre-amplifier 356.

(83) The input referred thermal noise is reduced by the architecture of the -DAC 366, as described above with the ADC 254 of FIG. 4. The -DAC 366 includes one or more bit circuits (a single bit circuit 430 is shown). The bit circuit 430 is connected to the output of the CR-DAC 364 and includes a first pair of switches 432, capacitors CR.sub., and a second pair of switches 434. In one embodiment, the capacitors CR.sub. have the same capacitance. The first pair of switches 432 is connected respectively between the voltage references V.sub.REFN, V.sub.REFP and one of the capacitors CR.sub.AE. The second pair of switches 434 is connected respectively between the voltage references V.sub.REFN, V.sub.REFP and a second of the capacitors CR.sub.. Each of the switches 432, 434 receives a corresponding one of control signals b.sub., b.sub. from the SAR- control module 360. As an example, the bit circuit 430 receives a control signal for converting bit [1:0].

(84) A first node 440 between the switches 432 and a first terminal of the first one of the capacitors CR.sub. is connected to the ground reference 384 based on a state of a switch 442. A second node 444 connected to a second terminal of the first one of the capacitors CR.sub. provides a first output voltage to the -DAC 366. A third node 446 connected to a first terminal of the second one of the capacitors CR.sub. provides a second output voltage to the -DAC 366. A fourth node 448 between the switches 434 and a second terminal of the second one of the capacitors CR.sub. is connected to the ground reference 384 based on a state of switch 450. The switches 442, 450 receive the S/H phase signal .sub.SH. The bit circuit 430: receives input voltages from the CR-DAC 364; performs a respective conversion based on corresponding ones of the control signals b.sub., b.sub.; and provides output voltages to the comparator static pre-amplifier 356.

(85) The comparator static pre-amplifier 356 receives output voltages from the DACs 362, 364, 366 and performs integration to provide an output across a load capacitor Cint, as described above with respect to the integrator 306 of FIG. 9. In one embodiment, the integration includes summing a difference between the output voltages from the DACs 362, 364, 366 for a predetermined period of time. A transistor 460 is connected across the load capacitor Cint and receives a control input from an output of a NOR-gate 462. The NOR-gate 462 receives an enable signal en and a clock signal Clk. The latch 358 latches, based on the clock signal Clk, a voltage across the load capacitor Cint and the transistor 460. Although the SAR- control module 360 is shown as including a decimation filter 464, in another embodiment the decimation filter 464 is separate from the SAR- control module 360, as similarly shown in FIG. 9. The SAR- control module 360 provides: S/H phase signal .sub.SH to the S/H circuit 352 and the DACs 362, 364, 366; a digital output and signals .sub.SH, b.sub.SAR10, b.sub.SAR6, b.sub.SAR6, b.sub., b.sub. to the DACs 362, 364, 366; and signals en, Clk to the NOR gate 462. At the end of a conversion, the SAR- control module 360 provides a digital output as LANE.sub.OUT (e.g., 12-bits representing analog input voltage provided by input voltage signals LANE INP, LANE INN).

(86) The segmented architecture of the hybrid DAC 354 includes the CS-DAC 362 for a predetermined number of MSBs (e.g., 4-MSBs), the CR-DAC 364 for LSBs (e.g., 6-LSBs) and/or the -DAC 366 for one or more LSBs. In one embodiment, the -DAC 366 is not included. Switch parasitic capacitances in the CS-DAC 362 are a small portion of the DAC capacitances of the hybrid DAC 354 and do not significantly impact linearity performance. In one embodiment, the capacitances of the CR-DAC 364 are scaled down as in a conventional CR-DAC. The voltage reference noise/ripple for the LSBs is reduced by 2.sup.4 (or 2 to the power 4 or the number of MSBs). The voltage reference noise/ripple is also attenuated at an input of the corresponding comparator due to the inclusion of the capacitors CS, which are connected to the ground reference 384. As a result and as an example, for a SAR-DAC core capacitance of 300 femtoFarad (fF), capacitance of the corresponding reference lane is only 5 picoFarad (pF).

(87) FIG. 11 further includes a table including TH and DAC weights, which refer to respective capacitances of the S/H circuit 352 and DACs 362, 364, 366. Each of the weights multiplied by, a predetermined capacitance (e.g., 600 atto-farad (aF)) provides the capacitance of the corresponding capacitance. Multiple weights are provided for the DACs 362, 364 respectively and correspond to bits converted by the DACs 362, 364. For example, bit 7 of the CS-DAC 362 has the weight 37, which if multiplied by the predetermined capacitance provides the value of each of the capacitors CS.sub.10 for that bit.

(88) FIG. 12 shows an example of an analog-to-digital conversion method including a digital-to-analog conversion method. Although the following operations are primarily described with respect to the implementations of FIGS. 9 and 11, the operations are easily modified to apply to other implementations of the present disclosure. In one embodiment, the operations are iteratively performed. The method begins at 450. At 452, the S/H circuit 302 receives the analog signal LANEINP, LANEINN, which is the input differential analog signal having positive and negative potentials, as shown in FIG. 11.

(89) In one embodiment, the following operations 456, 458, 460, 462 are performed during the same (first) period of time. At 456, the S/H circuit 302 including switches 370, 372 samples and holds a voltage of the analog signal LANEINP, LANEINN. At 458, capacitors CS.sub.10 of the CS-DAC 362 are charged based on reference voltages V.sub.REFP, V.sub.REFN. At 460, capacitors CR.sub.6 of the CR-DAC 364 are charged based on the common mode voltage VCM. At 462, capacitors C of the -DAC 366 are charged based on the common mode voltage VCM.

(90) At 464, the hybrid DAC 314 or 354 performs a conversion for current bits during a second period of time. If a MSB of a predetermined number of MSBs is being converted, then the SAR- control module 360 at 464A generates the bit control signals b[1:n] such that charges on the capacitors CS.sub.10 of CS-DAC 362 are shared by changing states of switches 380, 382. If intermediary bits or one or more LSBs are being converted, then the SAR-A control module 312, 360 at 464B generates the bit control signals b[1:n] such that charges on the capacitors CR.sub.6 are redistributed by changing states of the switches 402, 404 to connect the capacitors CR.sub.6 to received reference voltages V.sub.REFN, V.sub.REFP. If a LSB of a predetermined number of LSBs is being converted, then the SAR-A control module 360 at 464C generates the bit control signals b[1:n] such that charges on the capacitors C are redistributed by changing states of the switches 432, 434 to connect the capacitors C to received reference voltages V.sub.REFN, V.sub.REFP.

(91) At 466, output of the hybrid DAC 314, 354 is provided to the amplifier 306, 356. The output is residual voltage Vr (or VRP, VRN). At 468, the latch 308, 358 latches the residual voltage Vr based on the clock signal Clk. At 470, the SAR-A control module 312, 360 performs a successive approximation algorithm or algorithm based on the clock signal Clk and latched amplified output of the latch 308, 358. The successive approximation algorithm includes, for example, converting an analog signal into a discrete digital representation via a binary search of all possible quantization levels before finally converging upon a digital output for each conversion.

(92) At 472, the SAR- control module 312, 360 determines whether another cycle for a current conversion is to be performed. If another cycle for a current conversion is to be performed, task 464 is performed, otherwise task 473 is performed. At 473, the SAR- control module 312, 360 outputs a digital signal representing a word converted by the SAR-ADC 300, 351.

(93) At 474, the SAR- control module 312, 360 determines whether another conversion is to be performed. If conversion is to be performed, task 476 is performed, otherwise the method ends at 480. At 476, a conversion count is incremented by the SAR- control module 312, 360.

(94) The above-described operations are meant to be illustrative examples; in one or more embodiments, the operations are performed sequentially, synchronously, simultaneously, continuously, during overlapping time periods or in a different order depending upon the application. Also, in one embodiment, one or more of the operations is not performed or skipped depending on the implementation and/or sequence of events.

(95) The below described examples include a 12-bit 4-way interleaved ADC, which is shown in FIG. 13. The ADC performs, as an example, 600 mega-samples per second (MS/s) conversions. Although a 12-bit 4-way (i.e. 4 lanes) interleaved ADC is described, the aspects of the present disclosure are applicable to ADCs converting a different number of bits in parallel and having a different number of lanes.

(96) FIG. 13 shows SAR- ADC 500 that includes a clock generator 502, an input buffer 504, a reference buffer 506, Lanes 1-4, a serializer and gain correction module 508 and a lane gain calibration module 510. The clock generator 502 receives a clock signal Clk at a resonant frequency fs and generates phase shifted clock signals for the lanes 1-4. The phase shifted clock signals have phases 0, 90, 180 and 270, which are provided respectively to the lanes 1-4. The input buffer 504 receives an analog input signal ADC IN and provides the analog input signal ADC IN to the lanes 1-4. The reference buffer 506 receives a bandgap signal BG and provides the bandgap signal BG to the lanes 1-4. An output of the reference buffer is provided across a reference capacitor CREF.

(97) Each of the lanes 1-4 includes a S/H circuit 512, a first multiplier 514, a first subtractor 516, an integrator 518, a second subtractor 520, a latch 522, a latch offset calibration module 524, a SAR- control module 526, and a SAR- DAC 528. The S/H circuit 512 samples the analog input voltage ADC IN. The multiplier 514 multiplies an output of the S/H circuit 512 and a pseudo-random bit sequence (PRBS) generated by a PRBS generator 530. The first subtractor 516 subtracts an output of the SAR- DAC 528 from an output of the multiplier 516. The integrator 518 integrates an output of the first subtractor 516. The second subtractor 520 subtracts an output of the latch offset calibration module 524 from an output of the integrator 518. The latch 522 latches an output of the second subtractor 520 and provides the latched output to the SAR- control module 526. The SAR-A control module 526 and the SAR- DAC 528 are configured and/or operate similarly to (i) the SAR- control module 312 and the SAR- DAC 314 of FIG. 9, and/or (ii) the SAR- control module 360 and the hybrid DAC 354 of FIG. 11.

(98) Each of the lanes 1-4 further include decimation module 530, a SAR weighted summation module 532, a SAR-SD DAC calibration module 534, a summer 536, a lane offset calibration module 538, and a second multiplier 540. The decimation module 530 filters a bit signal bsd out of the SAR- control module 526. The SAR weighted summation module 532 provides a weighted sum of the bit signals bsar received from the SAR- control module 360. The SAR-SD DAC calibration module 534 generates SAR weights, which are provided to the SAR weighted summation module 532, which performs the weighted summation based on the SAR weights. The summer 536 sums outputs of the decimation module 530 and the SAR weighted summation module 532.

(99) The lane offset calibration module 538 includes an average module 542 and a third subtractor 544. The average module 542 averages outputs of the summer 536. The third subtractor 544 subtracts the average output of the average module 542 from the summation output of the summer 536. The second multiplier 540 multiples an output of the third subtractor 544 by the PRBS to provide a digital output. Digital outputs of the lanes 1-4 are provided to the serializer and gain correction module 508. The lane gain calibration module 510 generates a selection signal. The serializer and gain correction module 508 selects output of one of the lanes 1-4 based on the selection signal and adjusts gain of the selected output to provide an ADC output signal ADC OUT. In the example shown, the ADC output signal ADC OUT is a 12-bit digital signal. The serializer and gain correction module 508 serializes the parallel outputs of the lanes 1-4 to provide a serial signal (i.e. the ADC output signal ADC OUT).

(100) The ADC architecture of FIG. 13 includes 4-way interleaved ADC lanes (i.e. lanes 1-4) driven at 25% duty-cycle for maximized input signal buffer loading. For each of the lanes 1-4 at start-up, an offset of the latch 522 is calibrated by the latch offset calibration module 524 to prevent incremental saturation of the SAR- ADC 500. Next the capacitive SAR-DAC is calibrated for linearity requirements. Finally, gain and offset mismatches among the lanes 1-4 are measured and correction coefficients are applied during operation. This is done by the lane offset calibration module 538. Slow offset mismatch variations are tracked and corrected.

(101) FIG. 14 shows an example timing diagram of the signals .sub.TH, enSAR, en. FIG. 14 further shows an example of percentages of time associated with S/H operation versus SAR- DAC operation for each of the lanes 1-4 of FIG. 13. Offset operation of the lanes is also shown, which is due to the S/H timing associated with each bit of the lanes 1-4.

(102) In this application and in one or more embodiments, including the definitions below, the term module or the term controller is replaced with the term circuit. The term module refers to, be part of, or include: an Application Specific Integrated Circuit (ASIC); a digital, analog, or mixed analog/digital discrete circuit; a digital, analog, or mixed analog/digital integrated circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor circuit (shared, dedicated, or group) that executes code; a memory circuit (shared, dedicated, or group) that stores code executed by the processor circuit; other suitable hardware components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip.