GATE-TUNABLE P-N HETEROJUNCTION DIODE, AND FABRICATION METHOD AND APPLICATION OF SAME

Abstract

A method of fabricating a diode includes forming a first semiconductor layer having a first portion and a second portion extending from the first portion on a substrate; forming first and second electrodes on the substrate, the first electrode extending over and being in contact with the first portion of the first semiconductor layer; forming an insulting film to cover the first electrode and the first portion of the first semiconductor layer; and forming a second semiconductor layer having a first portion and a second portion extending from the first portion on the substrate. The second portion of the second semiconductor layer overlapping with the second portion of the first semiconductor layer to define a vertically stacked heterojunction therewith. The first portion of the second semiconductor layer extending over and being in contact with the second electrode. Each of the first and second semiconductor layers includes an atomically thin semiconductor.

Claims

1. A method of fabricating a diode, comprising: forming a first semiconductor layer on a substrate, wherein the first semiconductor layer has a first portion and a second portion extending from the first portion; forming a first electrode and a second electrode on the substrate, wherein the first electrode extends over and is in contact with the first portion of the first semiconductor layer; forming an insulting film to cover the first electrode and the first portion of the first semiconductor layer; and forming a second semiconductor layer on the substrate, wherein the second semiconductor layer has a first portion and a second portion extending from the first portion, the second portion of the second semiconductor layer overlapping with the second portion of the first semiconductor layer to define a vertically stacked heterojunction therewith, and the first portion of the second semiconductor layer extending over and being in contact with the second electrode, wherein each of the first semiconductor layer and the second semiconductor layer comprises an atomically thin semiconductor.

2. The method of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer has a monolayer thickness.

3. The method of claim 1, wherein the first semiconductor layer is formed of a first semiconductor having a first band gap and the second semiconductor layer is formed of a second semiconductor having a second band gap and being directly stacked on and in directly contact with the first semiconductor layer to define the vertically stacked heterojunction on a substrate.

4. The method of claim 3, wherein each of the first band gap and the second band gap is greater than 0 eV;

5. The method of claim 3, wherein one of the first semiconductor layer and the second semiconductor layer is formed of an n-type semiconductor, and the other of the first semiconductor layer and the second semiconductor layer is formed of a p-type semiconductor.

6. The method of claim 5, wherein a band gap of the n-type semiconductor is larger than that of the p-type semiconductor.

7. The method of claim 5, wherein the n-type semiconductor comprises molybdenum disulphide (MoS.sub.2) flakes, and the p-type semiconductor comprises single-walled carbon nanotubes (SWCNTs).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings illustrate one or more embodiments of the invention and together with the written description, serve to explain the principles of the invention. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like elements of an embodiment.

[0056] FIG. 1 shows schematically a heterojunction diode according to one embodiment of the present invention.

[0057] FIG. 2A shows schematically a fabrication process of an s-SWCNTs/SL-MoS.sub.2 p-n heterojunction diode according to one embodiment of the present invention. (I) SL-MoS.sub.2 FET and an extra pair of electrodes are fabricated via e-beam lithography on 300 nm SiO.sub.2/Si. The Si substrate acts as a global back gate. (II) The MoS.sub.2 FET is insulated by patterning an alumina film in a liftoff process, followed by (III) transfer and patterning of the s-SWCNT network to yield the final device configuration including a top contact SL-MoS.sub.2 FET, a bottom contact s-SWCNT FET, and a p-n heterojunction.

[0058] FIG. 2B shows false-colored scanning electron microscopy (SEM) image of an s-SWCNTs/SL-MoS.sub.2 p-n heterojunction diode according to one embodiment of the present invention. Regions 122 and 131 at the top and bottom are the gold electrodes. The patterned alumina (region 125) serves as a mask for insulating a portion of the SL-MoS.sub.2 flake (region 123). Region 133 is the patterned random network of s-SWCNTs (p-type) in direct contact with the exposed part of SL-MoS.sub.2 flake (n-type) to form the p-n heterojunction diode (140).

[0059] FIG. 2C shows optical micrograph showing the s-SWCNTs/SL-MoS.sub.2 p-n heterojunction diode of FIG. 2B at a lower magnification. The dashed boundary 123 indicates the SL-MoS.sub.2 flake while the dashed rectangle 133 denotes the patterned s-SWCNT film. Electrodes 1 and 2 form the n-type SL-MoS.sub.2 FET, which is insulated by the patterned alumina film (123). Electrodes 2-3 form the p-n heterojunction while electrodes 3-4 and electrodes 4-5 form p-type s-SWCNT FETs.

[0060] FIGS. 3A-3D shows electrical properties of an s-SWCNT/SL-MoS.sub.2 p-n heterojunction device according to one embodiment of the present invention. FIG. 3A shows gate-tunable output characteristics showing the transition from a nearly insulating state at V.sub.G=70 V to a conductive state with relatively poor rectification at V.sub.G=40 V to a highly rectifying diode behavior at negative gate voltages. FIG. 3B shows transfer characteristics of the p-n heterojunction (223), showing an anti-ambipolar characteristic, which is qualitatively a superposition of the transfer characteristics of the p-type s-SWCNT FET (221) and n-type SL-MoS.sub.2 FET (222). FIG. 3C shows a forward-to-reverse current ratio (at a heterojunction bias magnitude of about 10 V) as a function of a gate bias. The labels at the top show the corresponding band diagrams for the s-SWCNT/SL-MoS.sub.2 p-n heterojunction. At a high positive gate bias, the formation of an n.sup.+-n junction implies a low rectification ratio that transitions into an n.sup.+-i junction (plateau region in the plot) with reducing V.sub.G. The rectification ratio then rises with decreasing gate bias due to the formation of a p-n heterojunction. FIG. 3D shows gate-tunable rectification using the p-n heterojunction diode. The y-axis on the left shows the input voltage while the y-axis on the right shows the output voltage across the series resistor (1 M). As a function of the gate bias, the device evolves from a non-rectifying resistor-like state at V.sub.G=10 V (241) to a diode-like rectifying state at V.sub.G=10 V (242).

[0061] FIG. 4 shows a photoresponse of an s-SWCNTs/SL-MoS.sub.2 p-n heterojunction diode according to one embodiment of the present invention. (A) Scanning photocurrent micrograph of the s-SWCNTs/SL-MoS.sub.2 p-n heterojunction device showing the outlines of the SL-MoS.sub.2 flake (outlined with a dashed line 323) and the patterned s-SWCNT film (outlined with a dashed line 333) acquired at 700 nm with 20 W power. Regions of large negative photocurrent (341) are observed in the overlapping junction region (340). The patterned alumina is indicated by a dashed line 325 while electrodes are indicated by dashed lines 321, 322 and 331, respectively. (B) A photocurrent spectrum of the s-SWCNTs/SL-MoS.sub.2 p-n heterojunction device under global illumination and zero bias conditions. The photocurrent magnitude is highest at the characteristic absorption energies of both SL-MoS.sub.2 and s-SWCNTs. (C) An output curve of the s-SWCNTs/SL-MoS.sub.2 p-n heterojunction device in the dark (361) and under global illumination at about 650 nm (362). (D) The photocurrent spectral response can be tuned with the gate voltage. With decreasing the gate voltage, the increased p-doping of the nanotubes and concomitant decreased n-doping of MoS.sub.2 leads to a lower photocurrent in the near infrared region.

[0062] FIG. 5 shows photodetection using an s-SWCNTs/SL-MoS.sub.2 p-n heterojunction device according to one embodiment of the present invention. (A) and (B) Time dependent photoresponse of the p-n heterojunction showing fast rise and decay times of about 15 s. (C) External quantum efficiency (EQE) as a function of reverse bias for the heterojunction at about 650 nm. The EQE increases linearly with reverse bias from about 0 V to about 5 V with the highest EQE of about 25% occurring at about 10 V. (D) Spectrally dependent responsivity (R) of the photodiode in linear (441) and logarithmic (442) scales. A large responsivity is observed for the absorption wavelengths of SL-MoS.sub.2 as compared to s-SWCNTs since the diode is being operated at V.sub.G=40 V (depletion mode of SL-MoS.sub.2).

[0063] FIG. 6 shows a Raman spectrum of a representative MoS.sub.2 flake. A separation of 17.7 cm.sup.1 between E.sub.2g and A.sub.1g indicates a monolayer thickness.

[0064] FIG. 7 shows normalized optical absorbance spectra of arc discharge SWCNTs. The unsorted SWCNTs (611) possess a mixture of metallic and semiconducting species as evidenced by the presence of both semiconducting (S.sub.22 and S.sub.33) and metallic (M.sub.11) peaks, while the spectrum of the sorted semiconducting SWCNTs (612) shows strong semiconducting peaks and negligible metallic peaks.

[0065] FIG. 8 shows atomic force microscopy (AFM) images of the SWCNT film. (A) Topographic image and (B) amplitude error show the random network morphology and uniform coverage of SWCNTs (scale bar=1.5 m).

[0066] FIG. 9 shows linear (811) and semi-log (812) transfer characteristics of the exemplary p-n heterojunction diode showing anti-ambipolar behavior and on/off ratio exceeding 10.sup.4.

[0067] FIG. 10 shows (A) Shockley diode equation fit to the output curve at V.sub.G=40 V, (B) the variation of n with V.sub.G shows that the diode is closest to ideal behavior at V.sub.G=40 V.

[0068] FIG. 11 shows (A) optical micrograph of a heterojunction device showing a SL-MoS.sub.2 FET top right (1020) and s-SWCNT FET bottom left (1030) according to one embodiment of the present invention, where the white dotted outline 1033 indicates the extent of the patterned SWCNT film (scale bar=10 m), (B) Zoom-in of the optical micrograph (A) representing the area scanned for spatial photocurrent mapping in FIG. 4A. The black dotted outline 1050 indicates the scanned area for spatial mapping of PL and Raman shift (scale bar=2.5 m), (C) A spatial map of the Raman shift (3100-3250 cm.sup.1) showing the bright area as the patterned SWCNT film, where no Raman signal for the SWCNTs is observed in the MoS.sub.2 contact or channel region marked by lines 1060, and the boundary 1070 indicates the extent of ALD grown alumina, and (D) A PL map of the SL-MoS.sub.2 flake at the A peak (3700-3900 cm.sup.1), where the region of increased PL intensity represents the shape of the flake as seen in the optical images and the photocurrent map of FIG. 3A, no PL signal is observed in the contact regions, indicating PL quenching by the gold, and MoS.sub.2 PL is also observed from the SL-MoS.sub.2 FET channel area, between the contacts.

[0069] FIG. 12 shows power dependence of the photocurrent of the exemplary p-n heterojunction diode under zero applied bias. The line 1110 is a linear fit to the data showing a slope of 0.73.

DETAILED DESCRIPTION OF THE INVENTION

[0070] The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

[0071] The terms used in this specification generally have their ordinary meanings in the art, within the context of the invention, and in the specific context where each term is used. Certain terms that are used to describe the invention are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner regarding the description of the invention. For convenience, certain terms may be highlighted, for example using italics and/or quotation marks. The use of highlighting has no influence on the scope and meaning of a term; the scope and meaning of a term is the same, in the same context, whether or not it is highlighted. It will be appreciated that same thing can be said in more than one way. Consequently, alternative language and synonyms may be used for any one or more of the terms discussed herein, nor is any special significance to be placed upon whether or not a term is elaborated or discussed herein. Synonyms for certain terms are provided. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms discussed herein is illustrative only, and in no way limits the scope and meaning of the invention or of any exemplified term. Likewise, the invention is not limited to various embodiments given in this specification.

[0072] It will be understood that, as used in the description herein and throughout the claims that follow, the meaning of a, an, and the includes plural reference unless the context clearly dictates otherwise. Also, it will be understood that when an element is referred to as being on another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being directly on another element, there are no intervening elements present. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0073] It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the invention.

[0074] Furthermore, relative terms, such as lower or bottom and upper or top, may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the lower side of other elements would then be oriented on upper sides of the other elements. The exemplary term lower, can therefore, encompasses both an orientation of lower and upper, depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as below or beneath other elements would then be oriented above the other elements. The exemplary terms below or beneath can, therefore, encompass both an orientation of above and below.

[0075] It will be further understood that the terms comprises and/or comprising, or includes and/or including or has and/or having, or carry and/or carrying, or contain and/or containing, or involve and/or involving, and the like are to be open-ended, i.e., to mean including but not limited to. When used in this disclosure, they specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

[0076] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0077] As used herein, around, about or approximately shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term around, about or approximately can be inferred if not expressly stated.

[0078] The description will be made as to the embodiments of the invention in conjunction with the accompanying drawings. In accordance with the purposes of this disclosure, as embodied and broadly described herein, this disclosure, in one aspect, relates to a gate-tunable p-n heterojunction diode including a vertical stacked heterojunction of two ultrathin semiconductors, and fabrication method and applications of the same. According to the invention, among other things, the key innovations are fabrication of a p-n heterojunction from atomically thin materials, and a p-n heterojunction whose electrical properties and photoresponse can be tuned by a gate voltage.

[0079] Referring to FIG. 1, a gate-tunable diode including a vertical stacked heterojunction of two ultrathin semiconductors is schematically shown according to one embodiment of the invention. In this exemplary embodiment, the diode includes a substrate 10, and a heterojunction structure having a first semiconductor layer 20 and a second semiconductor layer 30 stacked on the first semiconductor 20 to define a vertically stacked heterojunction 40 on the substrate 10. The substrate 10 has a gate layer 11 and an insulating layer 12 formed on the gate layer 11. In certain embodiments, the gate layer 11 is a silicon layer, and the insulating layer is a silicon oxide (SiO.sub.2) layer.

[0080] The first semiconductor layer 20 has a first portion 21 and a second portion 22 extending from the first portion 21, formed on the substrate 10. The second semiconductor layer 30 has a first portion 31 and a second portion 32 extending from the first portion 31, formed on the substrate 10. The second portion 32 of the second semiconductor layer 30 and the second portion 22 of the first semiconductor layer 20 overlap with one another to define the vertically stacked heterojunction 40 therewith on the substrate 10.

[0081] In one embodiment, the first semiconductor layer 20 is formed of a first semiconductor having a first band gap and the second semiconductor layer 30 is formed of a second semiconductor having a second band gap and being directly stacked on and in directly contact with the first semiconductor layer 20 to define the vertically stacked heterojunction 40 on a substrate 10. In one embodiment, each of the first band gap and the second band gap is greater than 0 eV.

[0082] In one embodiment, the first semiconductor layer 20 and/or the second semiconductor layer 30 are formed of atomically thin materials, such as nanotubes, nanofibers, or a combination thereof.

[0083] In one embodiment, one of the first semiconductor layer 20 and the second semiconductor layer 30 is formed of an n-type semiconductor, and the other of the first semiconductor layer 20 and the second semiconductor layer 30 is formed of a p-type semiconductor. The n-type semiconductor has a band gap that is larger than that of the p-type semiconductor.

[0084] Further, the diode includes a first electrode 50 and a second electrode 60 formed on the substrate 10, which are in contact with the first portion 21 of the first semiconductor layer 20 and the first portion 31 of the second semiconductor layer 30, respectively. As such, the vertically stacked heterojunction 40 is located between the first electrode 50 and the second electrode 60. In certain embodiments, the first electrode 50 and the second electrode 60 are formed of gold, silver, copper, or the like.

[0085] As shown in FIG. 1, the first semiconductor layer 20, the second first semiconductor layer, the first electrode 50 and the second electrode 60 are located on the insulating layer 12.

[0086] According to the invention, the first semiconductor layer 20 and the second semiconductor layer 30 are of ultrathin layers having a monolayer thickness. The ultrathin nature of the heterojunction allows the gate tunability of the diode electrical characteristics.

[0087] The diode can be characterized with a ratio of a forward current to a reverse current. According to the invention, the forward-to-reverse current ratio varies as a function of a gate voltage applied to the gate layer. The electrical characteristics of the diode are tunable with the applied gate voltage over a wide range of charge transport behavior ranging from insulating to rectifying with the forward-to-reverse bias current ratio exceeding 10.sup.4. As a result, the diode is capable of functioning as an insulator, a linear-response resistor, or a highly rectifying diode, in response to the applied gate voltage.

[0088] In addition, the diode has an optical response to optical illumination of light at a wavelength ranging from near-infrared wavelength to a visible wavelength. The diode has a photoresponse time that is less than about 15 s, and an external quantum efficiency (EQE) that is greater than about 25%.

[0089] In one embodiment, the gate-tunable p-n heterojunction diode uses semiconducting single-walled carbon nanotubes (s-SWCNTs) and single-layer molybdenum disulphide (SL-MoS.sub.2) as p-type and n-type semiconductors, respectively. In particular, SL-MoS.sub.2 which is n-type semiconductor is stacked below p-type semiconducting s-SWCNTs with each of them connected to gold electrodes to form a p-n heterojunction. The vertical stacking of these two direct band gap [11-13] semiconductors forms a heterojunction with electrical characteristics that can be tuned with an applied gate bias over a wide range of charge transport behavior ranging from insulating to rectifying with forward-to-reverse bias current ratios exceeding 10.sup.4. The gate tunability also allows spectral control over the photoresponse. In addition, the band gaps of the carbon nanotubes (about 0.5 eV) and MoS.sub.2 (about 1.8 eV) allow concurrent optical response at near-infrared and visible wavelengths. This heterojunction diode also responds strongly to optical irradiation with an EQE of about 25% and fast photoresponse being less than 15 s. Since SWCNTs have a diverse range of electrical properties as a function of chirality and an increasing number of atomically thin 2D nanomaterials are being isolated [14], the gate-tunable p-n heterojunction should be widely generalizable to realize diverse ultrathin, high performance electronics and optoelectronics.

[0090] In one aspect, the invention relates to a method of fabricating a diode. In one embodiment, the method comprising the steps of forming a first semiconductor layer on a substrate, wherein the first semiconductor layer has a first portion and a second portion extending from the first portion; forming a first electrode and a second electrode on the substrate, wherein the first electrode extends over and is in contact with the first portion of the first semiconductor layer; forming an insulting film to cover the first electrode and the first portion of the first semiconductor layer; and forming a second semiconductor layer on the substrate, wherein the second semiconductor layer has a first portion and a second portion extending from the first portion, the second portion of the second semiconductor layer overlapping with the second portion of the first semiconductor layer to define a vertically stacked heterojunction therewith, and the first portion of the second semiconductor layer extending over and being in contact with the second electrode.

[0091] In one embodiment, each of the first semiconductor layer and the second semiconductor layer is formed of atomically thin materials and has a monolayer thickness.

[0092] In one embodiment, the first semiconductor layer is formed of a first semiconductor having a first band gap and the second semiconductor layer is formed of a second semiconductor having a second band gap and being directly stacked on and in directly contact with the first semiconductor layer to define the vertically stacked heterojunction on a substrate.

[0093] In one embodiment, each of the first band gap and the second band gap is greater than 0 eV.

[0094] In one embodiment, one of the first semiconductor layer and the second semiconductor layer is formed of an n-type semiconductor, and the other of the first semiconductor layer and the second semiconductor layer is formed of a p-type semiconductor.

[0095] In one embodiment, the n-type semiconductor has a band gap that is larger than that of the p-type semiconductor. The n-type semiconductor comprises SL-MoS.sub.2, and the p-type semiconductor comprises s-SWCNTs.

[0096] In one aspect, the invention relates to an electronic device having at least one diode as disclosed above.

[0097] In another aspect, the invention relates to a photodetector having at least one diode as disclosed above.

[0098] Without intent to limit the scope of the invention, examples and their related results according to the embodiments of the present invention are given below. Note that titles or subtitles may be used in the examples for convenience of a reader, which in no way should limit the scope of the invention. Moreover, certain theories are proposed and disclosed herein; however, in no way they, whether they are right or wrong, should limit the scope of the invention so long as the invention is practiced according to the invention without regard for any particular theory or scheme of action.

Materials and Device Fabrication

[0099] FIG. 2A shows schematically a fabrication process of an s-SWCNTs/SL-MoS.sub.2 p-n heterojunction diode according to one exemplary embodiment of the present invention. The device fabrication begins by depositing and e-beam lithographically defining gold electrodes on SL-MoS.sub.2 flakes that are exfoliated on a 300 nm SiO.sub.2/Si wafer. (I) SL-MoS.sub.2 FET 120 and an extra pair of electrodes 131 and 132 are fabricated via e-beam lithography on the 300 nm SiO.sub.2/Si wafer 110. The MoS.sub.2 FET 120 includes a monolayer of MoS.sub.2 flakes 123 deposited on the SiO.sub.2/Si wafer 110 and a pair of electrodes 121 and 122 formed on the monolayer of MoS.sub.2 flakes 123 and the SiO.sub.2/Si wafer 110. The Si substrate 112 acts as a global back gate. (II) The MoS.sub.2 FET 120 is insulated by patterning an alumina film 125 via atomic layer deposition (ALD) in a liftoff process, followed by (III) transfer and patterning of the sorted s-SWCNT thin film 133 [22, 23] to yield the final device configuration including a top contact SL-MoS.sub.2 FET 130, a bottom contact s-SWCNT FET 120, and a p-n heterojunction 140.

[0100] FIG. 2B shows false-colored scanning electron microscopy (SEM) image of an s-SWCNTs/SL-MoS.sub.2 p-n heterojunction diode according to one embodiment of the present invention. Regions 122 and 131 at the top and bottom are the gold electrodes. The patterned alumina 125 serves as a mask for insulating a portion of the SL-MoS.sub.2 flake 123. The patterned random network of s-SWCNTs 133 (p-type) is in direct contact with the exposed part of SL-MoS.sub.2 flake 123 (n-type) to form the p-n heterojunction 140.

[0101] FIG. 2C shows optical micrograph showing the s-SWCNTs/SL-MoS.sub.2 p-n heterojunction diode of FIG. 2B at a lower magnification. The dashed boundary 123 indicates the SL-MoS.sub.2 flake while the dashed rectangle 133 denotes the patterned s-SWCNT film. Electrodes 1 and 2 form the n-type SL-MoS.sub.2 FET, which is insulated by the patterned alumina film 123. Electrodes 2-3 form the p-n heterojunction while electrodes 3-4 and electrodes 4-5 form p-type s-SWCNT FETs.

Raman Spectroscopy of MoS.SUB.2

[0102] Monolayers of MoS.sub.2 were confirmed via Raman spectroscopy. The Raman spectra were acquired using a 532 nm laser with a 100 objective (NA=0.9) in a scanning confocal microscope (WITec Alpha300 R). The separation () between E.sub.2g and A.sub.1g modes of MoS.sub.2 is a well-known parameter for identifying layer thickness in ultrathin MoS.sub.2 flakes. Typically, a value less than about 20 cm.sup.1 indicates a single layer sample [31]. FIG. 6 shows the Raman spectrum of an exemplary MoS.sub.2 flake that was fabricated into the p-n heterojunction device, where is about 17.7 cm.sup.1. A separation of 17.7 cm.sup.1 between E.sub.2g and A.sub.1g clearly indicates a monolayer thickness of the exemplary MoS.sub.2 flake.

Sorting and Deposition of Semiconducting SWCNTs

[0103] Semiconducting SWCNTs with about 99% semiconductor purity were isolated by density gradient ultracentrifugation following the procedure discussed in a previous report [22]. SWCNT thin films were prepared by vacuum filtration and transferred onto pre-patterned Au electrodes by the acetone bath transfer method as outlined in the literature [22, 30]. The semiconducting purity of the sorted SWCNTs was estimated using the optical absorbance characterization and analysis protocol developed earlier [23, 30]. FIG. 7 shows the optical absorbance spectra for as-purchased arc-discharge SWCNTs (P2, Carbon Solutions Inc.) and sorted about 99% semiconductor purity SWCNTs. The average diameter of the semiconducting SWCNTs is 1.4 nm. The unsorted SWCNTs 611 possess a mixture of metallic and semiconducting species as evidenced by the presence of both semiconducting (S.sub.22 and S.sub.33) and metallic (M.sub.11) peaks, while the spectrum of the sorted semiconducting SWCNTs 612 shows strong semiconducting peaks and negligible metallic peaks.

Device Fabrication

[0104] All devices were fabricated on 300 nm thick SiO.sub.2/Si substrates. The Si <100> wafers were purchased from Silicon Quest International. The wafers were doped n-type with As (resistivity=0.001-0.005 -cm). The MoS.sub.2 FETs were fabricated using previously reported techniques [32]. Specifically, bulk MoS.sub.2 crystals were purchased from SPI Supplies and mechanically exfoliated using scotch tape. The MoS.sub.2 flakes were identified using an optical microscope (Olympus BX 51M) and then subjected to electron-beam lithography (EBL). A two-step EBL process was adopted to fabricate Au contacts with no adhesion layer. The patterns in the first step were designed to be just short of touching the MoS.sub.2 flakes. Au (75 nm thick) is the metal in contact with the MoS.sub.2 flake. Following liftoff in acetone, the devices were further cleaned with remover PG (Microchem) at about 60 C. for about 1 hour.

[0105] A portion of the MoS.sub.2 FET including both the contacts and channel was exposed in a subsequent step of EBL. Atomic layer deposition (ALD) (Cambridge Nanotech, Savannah S100) was used to grow about 30 nm alumina at about 100 C. to insulate the MoS.sub.2 channel and contacts, thus prevent shorting following subsequent SWCNT deposition. Trimethyl aluminum (TMA) (Aldrich, 99%) was used as the precursor for ALD growth of alumina, and ultrahigh purity nitrogen (Airgas) was used as the purging gas. A single ALD cycle included a TMA pulse for about 0.015 s and a 30 s purge, followed by a H.sub.2O pulse for 0.015 s and a second 30 s purge. The growth rate was determined to be about 0.75 /cycle. A total of about 400 cycles was performed to achieve about 30 nm thickness. The oxide was lifted off in warm acetone at about 50 C. for about 1 hour. A cellulose membrane containing the semiconducting SWCNT film was then stamped onto the entire substrate and dissolved under acetone vapor as outlined in previous reports [22]. The SWCNT film was annealed in vacuum (50 mTorr) at about 200 C. for about 1 hour and then patterned with EBL using a ZEP 150 (Nippon Zeon) resist. Reactive ion etching (Samco RIE-10 NR) in an oxygen plasma atmosphere (100 mW, 15 sec, 20 sccm) was then used to etch the nanotubes. The resist was subsequently dissolved in heated (80 C) N-methyl-2-pyrrolidone for about 6 hours. The SWCNT film morphology close to the heterojunction region was characterized using atomic force microscopy (AFM), as shown in FIG. 8, where (A) topographic image and (B) amplitude error show the random network morphology and uniform coverage of SWCNTs (scale bar=1.5 m).

Device Characterization

Transfer Characteristics of the p-n Heterojunction Diode

[0106] In this exemplary embodiment, the output and transfer characteristics of the p-n heterojunction diode were measured using Keithley 2400 source meters and custom Lab View programs.

[0107] The ultrathin nature of the heterojunction allows the gate tunability of the diode electrical characteristics. FIG. 3A shows the output plots 211-215 of the p-n heterojunction diode under different gate biases V.sub.G=70 V, 40 V, 0 V, 40 V, and 80 V, respectively. The p-n heterojunction diode transitions from a nearly insulating behavior at V.sub.G=70 V to a poorly rectifying state (r.sup.2<60% for fits to the Shockley diode equation) at V.sub.G=40 V to a highly rectifying diode for V.sub.G0 V (r.sup.2>99%). The transfer plot further demonstrates the gate tunability of the current through the p-n heterojunction, as shown in FIG. 3B, where the gate voltage V.sub.G was swept at 10 V/sec in steps of 1 V in the transfer and output plots. The transfer characteristics 223 of the heterojunction can be qualitatively viewed as a superposition of the transfer plots of the p-type s-SWCNT FET 222 and n-type SL-MoS.sub.2 FET 221. However, the net current through the heterojunction is smaller than the SL-MoS.sub.2 and s-SWCNT FET transfer characteristics due to the additional resistance at the heterojunction. The transfer characteristics 223 of the heterojunction shows an unusual gate voltage dependence, which refers to as anti-ambipolar behavior. In particular, the maximum conductance occurs near V.sub.G=0, which is the opposite of conventional ambipolar behavior that shows a minimum conductance near V.sub.G=0. The current on/off ratio exceeds 10.sup.4 in the transfer plots, which is suitable for advanced logic applications. FIGS. 9A and 9B respectively show the linear transfer characteristics 811 and the semi-log transfer characteristics 812 of the exemplary p-n heterojunction diode showing anti-ambipolar behavior and on/off ratio exceeding 10.sup.4.

[0108] An important parameter in characterizing the diode characteristics is the ratio of the forward current, |I.sub.f|, to the reverse current, |I.sub.r|, at the same bias magnitude. FIG. 3C shows that |I.sub.f|/|I.sub.r| varies by over five orders of magnitude as a function of gate voltage. Between the two gate bias extremes, the s-SWCNT/SL-MoS.sub.2 heterojunction transitions from an n-n.sup.+ junction at V.sub.G=80 V to a p-n junction at V.sub.G=80 V. The large band gap of SL-MoS.sub.2 (greater than 1.8 eV) [13] compared to the s-SWCNTs (about 0.7 eV) allows electrostatic depletion of SL-MoS.sub.2 to a lightly n doped (n.sup.) or nearly intrinsic insulating state, thereby leading to |I.sub.f|/|I.sub.r| values exceeding 10.sup.4 at V.sub.G=80 V. On the other hand, the small band gap of the s-SWCNTs allows electrostatic inversion from p-doping to n-doping at large positive V.sub.G, resulting in poor |I.sub.f|/|I.sub.r| values for V.sub.G>60 V.

[0109] The diode output curves with varying gate bias (V.sub.G) were fit with the Shockley diode equation,

[00001]$.Math.I_D.Math.=.Math.I_{\mathrm{rs}}.Math..Math.\left(e^{\frac{e.Math..Math.V_D}{{\mathrm{nk}}_B.Math.T}}-1\right),$

where I.sub.D is the drain current, V.sub.D is the drain bias, I.sub.rs is the reverse saturation current at V.sub.D=0.05 V, e is the electronic charge, n is the ideality factor, k.sub.B is the Boltzmann constant, and T is the temperature of operation (about 300 K).

[0110] To further understand the gate-dependent modulation of the heterojunction I-V curves, it was fitted to the Shockley diode equation. FIG. 10 shows (A) Shockley diode equation fit to the output curve at V.sub.G=40 V, (B) the variation of n with V.sub.G shows that the diode is closest to ideal behavior at V.sub.G=40 V. The best fit to the diode curve (r.sup.2>99%) was achieved for V.sub.G values ranging from 30 to 60 V with the diode ideality factor (n) approaching closest to 1 at 40 V (FIG. 10). For other V.sub.G values, either the diode ideality factor (n) was >3 or the fits were poor (r.sup.2<60%).

[0111] The gate dependence of the diode behavior enables gate-tunable rectifier circuits, as shown in FIG. 3D, which is a unique feature of the s-SWCNT/SL-MoS.sub.2 heterojunction diode that has not been observed in conventional bulk semiconductor diodes. The p-n heterojunction diode was used as a half-wave rectifier using the circuit outlined in the inset of FIG. 3D. A 1 M resistor was used in series with the diode to limit the current. A sinusoidal wave from a waveform generator was used as the input, while the output current was measured using a pre-amplifier (1211 DL Instruments) and the output voltage as it would appear across a 1 M resistor, as shown in the inset of FIG. 3D. Time domain waveforms were captured using an oscilloscope.

Spatial Mapping of Photoluminescence and Raman Shift

[0112] A scanning confocal microscope (100 objective with NA=0.9, WiTec system) coupled to a tunable coherent white light source (NKT Photonics) was used to generate the spatially resolved photocurrent, which was converted into a voltage by a current preamplifier and recorded by either a lock-in amplifier (for imaging) or a digital sampling oscilloscope (for temporally resolved measurements). The heterojunction area was subjected to global illumination using the same apparatus with a 20 objective. The I-V characteristics under the global illumination were acquired using the same Keithley 2400 source meters and custom Lab View programs.

[0113] SL-MoS.sub.2 and s-SWCNTs both have direct band gaps [11, 12] and show signatures of bound excitonic states in their absorption spectra [2, 12]. Therefore, photocurrent is expected upon optical irradiation of the p-n heterojunctions based on these materials. Towards that end, scanning photocurrent microscopy is employed to spatially map the local photoresponse of the s-SWCNT/SL-MoS.sub.2 heterojunction device, as shown in FIG. 4A. The regions of high photocurrent intensity 341 lie in the heterojunction area 340 outlined by the SL-MoS.sub.2 flake 323 overlapping with the patterned s-SWCNT film 333. The patterned alumina is indicated by a dashed line 325 while electrodes are indicated by dashed lines 321, 322 and 331, respectively. No measurable photocurrent is observed from the non-overlapping regions of either the s-SWCNT film, SL-MoS.sub.2, or the electrical contacts, indicating that the photocurrent is generated by the vertical heterojunction 340.

[0114] Spatial Raman and photoluminescence (PL) mapping was performed on the heterojunction device. A spatial map of the Raman 2G peak (3100-3250 cm.sup.1) from SWCNTs and photoluminescence from SL-MoS.sub.2 at 3700-3900 cm.sup.1 (A peak) shows that the photocurrent arises only from the heterojunction region. It was also observed that that the PL signal was uniform in the heterojunction area of the MoS.sub.2 flake as compared to the protected/masked area as shown in FIG. 11. FIG. 11A is an optical micrograph of the heterojunction device showing a SL-MoS.sub.2 FET 1020 and s-SWCNT FET 1030, where the white dotted outline 1033 indicates the extent of the patterned SWCNT film (scale bar=10 m). FIG. 11B is a zoom-in of the optical micrograph of FIG. 11A representing the area scanned for spatial photocurrent mapping in FIG. 4A. The black dotted outline 1050 indicates the scanned area for spatial mapping of PL and Raman shift (scale bar=2.5 m). FIG. 11C is a spatial map of the Raman shift (3100-3250 cm.sup.1) showing the bright area as the patterned SWCNT film, where no Raman signal for the SWCNTs is observed in the MoS.sub.2 contact or channel region marked by lines 1060, and the boundary 1070 indicates the extent of ALD grown alumina. FIG. 11D shows a PL map of the SL-MoS.sub.2 flake at the A peak (3700-3900 cm.sup.1), where the region of increased PL intensity represents the shape of the flake as seen in the optical images and the photocurrent map of FIG. 3A, no PL signal is observed in the contact regions, indicating PL quenching by the gold, and MoS.sub.2 PL is also observed from the SL-MoS.sub.2 FET channel area, between the contacts.

[0115] The spectral dependence of the photocurrent, as shown in FIG. 4B, correspond to the absorption peaks of SL-MoS.sub.2 [13] and S.sub.22 [23] peaks of s-SWCNTs, which demonstrates that this novel heterointerface can induce carrier separation following exciton and/or free carrier generation in either material.

[0116] To further illustrate the photoresponse of the s-SWCNT/SL-MoS.sub.2 heterojunction, both output curve (I-V) and transfer curve (I-V.sub.g) were acquired under global illumination at a series of wavelengths. A representative comparison of the dark (361) and illuminated (362) I-V curves at V.sub.G=40 V reveals that the photocurrent increases by 4 orders of magnitude at a heterojunction reverse bias of 5 V, as shown in FIG. 4C. FIG. 4D also shows the gate voltage dependent photocurrent values at a heterojunction reverse bias of 10 V. As the gate voltage becomes more negative, the relative contribution from the s-SWCNT portion of the spectrum decreases, which is consistent with the s-SWCNT/SL-MoS.sub.2 heterojunction becoming a p.sup.+-n.sup. junction. This decrease could be due to a reduction in the rate of charge transfer due to changes in Fermi level differences across the heterojunction or a decrease in the depletion of the s-SWCNTs adjacent to the heterojunction leading to reduced efficiency of electron extraction.

[0117] With a strong photoresponse, the s-SWCNT/SL-MoS.sub.2 heterojunction can be exploited as a photodetector. Diode-based photodetectors are known for their fast photoresponse times compared to phototransistors since the photoexcited carriers must only traverse a distance equal to the depletion width of the junction. Indeed, a fast photoresponse, less than about 15 s, was observed from the s-SWCNT/SL-MoS.sub.2 heterojunction, as shown in FIGS. 5A and 5B. Importantly, this photoresponse time is orders of magnitude smaller than recently reported heterojunction phototransistors based on graphene [24]. Furthermore, the s-SWCNT/SL-MoS.sub.2 heterojunction photoresponse time observed here is limited by the rise time of the preamplifier used in the experiment, and thus 15 s represents an upper bound.

Responsivity and Quantum Efficiency

[0118] The external quantum efficiency (EQE) of the s-SWCNT/SL-MoS.sub.2 heterojunction photodetector is also noteworthy (about 25% at V.sub.D=10 V) and compares favorably to other recently reported 2D nanomaterial heterostructures, as shown in FIG. 5C [24-26].

[0119] The EQE is calculated as

[00002]$E.Math..Math.Q.Math..Math.E=\frac{I_{\mathrm{ph}}/e}{P/\mathrm{hv}}100,$

where I.sub.ph, e, P, and hv represent the photocurrent, electronic charge, incident optical power, and photon energy, respectively. The photocurrent was extracted by subtracting the dark I-V curves from the illuminated I-V curves. The responsivity (R) was calculated using R=EQEx1.24/, where is in m.

[0120] The linear rise in EQE at low reverse biases shown in FIG. 5C is similar to the behavior of quantum dot (QD) based photodiodes [27], which was related to changes in the depletion region. Here, given the negligible thickness of SL-MoS.sub.2 compared to the expected depletion width [28], the increasing EQE is attributed to an increase in the rate of charge transfer across the heterojunction interface due to the change in band alignment, rather than an increase in the depletion width. The spectral responsivity (R) of the heterojunction photodetector is presented in FIG. 5D. The highest R exceeds 0.1 A/W at a wavelength of 650 nm, which is comparable to other nanostructured diode-based photodetectors in the literature [29]. The combination of high R and fast photoresponse time presents advantages over currently available organic and QD photodiodes [27].

Power Dependence of Photocurrent

[0121] The power dependence of the photocurrent was measured under zero bias using the same illumination system. The power dependence is sub-linear which is consistent with bimolecular recombination of electrons and holes, further implying that the concentration of photogenerated carriers is similar to or greater than the intrinsic carrier concentration [33]. FIG. 12 shows power dependence of the photocurrent under zero applied bias. The line 1110 is a linear fit to the data showing a slope of 0.73.

[0122] In sum, the present invention recites, among other things, a gate-tunable p-n heterojunction diode through the integration of p-type s-SWCNTs and n-type SL-MoS.sub.2. The ultrathin nature of the constituent materials implies that both components can be modulated by a capacitively coupled gate bias, thereby enabling wide tunability of charge transport from a nearly insulating state to a highly rectifying condition with forward-to-reverse bias current ratios exceeding 10.sup.4. When operated as a three-terminal device, the p-n heterojunction diode also shows anti-ambipolar behavior with current on/off ratios greater than 10.sup.4, suggesting its utility in advanced logic applications. Furthermore, since s-SWCNTs and SL-MoS.sub.2 are direct band gap semiconductors, the p-n heterojunction diode serves as an effective photodetector with fast photoresponse less than about 15 s. By combining other chirality-resolved s-SWCNTs [30] with the growing list of 2D semiconductor nanomaterials [14], the p-n heterojunction diode can be generalized to a wide range of electronic and optoelectronic applications.

[0123] The foregoing description of the exemplary embodiments of the invention has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.

[0124] The embodiments were chosen and described in order to explain the principles of the invention and their practical application so as to enable others skilled in the art to utilize the invention and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the invention pertains without departing from its spirit and scope. Accordingly, the scope of the invention is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.

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