Abstract
In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.
Claims
1. A top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate comprising: a source electrode disposed on a bottom surface of the semiconductor substrate; a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate; and at least a trench filled with a metal as a conductive material and extending vertically from the body region near the top surface of the semiconductor substrate downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.
2. The TD-LDMOS device of claim 1 wherein: the semiconductor substrate comprising a P+ substrate supporting a P epitaxial layer for forming the source and drain regions of an N type dopant near the top surface of the semiconductor substrate.
3. The TD-LDMOS device of claim 1 wherein: the trench is further filled with the conductive material comprising a selective epitaxial growth (SEG) of silicon or a SEG of silicon-germanium (SiGe).
4. The TD-LDMOS device of claim 2 wherein: the trench is further filled with the conductive material comprising a heavily doped P++ selective epitaxial growth (SEG) of silicon or a SEG of silicon-germanium (SiGe).
5. The TD-LDMOS device of claim 1 further comprising: a heavily doped liner implant region disposed below the bottom of the trench and surrounding sidewalls of the trench.
6. The TD-LDMOS device of claim 2 further comprising: a P++ liner implant region disposed below the bottom of the trench and surrounding the sidewalls of the trench.
7. The TD-LDMOS device of claim 7 wherein: the trench is filled with tungsten as the conductive material in the trench.
8. The TD-LDMOS device of claim 1 wherein: the trench further comprises a metal liner layer formed on a bottom surface of the trench.
9. The TD-LDMOS device of claim 1 wherein: the trench is a narrow and deep trench having a high depth to width ratio ranging from 10 to 25.
10. The TD-LDMOS device of claim 1 wherein: the TD-LDMOS device is configured to have a closed cell layout.
11. The TD-LDMOS device of claim 1 wherein: the semiconductor substrate further comprising a heavily doped layer having an opposite conductivity type from a conductivity type of the body region.
12. The TD-LDMOS device of claim 1 wherein: the semiconductor substrate further comprising a deep buffer layer implanted with dopant with a same conductivity type as a conductivity type of the body region.
13. The TD-LDMOS device of claim 1 wherein: the TD-LDMOS comprises a P-channel device formed in an N+Si substrate.
14. The TD-LDMOS device of claim 1 wherein: the planar gate further comprises a stacked planar gate padded underneath by a gate oxide layer and covered by a gate cap oxide and further surrounded by a side spacer layer.
15. The TD-LDMOS device of claim 14 further comprising: a gate shield layer comprises a metal layer covering over the gate cap oxide and side spacer layer wherein the gate shield layer further extends to a top surface above the source region and processed as a salicide layer for conductively interfacing between the source region and a top metal source.
16. A semiconductor power device comprising: a gate disposed on a top surface of a semiconductor substrate for controlling a current path between a source region and a drain region disposed near the top surface of the substrate; and a trench filled with a metal as a material and extends downwardly for shorting the source region to a source electrode disposed on a bottom surface of the substrate.
17. A method for manufacturing a semiconductor power device on a semiconductor substrate comprising: forming a body region encompassing a source region and a drain region with a gate on a top surface of the semiconductor substrate for controlling a lateral current path in the body region between the source region and a drain region near the top surface of the semiconductor substrate; and opening a trench extending from the body region downwardly to a source electrode on a bottom surface of the semiconductor substrate and filling the trench with a conductive material to function as a body-source interconnect.
18. The method of claim 17 wherein: the step of filling the trench with a conductive material comprises a step of filling the trench with the conductive material comprising a selective epitaxial growth (SEG) of silicon or a SEG of silicon-germanium (SiGe).
19. The method of claim 18 further comprising: implanting a heavily doped liner region below the bottom of the trench and surrounding sidewalls of the trench.
20. The method of claim 17 wherein: the step of filling the trench with a conductive material comprises a step of filling the trench with a metal.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1A is a cross sectional view of a conventional lateral diffusion MOS (LDMOS) device with a bottom source used for RF base station amplifier.
[0021] FIG. 1B is a cross sectional view of bottom source LDMOS with diffused sinker region disclosed in a referenced patent.
[0022] FIG. 2A is a cross sectional view of a top drain LDMOS device with trench body-source short structure as an embodiment of this invention.
[0023] FIG. 2B is a cross sectional view illustrating a whole TD-LDMOS device cell that can be arranged in a closed cell configuration.
[0024] FIG. 2C is a top view illustrating a whole TD-LDMOS device cell that can be arranged in a closed cell configuration.
[0025] FIG. 3 is a cross sectional view of another top drain LDMOS device as another embodiment of this invention.
[0026] FIGS. 4A to 4L are a serial cross sectional views for describing the manufacturing processes to fabricate a TD-LDMOS device of this invention.
DETAILED DESCRIPTION OF THE METHOD
[0027] Referring to FIG. 2A for a cross sectional view of an N-channel inverted top drain and ground-source trenched FET device with a top drain and a bottom source of this invention. The inverted top-drain ground-source N-channel FET device is supported on a P+ substrate 105 functioning as a bottom source electrode. Alternatively, a P-channel device may be formed over an N+ Si substrate. A layer of Pepitaxial layer 110 is supported on top of the substrate 105. The substrate is configured with an active cell area and a termination area typically disposed on the peripheral of the substrate. A deep trench 120 with a high aspect ratio is opened through the epitaxial layer 110 and extending downwardly to the substrate 105. Selective epitaxial growth (SEG) of silicon or SEG of silicon-germanium (SiGe) with a heavily P doped P++ is performed to fill the deep trench 120 forming a self-aligned source/body contact functioning as an ultra-low resistive local interconnect from source to body and to the substrate. For the purpose of improving the contact, a P++ liner implant region 128 is formed with angled P++ implant below the bottom of the trench and surrounding the sidewalls of the source-body interconnect trench 120 before the P++ conductive trench filling material is filled in the trench. A body region 115 is formed in the upper portion of the epitaxial layer 110 that extends laterally to a drain drift region 125. The P-dopants in the body region 115 compensate some of the Ndopant in the accumulation of the transistor for tailoring a dopant profile of N-drift region 125 to minimize the gate-drain capacitance while maintaining a low drain to source resistance Rdson. The deep trenched source-body interconnect 120 further extends vertically both downward to the bottom P+ substrate 105, and upward to the body region 115. Part of the body region 115 forms a channel at a top surface under a gate oxide 135. The deep trenched source-body interconnect 120 has a narrow opening and high aspect ratio such that the cell pitch can be reduced without requiring a sinker region that is formed with a lateral diffusion expansion for the purpose of extending the sinker region to a greater depth to reach the bottom source region 105.
[0028] A stacked planar gate 140 surrounded by a gate spacer 165 and covered by a gate shield metal 170-G is disposed above the gate oxide layer 135 formed on the top surface between the source region 160 and the drain drift region 125. The gate 140 thus controls the current flow between the source region 160 and the drain drift region 125 through the channel form by body region 115 under the gate140 to function as a lateral MOS device. The drain drift region 125 is disposed below a field oxide 130 covered by a BPSG layer 180 and optionally a passivation layer 185. A drain contact opening is etched through the passivation layer 185 and the BPSG layer 180 for the top drain metal 199 to contact the drain region 125 via a contact N+ dopant region 190 with reduce contact resistance. The stacked gate 140 with the oxide 130 and 135 below the stacked gate 140 as shown may be formed by different methods. The methods include the processes of growing or depositing the oxide and etching from the channel region or by using a LOCOS type of oxidation process. The stacked gate 140 has a longer gate length and field plating over the drain extension without increasing the cell pitch. The stacked gate 140 controls the link for current to flow between the channel and the drain under the gate oxide 135 and field oxide 130 with reduced gate-drain capacitance. The stacked gate 140 is surrounded by insulation spacer 165 and surrounded by a buried gate shield 170-G that further includes a salicide portion 170-S for body-source contact and to further reduce the gate to drain capacitance Cgd with the gate shield layer 170-G shields the drain metal 199 covering over the top surface. For better mechanical and electrical performance, a barrier Ti/TiN liner layer 198 is further formed between the drain contact region 190 and the drain metal 199. The half pitch of the cell is significantly reduced with the self-aligned source-body interconnected formed as trench interconnect 120 filled with the selective epitaxial growth (SEG) P++ Si or SEG P++ SiGe such that no sinker diffusion is required.
[0029] FIG. 2B is a cross-sectional view illustrating a whole cell of the TD-LDMOS device of this invention, which can be arranged in a closed cell configuration. As shown in FIG. 2B, both sources of the half-cell pitch are grounded, thus space savings are achieved because there is no need to provide the extra space for termination area for this TD-LDMOS device. FIG. 2C is a top view of a whole cell of the TD-LDMOS device of this invention, which can be arranged in a closed cell configuration.
[0030] FIG. 3 is another exemplary embodiment of the TDLDMOS device that is similar to the device shown in FIG. 2. The only difference is that the device is formed on a heavily doped N++ substrate 101 to substantially reduce the series resistance. The P+ epitaxial layer 105 functioning as a bottom source electrode is formed on top of the N++ substrate 101 and shorted to the N++ substrate, thus reduce the resistance of the substrate. Furthermore, as an optional, a deep buffer layer 115 is formed within the P epitaxial layer 110 at a predetermined depth and above the P+ source layer 105 for the purpose of breakdown voltage (BV) adjustment and sub-surface punch-through prevention due to thermal cycles as that required in the manufacturing processes. In this embodiment, the deep trench 120 opens through the Pepitaxial layer 110 and the P+ source layer 105 extends downwardly to the N++ substrate 101. As that described above in FIG. 2A, the deep trench 120 has a high aspect ratio and is filled with a heavily P doped P++ conductive material such as selective epitaxial growth (SEG) of silicon or SEG of silicon-germanium (SiGe). Alternatively, the deep trench 120 can be filled with P++ poly or with a metal, such as tungsten, with a metal liner 129, for example salicide Ti/TiN, forming an ultra-low resistive local interconnect between the drain and the source. The passivation layer 185 can be omitted with this device configuration.
[0031] FIGS. 4A to 4L are a series of cross sectional views to illustrate the manufacturing processes for making a device structure as shown in FIGS. 2A and 3. As will be understood from the disclosures made in through the descriptions of the manufacturing steps, the processes only require six masking steps because of a beneficial Self-Aligned Structure. As shown in FIG. 4A, the processes start with a starting silicon substrate that includes a P+ substrate 205 doped with Boron with a resistivity of 3 to 5 mOhm-cm or a lower resistivity. The substrate 205 is preferably along a <100> crystal orientation as a standard prime. A P epitaxial layer 210 is formed on the substrate 205 with a thickness ranging from 2 to 7 micrometers and typically doped with a low dosage of 5E14 to 5E15 for 20-60 volts application. In another embodiment, the epitaxial layer 210 may be an N doped layer.
[0032] In FIG. 4B, a pad oxide layer 212 is grown for a nitride deposition step later in process. As an optional processing step, a blanket deep buffer layer implant with an implant dose of 1E14 at an implant energy of approximately 600 KEV is performed to form a deep buffer layer 215 for the purpose of breakdown voltage (BV) adjustment and sub-surface punch-through prevention between the N-drift layer, formed in later process, and P+ substrate 205 due to thermal cycles as that required later on when subsequent manufacturing processes are carried out. It can be a lightly doped blanket P implant to increase the P doping to avoid punch through or it can be a lightly doped N-implant for an N-epi.
[0033] A nitride deposition is carried out on top of the pad oxide layer 212 and then etched using an active mask, first mask, which is not shown, to protect the channel region and expose the drain extension region during the subsequent processing. An N-drift implant is performed in the regions not protected by nitride at a zero degree tilt to form the N-drift region 225 as shown in FIG. 4C. The N-drift region 225 can be formed by implanting Phosphorous with an implanting energy ranging between 60 Kev to 200 Kev and a dosage ranging from 5E11 to 2E13 and preferably a dosage of 3E12 for 30V application. This step results in a self-aligned n-type drift implant (for NMOS) in the drift drain extension of the LDMOS device, region 225. This is followed by a standard field oxidation process (referred to as LOCOS), with optional N2 drive step, to form mold oxide region 230 atop of the N-drift region 225. Temperature can be in the range of 900 to 1100 C. to grow an oxide with a thickness in the 0.3 to 1 micron range, with a preferred thickness of about 0.55 microns.
[0034] Nitride (not shown) and the pad oxide 212 are stripped followed by a sacrificial oxide layer growth and strip (not shown) to clean the surface of the structure. In FIG. 4D, a gate oxide layer 235 is grown followed by depositing a polysilicon layer or preferably a polycide layer 240 having a thickness up to 2000 to 6000 Angstroms for forming a gate. Then the N+ dopant ions are implanted to the Polysilicon layer and an optional WSix layer is formed on top for providing a low gate resistance contact layer. Note the poly can be in situ doped or doped using POCl.sub.3 as well. An oxide cap deposition by using a HTO or LTO process is carried out to deposit an oxide cap layer 245 on top of the polysilicon layer 240. The oxide cap layer 245 has a thickness of about 500 to 4500 Angstroms on top of the polysilicon layer 240. A gate mask, i.e., a second mask (not shown), is applied to etch and pattern the oxide cap layer 245 and the gate layer 240. An oxide etch is first performed to pattern the oxide cap layer 245 followed by a polysilicon or polycide etch. The polysilicon or polycide etch is stopped on top of the gate oxide layer 235 and the field oxide 230 as shown.
[0035] In FIG. 4E, a blanket shallow body high angle implantation of boron (high angle implantation to introduce channel under the gate) with a dosage range between 1E12 to 1E14, preferably at a dose of 1E13, is carried out to form the P-body region 250. Optionally, the blanket shallow body implantation at zero angle and higher energy body implant is also carried out to form P-body region 250. With the field oxide 230, the gate 240 and oxide cap 245 stack-structures, the boron ions are implanted only in the source side of the gate. Then a body drive is performed with an elevated temperature ranging between 950 to 1150 degrees Celsius and preferably at 1050 degree Celsius for approximately 60 minutes. In FIG. 4F, a blanket shallow source-implant, for example As dopant ions implanted with a dosage ranging between 1E15 to 1E16, preferably at 4E15, is carried out to form N+ source region 260. Then a source annealing operation at an elevated temperature ranging between 850C. to 1000C. and preferably 950C. is performed for 30 minutes. Some oxygen may be used during the source anneal annealing process depending on the gate stack to form poly oxide side wall on the edges of the stacked gate 240.
[0036] In FIG. 4G, a spacer oxide layer 265 is deposited, which is preferably a conformal oxide layer having a thickness ranging between 1000 to 4000 Angstroms and preferably more than 3000 Angstroms to function as a hard mask for body trench etch and isolation for selective epitaxial growth (SEG) and also to passivate gate sidewall in subsequent manufacturing processes. Then a source-body local interconnect trench mask, i.e., third mask, (not shown), is applied then an oxide etch followed by a silicon etch is performed to open a trench 255 with a narrow opening and high aspect ratio with a trench depth extends downwardly to reach the P+ substrate 205. Then the photoresist (not shown) is removed. A blanket P++ implant at a seven degree tilt implant angle is
[0037] optionally carried to implant heavily doped P++ into the trench bottom, also to the sidewall of the trench (not shown), to form the liner implant region 258 for better contact. In FIG. 4H, a selective epitaxial growth (SEG) of Si or SiGe with highly doped P++ is performed, preferably a SEG of SiGe doped with P++ boron, to form an ultra-low resistive local interconnect 220 from source 260 to body layer 250 and deep buffer layer 215 and to the substrate 205. In FIG. 4I, an oxide spacer etch is carried out by performing a reactive ion etch (RIE) to form the gate spacer 265 to passivate gate sidewalls with minimal over etch to assure that there is oxide, 230 and 245, left below the polysilicon gate 240 and on the drain extension.
[0038] In FIG. 4J, a slight wet oxide etch is performed to remove the oxide on top of the N+ source regions 260. Ti or Co is then deposited on top surface of the silicon to form Ti or Co layer 275. Then, a first salicide formation process is carried out by applying a first rapid thermal annealing (RTA) process to form TiSi or CoSi layer 275 on the top surface of the silicon and Ti/TiN layer 275 on top of the oxide layers 265, 245 and 230. The process is continued by applying a gate shield mask, i.e., fourth mask (not shown), followed with a Ti/TiN wet etch to form the gate shield 275. This mask is not required if the gate shield is not needed. Then the photoresist is removed followed by carrying out a second salicide formation also carried out with RTA to form TiSi2 or CoSi2 layer 275 on the top surface of the silicon. The silicidation processes form a self-aligned body-source interconnects with good contact and low resistance and a good gate shield metal with good insulation.
[0039] In FIG. 4K, an ILD0 material including oxide, nitride or oxy-nitride is deposited to form the insulation layer 280 followed by applying a drain and gate mask (not shown), i.e., fifth mask, to open the gate contact opening (not shown) and drain contact openings 285 over the insulation. layer 280. A low energy contact implant with phosphorus ions with an implant dosage between 5E14 to 1E16 is performed to form the low resistance contact regions 290 followed by an annealing process preferably using RTA with temperature between 700-900 C. in N2 and for a time of 20 sec to 5 minutes, preferably 1 minute. In FIG. 4L, a thick metal deposition with Ti/TiN liner is carried out to form the drain metal 295 with barrier metal layer 298. Then a metal mask, i.e., sixth mask (not shown), is applied to perform a metal etch to form the gate metal and the drain metal on the top surface followed by removing the photoresist, cleaning up and an alloy process to complete the manufacturing processes.
[0040] In another embodiment, which is not shown, the process start with a heavy doped N++ silicon substrate, then a P+ source epitaxial layer is formed on the N++ substrate followed by a growth of a P epitaxial layer on the P+ source epitaxial layer. The following steps are similar to the process steps described above in FIGS. 4B-4K except that the trench 255 extends downwardly through the Pepitaxial layer and the P+ source epitaxial layer to reach the N++ substrate.
[0041] According to above device configuration, a low manufacturing cost is achieved because a lower effective die cost can be achieved by using a small die by reducing the cell pitch with the trenched source body interconnect without lateral diffusion of the sinker connect region. This reduced cost is able to offset the higher manufacturing costs. Most importantly, a low source inductance is achieved through the use of a substrate source contact while minimizing the source resistance by implementing the source-body interconnect structure surrounded with P++ liner implant regions. Furthermore, a small pitch of the device as described above further reduces the specific-on-resistance (Rsp) for a given operating voltage. The device configuration is conveniently scalable for compatible designs and operations adaptable to devices that require a range of high and low voltages.
[0042] Therefore, the top drain LDMOS device with an inverted ground-source as disclosed allows for vertical current through vertical channel with controllable drift length of the drift region implemented with the vertical channel enable the manufactures of small and scalable cell pitch. With the source contact at the bottom of the trench in direct contact with the highly doped substrate reduces the source resistance. There is no longer a need for deep resistive sinker region or trench contact as that usually implemented in the conventional bottom source FET devices.
[0043] Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.
