DUMMY GATE USED AS INTERCONNECTION AND METHOD OF MAKING THE SAME

Abstract

Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Claims

1. A device comprising: a semiconductor substrate; a plurality of real gate structures disposed over the semiconductor substrate; a metallization layer disposed over the real gate structures; and a first dummy gate structure including a single sidewall spacer on a first side of the first dummy gate structure and a first gate contact over the first dummy gate structure, the first gate contact connected to a source/drain region on a second side.

2. The device according to claim 1, further comprising: a second dummy gate structure including a single sidewall spacer on a second side of the second dummy gate structure and a second gate contact over the second dummy gate structure, the second gate contact connected to a source/drain region on a second side.

3. The device according to claim 2, wherein the first and second gate contacts are filled with tungsten, tungsten alloy, copper, aluminum-copper alloy, or silicon-copper alloy.

4. The device according to claim 2, wherein the first and second dummy gate structures are formed over first and second shallow trench isolation regions.

5. The device according to claim 2, wherein the first dummy gate structure is formed in a PFET region of the semiconductor substrate.

6. The device according to claim 5, wherein the second dummy gate structure is formed in a NFET region of the semiconductor substrate.

7. The device according to claim 6, wherein the first or second dummy gate structure connects an NFET source/drain region and a PFET source/drain region.

8. The device according to claim 2, wherein the first dummy gate structure is formed at a first edge of a cell.

9. The device according to claim 8, wherein the second dummy gate structure is formed at a second edge of the cell.

10. A device comprising: a semiconductor substrate; a plurality of real gate structures formed over the semiconductor substrate; a metallization layer formed over the real gate structures; a first dummy gate structure including a single sidewall spacer on a first side of the first dummy gate structure and a first gate contact over the first dummy gate structure, the first gate contact connected to a source/drain region on a second side; and a second dummy gate structure including a single sidewall spacer on a second side of the second dummy gate structure and a second gate contact over the second dummy gate structure, the second gate contact connected to a source/drain region on a second side, wherein at least one real gate structure is formed between the first and second dummy gate structures, and wherein the metallization layer is formed over the first and second gate contacts.

11. The device according to claim 10, wherein: the first dummy gate structure is formed on a PFET side of the semiconductor substrate; and the second dummy gate structure is formed on a NFET side of the semiconductor substrate.

12. The device according to claim 11, wherein: the first dummy gate structure is formed over a first shallow trench isolation (STI) region; and the second dummy gate structure is formed over a second STI region.

13. The device according to claim 10, wherein the first and second gate contacts are fat or shifted gate contacts on the first and second dummy gate structures.

14. The device according to claim 10, wherein a first source/drain structure of the first dummy gate structure is connected with a second source/drain structure of the second dummy gate structure.

15. The device according to claim 10, wherein at least one of the real gate structures is disposed between a source region and a drain region.

16. The device according to claim 10, wherein the first dummy gate structure is formed at a first edge of a cell.

17. The device according to claim 16, wherein the second dummy gate structure is formed at a second edge of the cell.

18. A device comprising: dummy gate structures formed at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; first and second expanded gate contact trenches formed by simultaneously removing a first sidewall spacer on a first side of a first dummy gate structure and etching a first gate contact trench over the first dummy gate structure and removing second sidewall spacer on a second side of a second dummy gate structure and etching a second gate contact trench over the second dummy gate structure; real gate structures formed between the first and second dummy gate structures, wherein the first and second expanded gate contact trenches are filled with tungsten, tungsten alloy, copper, aluminum-copper alloy, or silicon-copper alloy respectively connecting the first and second gate contacts with first and second source/drain regions.

19. The device according to claim 18, wherein: the first dummy gate structure is formed on a PFET side, and the second dummy gate structure is formed on a NFET side.

20. The device according to claim 18, wherein: the first dummy gate structure is formed over a first shallow trench isolation (STI) region, and the second dummy gate structure is formed over a second STI region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

[0017] FIG. 1 schematically illustrates a cross sectional view of a conventional process of using a dummy gate structure to define a STI region;

[0018] FIG. 2 schematically illustrates a conventional integrated circuit layout using dummy gate structures at edges of adjacent cells to define a STI region;

[0019] FIG. 3 schematically illustrates a cross sectional view of a gate contact etch of a dummy gate structure, in accordance with an exemplary embodiment;

[0020] FIG. 4 schematically illustrates a cross sectional view of a gate contact etch of dummy gate patterns in PFET and NFET regions, in accordance with an exemplary embodiment;

[0021] FIGS. 5A and 5B schematically illustrate integrated circuit layouts, in accordance with an exemplary embodiment; and

[0022] FIG. 6 schematically illustrates an integrated circuit layout, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

[0023] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term about.

[0024] The present disclosure addresses and solves the current problem of M1 design congestion attendant upon scaling down cell size in advanced technology nodes. By using a dummy gate structure as an interconnection without additional processing steps, space can be freed up in M1 design layout. The color of M1 can be reassigned after more space becomes available and printability is improved.

[0025] Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

[0026] Adverting to FIG. 3, plural gate structures, for example 101a, 101b are formed over a substrate 100. Gate structure 111 is a dummy gate structure formed at an edge of a cell region. A cavity 110 is created over the dummy gate structure 111, for forming a gate contact, by etching through a oxide layer/dielectric layer 105 and interlayer dielectrics (ILDs) 109 and the cap layer 115 (FIG. 1). The formation of the cavity 110 also removes the cap 115 and sidewall spacer closest to the cell edge and leaves behind only one of the sidewall spacers of the dummy gate structure 111. Each of the real gate structures 101a, 101b is formed between source/drain regions 108. Each dummy gate will only have one source/drain region on one side and the other side is empty.

[0027] FIG. 4 schematically illustrates a cross sectional view of a plurality of gate structures in PFET and NFET regions of a cell after a metal filling step is formed to produce metal gate structures. During the etching of the dielectric, ILDs 402 and a part or all of the cap layer 115 (FIG. 1) to form gate contact trenches, a sidewall spacer and cap on a cell edge side of a dummy gate structure 411 in the PFET region is removed leaving only one sidewall spacer. During the same etching step, the sidewall spacer and cap on the opposite cell side of a dummy gate structure 416 in the NFET region is removed leaving only one sidewall spacer. The etching step for forming the gate contact trenches and for removing one of the sidewall spacers of each dummy gate is a nitride type etch. Also during the same etch, gate contact trenches for real gate structures 401a and 401b (PFET side) are also formed, but with both sets of sidewall spacers remaining for the real gate structures 401a and 401b. Also during the same etch, gate contact trenches for real gate structures 401c and 401d (NFET side) are also formed, but with both sets of sidewall spacers remaining for the real gate structures 401c and 401d.

[0028] The gate contact trenches for dummy gate structures 411, 416 are filled with a metal 414, 417 to respectively form gate contacts for the gate structures at the edges of the PFET and NFET regions. Further, contact trenches for real gate structures 401a, 401b, 401c, and 401d are also filled with metal 418. The contact to the active region (i.e., source/drain region) 408 is connected with the gate contact 414 formed over adjacent STI region 412 in PFET region. Similarly, the contact to the active region (i.e., source/drain region) 410 is connected with the gate contact 417 formed adjacent STI region 413 in the NFET region. The metal in each 414, 415, 418 and 417 is the same. Metal layer 415 is subsequently removed after the trench fill by a planarizing technique such as chemical mechanical planarization (CMP). Metallization layers can be formed after the CMP.

[0029] Adverting to FIG. 5A, an integrated circuit layout 500a is illustrated. Cells 501 and 502 are disposed between power rails 503. When a dummy gate electrode 504 and a via 505 to the source/drain regions are connected in the circled regions of FIG. 5A, M1 is needed at, for example, 506. Metal 506 is used to connect source drain 505 to 508 using via 505.

[0030] FIG. 5B illustrates integrated circuit layout 500b with the dummy gate used as an interconnection by forming a fat or shifted gate contact 505 connected to source/drain 507 in the circled regions of cells 501 and 502. Connection between 507 and 508 is established by dummy gate and shifted gate contact 505. Metal line is no longer needed. The color of M1 can be reassigned after more space becomes available as a result of the dummy gate being used as an interconnection. Printability is improved as compared with the layout in FIG. 5A.

[0031] Adverting to FIG. 6 integrated circuit layout 600 is illustrated in which fat or shifted gate contacts 601, 602 are formed on dummy gate structures, connected to source/drain contacts 603. Accordingly, the M1 colors have been reassigned.

[0032] The embodiments of the present disclosure can achieve several technical effects, such as mitigating congestion in M1 design layout by using a dummy gate as an interconnection. Devices formed in accordance with embodiments of the present disclosure enjoy utility in various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in the manufacture of any of various types of highly integrated semiconductor devices using a dummy gate as an interconnection particularly for the 10 nm, 7 nm technology nodes and beyond.

[0033] In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.